diff --git a/bat/BLDLIB.BAT b/bat/BLDLIB.BAT index 21216341b..ae6be8994 100644 --- a/bat/BLDLIB.BAT +++ b/bat/BLDLIB.BAT @@ -20,9 +20,9 @@ call bat\asm %z_TraceMode% linklib\FPCONMFC bal notiming stats || goto e call bat\asm %z_TraceMode% linklib\CVTTOHEX bal notiming stats || goto error call bat\asm %z_TraceMode% linklib\SQXTR bal notiming stats || goto error call bat\asm %z_TraceMode% linklib\DAT bal notiming stats || goto error -call bat\asmlg %z_TraceMode% linklib\IEFBR14 sysobj(+linklib) || goto error -call bat\asmlg %z_TraceMode% linklib\TESTFPC1 sysobj(+linklib) || goto error -call bat\asmlg %z_TraceMode% linklib\TESTFPC2 sysobj(+linklib) || goto error +call bat\asmlg %z_TraceMode% linklib\IEFBR14 sysobj(+linklib) stats || goto error +call bat\asmlg %z_TraceMode% linklib\TESTFPC1 sysobj(+linklib) stats || goto error +call bat\asmlg %z_TraceMode% linklib\TESTFPC2 sysobj(+linklib) stats || goto error call bat\asm %z_TraceMode% linklib\RTGENDIR noasm bal notiming stats sysparm(RTGENDIR) || goto error call bat\asm %z_TraceMode% linklib\RTGENCMP noasm bal notiming stats sysparm(RTGENCMP) || goto error diff --git a/doc/contributing/contribute_code.md b/doc/contributing/contribute_code.md index b36f35f56..7fa709d68 100644 --- a/doc/contributing/contribute_code.md +++ b/doc/contributing/contribute_code.md @@ -71,6 +71,7 @@ Action | Command ------------------------------------------|------------ get a list of gradlew command options | gradlew --help force a test run | gradlew test -—rerun +execute a specific test | gradlew test --tests RunAsmTests.test_TESTASC1 ## Proposing new functionality diff --git a/doc/user_guide/z390/commands.md b/doc/user_guide/z390/commands.md index f7d6e2091..eb39bb939 100644 --- a/doc/user_guide/z390/commands.md +++ b/doc/user_guide/z390/commands.md @@ -77,30 +77,36 @@ The ez390 emulator supports the following interactive test commands when the * `addr=sdt` – set memory value (i.e. 1r?=x'80' changes mem at (r1) 31 bit * `reg=sdt` - set register value (i.e. 15r=8 changes reg 15 to 8) -* `A addr` – set or reset up to 100 instruction address stops with hex address or relative expression such as *+4 -* `B=addr` - set base for rel addr (ie B=15r% sets base to (r15) 24 bit -* `D` – display DCB file information from TIOT -* `E` – toggle between EBCDIC and ASCII mode -* `F` – display floating point registers F0-FF -* `G` - nn/addr/opcode - exec nn instr. or until specified instruction address or opcode is found with no trace. One instruction is always executed before next opcode break even if it’s the same instruction such as a BCT 1,*. Addresses are distinguished from count by hex . or relative expression term such as *, +, or -. -* `H` - list help command summary +* `A addr` – add/remove address stop (ie A FF348. or A *+4 etc.) +* `AR nn` - display specified access register else all AR0-AR15 +* `B=addr` - set base for rel addr (i.e. B=15r% sets base to (r15) 24 bit +* `D` – display DCB file status, DDNAME, and DSNAME information +* `E` – toggle EBCDIC/ASCII mode for dumping storage etc. +* `F nn` – display specified floating point registers else all FPR0-FPR15 +* `G` - nn/addr/opcode - exec nn instr. or until specified instruction address or opcode is found with no trace. One instruction is always executed before next opcode break even if it’s the same instruction such as a BCT 1,*. Addresses are distinguished from count by hex . or relative expression term such as *, +, or -. +* `H` - list help command summary * `J addr` - jump to new addr and trace instruction -* `L` - list all regs and trace current instruction -* `L reg` - list contents of register (ie l 1r dumps register 1 +* `L` - list all regs and trace current instruction +* `L reg` - list contents of register (i.e. l 1r dumps register 1 * `L addr len` - list contents of memory area (ie l 10. 4 dumps cvt addr -* `M` – display total memory in MB and total allocate and free bytes - * `P` – display current loaded program information from CDE including name, entry and length - * `Q` - quit execution now - * `R` – display general purpose registers R0-RF -* `S` - clear register, address, and memory breaks -* `S reg??sdt` - set break on register change +* `M` – display total memory in MB and total allocated and free bytes +* `P` – display current loaded program information from CDE including name, entry and length +* `PSW` - display current PSW +* `PSW+` - display current PSW in verbose mode +* `PSW16` - display 16 byte current PSW +* `Q` - quit execution now +* `R nn` – display specified general purpose register else R0-R15 +* `S` - clear register, address, and memory breaks +* `S reg??sdt` - set break on register change * `S addr??sdt` - set break on memory change -* `T nn/addr/opcode` - trace n instr. or until specified instruction address or opcode is found. One instruction is always executed before next opcode break even if it’s the same instruction such as a BCT 1,*. Addresses are distinguished from count by hex . or relative expression term such as *, +, or -. The symbol EPA may be used in place of address to refer to last program load point address. -* `V` - validate/verify +* `T nn/addr/opcode` - trace n instr. or until specified instruction address or opcode is found. One instruction is always executed before next opcode break even if it’s the same instruction such as a BCT 1,*. Addresses are distinguished from count by hex . or relative expression term such as *, +, or -. The symbol EPA may be used in place of address to refer to last program load point address. +* `V op1 = op2` - validate/verify + * `op1` - addr len | reg[.+offset] [length] | psw.[cc | mask | amode | key | addr] + * `op2` - addr len | reg[.+offset] [length] | sdt * `V * nn` - validate nn bytes starting at PSW address * `V psw.subfield` - validate PSW subfield * `V nnr` - validate GPR nn -* `Z` - exit test and run to end of program without trace +* `Z` - run to end of program without trace and exit * `* addr` = hex.,+-hex, *+-hex, dec, nnr% (24 bit), nnr? (31 bit) * `* reg` = nnr where nn = 0-15 * `* sdt` = self defining term (b'01',c'ab',f'1',h'2',x'ff') diff --git a/rt/mlc/TESTASC1.MLC b/rt/mlc/TESTASC1.MLC index 63da96297..0a305d259 100644 --- a/rt/mlc/TESTASC1.MLC +++ b/rt/mlc/TESTASC1.MLC @@ -50,6 +50,7 @@ * 01/25/11 RPI 1139 C2X ARG IN QUOTES FOR NOALLOW * 2022-05-03 update copyright, add to z390\rt\mlc, fix SETC '&&' to '&' * 2022-05-07 replace TESTSUB1 with CVTTOHEX to remove dependency +* 2023-07-30 #504 bring floating point special values in line with HLASM/PoP ********************************************************************* PRINT DATA TESTDC1 RT1 MAIN @@ -107,16 +108,16 @@ LEN EQU X'5678' RT1 CCE,=LS2'1',=X'43100000000000003500000000000000' * test (MIN) and (MAX) constants RT1 CCE,=DB'(MIN)',=X'0010000000000000' - RT1 CCE,=DD'(MIN)',=X'0000000000000001' - RT1 CCE,=DH'(MIN)',=X'0110000000000000' + RT1 CCE,=DD'(MIN)',=X'0400000000000000' #504 + RT1 CCE,=DH'(MIN)',=X'0010000000000000' #504 RT1 CCE,=EB'(MIN)',=X'00800000' - RT1 CCE,=ED'(MIN)',=X'00000001' - RT1 CCE,=EH'(MIN)',=X'01100000' + RT1 CCE,=ED'(MIN)',=X'04000000' #504 + RT1 CCE,=EH'(MIN)',=X'00100000' RT1 CCE,=LB'(MIN)',=X'00010000000000000000000000000000' - RT1 CCE,=LD'(MIN)',=X'00000000000000000000000000000001' - RT1 CCE,=LH'(MIN)',=X'01100000000000007200000000000000' + RT1 CCE,=LD'(MIN)',=X'04000000000000000000000000000000' #504 + RT1 CCE,=LH'(MIN)',=X'00100000000000007200000000000000' #504 RT1 CCE,=DB'(MAX)',=X'7FEFFFFFFFFFFFFF' - RT1 CCE,=DD'(MAX)',=X'77FCFF3FCFF3FCFF' + RT1 CCE,=DD'(MAX)',=X'77FCFF3FCFF3FCFF' RT1 CCE,=DH'(MAX)',=X'7FFFFFFFFFFFFFFF' RT1 CCE,=EB'(MAX)',=X'7F7FFFFF' RT1 CCE,=ED'(MAX)',=X'77F3FCFF' diff --git a/rt/mlc/TESTDC1.MLC b/rt/mlc/TESTDC1.MLC index 6137d652d..febb649c7 100644 --- a/rt/mlc/TESTDC1.MLC +++ b/rt/mlc/TESTDC1.MLC @@ -50,6 +50,7 @@ * 01/25/11 RPI 1139 C2X ARG IN QUOTES FOR NOALLOW * 2022-05-03 update copyright, add to z390\tests, fix SETC '&&' to '&' * 2022-05-07 replace TESTSUB1 with CVTTOHEX to remove dependency +* 2023-07-30 #504 bring floating point special values in line with HLASM/PoP ********************************************************************* PRINT DATA TESTDC1 RT1 MAIN @@ -107,14 +108,14 @@ LEN EQU X'5678' RT1 CCE,=LS2'1',=X'43100000000000003500000000000000' * test (MIN) and (MAX) constants RT1 CCE,=DB'(MIN)',=X'0010000000000000' - RT1 CCE,=DD'(MIN)',=X'0000000000000001' - RT1 CCE,=DH'(MIN)',=X'0110000000000000' + RT1 CCE,=DD'(MIN)',=X'0400000000000000' #504 + RT1 CCE,=DH'(MIN)',=X'0010000000000000' #504 RT1 CCE,=EB'(MIN)',=X'00800000' - RT1 CCE,=ED'(MIN)',=X'00000001' - RT1 CCE,=EH'(MIN)',=X'01100000' + RT1 CCE,=ED'(MIN)',=X'04000000' #504 + RT1 CCE,=EH'(MIN)',=X'00100000' RT1 CCE,=LB'(MIN)',=X'00010000000000000000000000000000' - RT1 CCE,=LD'(MIN)',=X'00000000000000000000000000000001' - RT1 CCE,=LH'(MIN)',=X'01100000000000007200000000000000' + RT1 CCE,=LD'(MIN)',=X'04000000000000000000000000000000' #504 + RT1 CCE,=LH'(MIN)',=X'00100000000000007200000000000000' #504 RT1 CCE,=DB'(MAX)',=X'7FEFFFFFFFFFFFFF' RT1 CCE,=DD'(MAX)',=X'77FCFF3FCFF3FCFF' RT1 CCE,=DH'(MAX)',=X'7FFFFFFFFFFFFFFF' diff --git a/rt/test/TESTDFP1.MLC b/rt/test/TESTDFP1.MLC deleted file mode 100644 index 39915b2a6..000000000 --- a/rt/test/TESTDFP1.MLC +++ /dev/null @@ -1,1517 +0,0 @@ -********************************************************************* -* z390 - Mainframe assembler emulator and run-time engine -* Copyright (C) 2021 z390 Assembler LLC -* -* This file is part of z390. -* -* z390 is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License as published by -* the Free Software Foundation; either version 2 of the License, or -* (at your option) any later version. -* z390 is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -* -* You should have received a copy of the GNU General Public License -* along with this program; if not, see https://www.gnu.org/licenses. -********************************************************************* -* Author - Don Higgins * -* Date - 12/09/06 * -********************************************************************* -* TEST DFP DECIMAL FLOATING POINT -********************************************************************* -* Maintenance: -* 12/09/06 RPI 407 ADD ADTR, SDTR, MDTR, DDTR, CDTR, CSDTR -* 12/15/06 RPI 518 ADD AXTR, SXTR, MXTR, DXTR -* 12/18/06 RPI 406 ADD REMAINING DFP INSTRUCTIONS -* KDTR, KXTR, CEDTR, CEXTR, CDGTR, CXGTR, CDSTR, CXSTR -* CDUTR, CXUTR, CGDTR, CGXTR, CUDTR, CUXTR, ESDTR, ESXTR -* IEDTR, IEXTR, FIDTR, FIXTR -* SRNMT, SFASR, LFAS -* LDETR, LXDTR, LEDTR, LDXTR, QADTR, QAXTR, RRDTR, RRXTR -* SLDT, SLXT SRDT, SRXT -* TDCDT, TDCET, TDCXT, TDGDT, TDGET, TDGXT -* 12/29/06 RPI 527 ADD MISSING DFP INS -* LPDFR, LNDFR, CPSDR, LCDFR, LDGR, LGDR -* 01/08/07 RPI 527 CORRECT CGDTR, CGXTR ROUNDING -* 01/10/07 RPI 533 CORRECT CGDTR, CGXTR ROUNDING -* 01/12/08 RPI 786 CHANGE BIAS BAASED ON NEW CANONIZATION -* 01/13/08 RPI 786 USE FP COMPARES TO HANDLE EQUIVALENT DFP VALUES -* 01/17/08 RPI 790 CORRECT TEST FOR EXPECTED BIAS BASED ON DFP CONST. -* 01/22/08 RPI 791 TEST CGDTR AND CGXTR SETTING CC3 IF TOO BIG -* 02/27/08 RPI 811 TEST THE FOLLOWING FIXES -* 1. CSDTR FIX FOR HIGH DIGIT 0 IF NEGATIVE -* 2. SRDT/SLDT/SRXT/SLXT INCORRECT FOR EXP > 0 -* 03/13/08 RPI 820 TEST IEEE DIV,OVF,UNF EXCEPTION HANDLING -* 06/20/08 RPI 845 CHANGE EPIED TO IHAEPIE -********************************************************************* - MACRO -&N CLCED &S1,&S2 -&N LE F0,&S1 - LDETR F0,F0,0 - LE F1,&S2 - LDETR F1,F1,0 - CDTR F0,R1 - MEND - MACRO -&N CLCDD &S1,&S2 -&N LD F0,&S1 - LD F1,&S2 - CDTR F0,F1 - MEND - MACRO -&N CLCLD &S1,&S2 -&N LX F0,&S1 - LX F1,&S2 - CXTR F0,F1 - MEND - PRINT DATA -TESTDFP1 RT1 MAIN -DD1 DC DD'0' -ED1 DC ED'0' -LD1 DC LD'0' -PL16 DC PL16'0' -WORK DC XL16'00' -ED_BIAS EQU 101 S,C5,BXCF6,CCF20 -DD_BIAS EQU 398 S,C5,BXCF8,CCF50 -LD_BIAS EQU 6176 S,C5,BXDF12,CCF110 -DDMIN DC DD'(MIN)' RPI 820 -DDMAX DC DD'(MAX)' RPI 820 -LDMIN DC LD'(MIN)' RPI 820 -LDMAX DC LD'(MAX)' RPI 820 -FPCREG DC F'0' FPC BFP/DFP CONTROL REG WORK AREA -FPCDXC EQU FPCREG+2 REASON CODES FOR 0C7 DATA EXCEPTIONS -TDCPZ EQU X'800' TEST DFP DATA CLASS PLUS ZERO -TDCMZ EQU X'400' TEST DFP DATA CLASS MINUS ZERO -TDCPSN EQU X'200' TEST DFP DATA CLASS PLUS SUBNORMAL MAX -TDCMSN EQU X'100' TEST DFP DATA CLASS MINUS SUBNORMAL -TDCPN EQU X'080' TEST DFP DATA CLASS PLUS NORMAL IN RANGE -TDCMN EQU X'040' TEST DFP DATA CLASS MINUS NORMAL -TDCPI EQU X'020' TEST DFP DATA CLASS PLUS INFINITY -TDCMI EQU X'010' TEST DFP DATA CLASS MINUS INFINITY -TDCPQ EQU X'008' TEST DFP DATA CLASS PLUS QUIET NAN -TDCMQ EQU X'004' TEST DFP DATA CLASS MINUS QUIET NAN -TDCPSG EQU X'002' TEST DFP DATA CLASS PLUS SIGNAL NAN -TDCMSG EQU X'001' TEST DFP DATA CLASS MINUS SIGNAL NAN -TDGPSZ EQU X'800' TEST DFP DATA GROUP PLUS SAFE ZERO -TDGMSZ EQU X'400' TEST DFP DATA GROUP MINUS SAVE ZERO -TDGPEZ EQU X'200' TEST DFP DATA GROUP PLUS EXTREME EXP ZERO -TDGMEZ EQU X'100' TEST DFP DATA GROUP MINUS EXTREME EXP ZERO -TDGPEF EQU X'080' TEST DFP DATA GROUP PLUS EXTRENE FINITE -TDGMEF EQU X'040' TEST DFP DATA GROUP MINUS EXTREME FINITE -TDGPSF EQU X'020' TEST DFP DATA GROUP PLUS SAFE FINITE -TDGMSF EQU X'010' TEST DFP DATA GROUP MINUS SAFE FINITE -TDGPDF EQU X'008' TEST DFP DATA GROUP PLUS FIRST DIGIT NON EXT EXP -TDGMDF EQU X'004' TEST DFP DATA GROUP MINUS FIRST DIGIT NON EXT EXP -TDGPIN EQU X'002' TEST DFP DATA GROUP PLUS INFINITY OR NAN -TDGMIN EQU X'001' TEST DFP DATA GROUP MINUS INFINITY OR NAM - EQUREGS REGS=GPR - EQUREGS REGS=FPR -ESPIE_EXIT DS 0H - USING *,R15 - USING EPIE,R1 - L R0,EPIEPARM - ST R0,EPIEPSW+4 - BR R14 - DROP R15,R1 - RT1 START -* B2B9 SRNMT - SRNMT 1 SET DFP ROUND TO ZERO - LD 4,=DD'1.5' - FIDTR 1,0,4,0 - LD 5,=DD'1' - CDTR 1,5 - RT1 CC0 - SRNMT 0 RESET TO DFP ROUND HALF EVEN - LD 4,=DD'1.5' - FIDTR 1,0,4,0 - LD 5,=DD'2' - CDTR 1,5 - RT1 CC0 -* B2BD LFAS - STFPC FPCREG - OI FPCREG+3,X'10' - LFAS FPCREG SET DFP ROUND MODE 1 - RND TO ZERO - LD 4,=DD'1.5' - FIDTR 1,0,4,0 - LD 5,=DD'1' - CDTR 1,5 - RT1 CC0 - NI FPCREG+3,X'8F' RESET DFP RND TO 0 - NEAR HALF EVEN - LFAS FPCREG - LD 4,=DD'1.5' - FIDTR 1,0,4,0 - LD 5,=DD'2' - CDTR 1,5 - RT1 CC0 -* B370 LPDFR - LD 2,=DD'1' - LD 3,=DD'1' - LPDFR 1,2 - CDTR 1,3 - RT1 CC0 - LD 2,=DD'-1' - LD 3,=DD'1' - LPDFR 1,2 - CDTR 1,3 - RT1 CC0 -* B371 LNDFR - LD 2,=DD'1' - LD 3,=DD'-1' - LNDFR 1,2 - CDTR 1,3 - RT1 CC0 - LD 2,=DD'-1' - LD 3,=DD'-1' - LNDFR 1,2 - CDTR 1,3 - RT1 CC0 -* B372 CPSDR - LD 2,=DD'2' - LD 3,=DD'-3' - LD 4,=DD'3' - CPSDR 1,2,3 - CDTR 1,4 - RT1 CC0 - LD 2,=DD'-2' - LD 3,=DD'3' - LD 4,=DD'-3' - CPSDR 1,2,3 - CDTR 1,4 - RT1 CC0 -* B373 LCDFR - LD 2,=DD'1' - LD 3,=DD'-1' - LCDFR 1,2 - CDTR 1,3 - RT1 CC0 - LD 2,=DD'-1' - LD 3,=DD'1' - LCDFR 1,2 - CDTR 1,3 - RT1 CC0 -* B385 SFASR - STFPC FPCREG - OI FPCREG+3,X'10' - L 1,FPCREG - SFASR 1 SET DFP ROUND MODE 1 - RND TO ZERO - LD 4,=DD'1.5' - FIDTR 1,0,4,0 - LD 5,=DD'1' - CDTR 1,5 - RT1 CC0 - NI FPCREG+3,X'8F' RESET DFP RND TO 0 - NEAR HALF EVEN - L 1,FPCREG - SFASR 1 - LD 4,=DD'1.5' - FIDTR 1,0,4,0 - LD 5,=DD'2' - CDTR 1,5 - RT1 CC0 -* B3C1 LDGR - LG 2,=DD'1' - LD 3,=DD'1' - LDGR 1,2 - CDTR 1,3 - RT1 CC0 - LG 2,=DD'2' - LD 3,=DD'2' - LDGR 1,2 - CDTR 1,3 - RT1 CC0 -* B3CD LGDR - LD 2,=DD'1' - LG 3,=DD'1' - LGDR 1,2 - CGR 1,3 - RT1 CC0 - LD 2,=DD'2' - LG 3,=DD'2' - LGDR 1,2 - CGR 1,3 - RT1 CC0 -* B3D0 MDTR - LD 2,=DD'30' - LD 3,=DD'20' - MDTR 1,2,3 - STD 1,DD1 - CLCDD DD1,=DD'600' - RT1 CCE - LD 2,=DD'-30' - LD 3,=DD'-20' - MDTR 1,2,3 - STD 1,DD1 - CLCDD DD1,=DD'600' - RT1 CCE - ESPIE SET,ESPIE_EXIT,7,PARAM=MDTR1 DFP OVERFLOW FPCDXC=20 - LD R0,=DD'1' - LD R1,DDMAX - MDTR R0,R0,R1 - RT1 ABORT -MDTR1 ESPIE RESET - WTO 'ESPIE DFP MDTR OVERFLOW OK' -* B3D1 DDTR - LD 2,=DD'600' - LD 3,=DD'20' - DDTR 1,2,3 - STD 1,DD1 - CLCDD DD1,=DD'30' - RT1 CCE - LD 2,=DD'10' - LD 3,=DD'3' - DDTR 1,2,3 - STD 1,DD1 - CLCDD DD1,=DD'3.333333333333333' - RT1 CCE - ESPIE SET,ESPIE_EXIT,7,PARAM=DDTR1 DFP DIV FPCDXC=40 RPI 820 - LD R4,=DD'1' - LD R5,=DD'0' - DDTR R1,R4,R5 - RT1 ABORT -DDTR1 ESPIE RESET - STFPC FPCREG - CLI FPCDXC,X'40' - RT1 CCE - WTO 'ESPIE DFP DDTR DIVIDE OK' -* B3D2 ADTR - LD 2,=DD'1234567890123456' - LD 3,=DD'1111111111111111' - ADTR 1,2,3 - RT1 CC2 - STD 1,DD1 - CLCDD DD1,=DD'2345679001234567' - RT1 CCE - LD 2,=DD'1' - LD 3,=DD'2' - ADTR 1,2,3 - RT1 CC2 - STD 1,DD1 - CLCDD DD1,=DD'3' - RT1 CCE - LD 2,=DD'1.1' - LD 3,=DD'2.2' - ADTR 1,2,3 - RT1 CC2 - STD 1,DD1 - CLCDD DD1,=DD'3.3' - RT1 CCE - LD 2,=DD'1' - LD 3,=DD'-1' - ADTR 1,2,3 - RT1 CC0 - STD 1,DD1 - CLCDD DD1,=DD'0' - RT1 CCE - LD 2,=DD'1' - LD 3,=DD'-2' - ADTR 1,2,3 - RT1 CC1 - STD 1,DD1 - CLCDD DD1,=DD'-1' - RT1 CCE - ESPIE SET,ESPIE_EXIT,7,PARAM=ADTR1 DFP OVERFLOW FPCDXC=20 - LD R0,DDMAX - LD R1,DDMAX - ADTR R0,R0,R1 - RT1 ABORT -ADTR1 ESPIE RESET - STFPC FPCREG - CLI FPCDXC,X'20' - RT1 CCE - WTO 'ESPIE DFP ADTR OVERFLOW OK' -* B3D3 SDTR - LD 2,=DD'1234567890123456' - LD 3,=DD'1111111111111111' - SDTR 1,2,3 - RT1 CC2 - STD 1,DD1 - CLCDD DD1,=DD'123456779012345' - RT1 CCE - LD 2,=DD'1' - LD 3,=DD'1' - SDTR 1,2,3 - RT1 CC0 - STD 1,DD1 - CLCDD DD1,=DD'0' - RT1 CCE - LD 2,=DD'0' - LD 3,=DD'1' - SDTR 1,2,3 - RT1 CC1 - STD 1,DD1 - CLCDD DD1,=DD'-1' - RT1 CCE - ESPIE SET,ESPIE_EXIT,7,PARAM=SDTR1 DFP UNDERFLOW FPCDXC=10 - LD R4,DDMIN - LD R5,DDMIN - ADTR R4,R4,R5 - SDTR R4,R4,R5 - RT1 ABORT -SDTR1 ESPIE RESET - STFPC FPCREG - CLI FPCDXC,X'10' - RT1 CCE - WTO 'ESPIE DFP SDTR UNDERFLOW OK' -* B3D4 LDETR - LE 4,=ED'123' - LDETR 1,4,0 - LD 5,=DD'123' - CDTR 1,5 - RT1 CC0 -* B3D5 LEDTR - LD 4,=DD'1234568.5' - LEDTR 1,0,4,0 DEFAULT NEAREST HALF EVEN - STE 1,ED1 - CLCED ED1,=ED'1234568' - RT1 CC0 - LD 4,=DD'1234565.5' - LEDTR 1,0,4,0 DEFAULT NEAREST HALF EVEN - STE 1,ED1 - CLCED ED1,=ED'1234566' - RT1 CC0 - LD 4,=DD'1234568.5' - LEDTR 1,8+1,4,0 ROUND TOWARD ZERO - STE 1,ED1 - CLCED ED1,=ED'1234568' - RT1 CC0 - LD 4,=DD'1234567.5' - LEDTR 1,8+1,4,0 ROUND TOWARD ZERO - STE 1,ED1 - CLCED ED1,=ED'1234567' - RT1 CC0 -* B3D6 LTDTR - LD 4,=DD'1' - LTDTR 1,4 - RT1 CCH - CDTR 1,4 - RT1 CC0 - LD 4,=DD'0' - LTDTR 1,4 - RT1 CC0 - CDTR 1,4 - RT1 CC0 - LD 4,=DD'-1' - LTDTR 1,4 - RT1 CC1 - CDTR 1,4 - RT1 CC0 -* B3D7 FIDTR - LD 4,=DD'123' - FIDTR 1,0,4,0 - LD 5,=DD'123' - CDTR 1,5 - RT1 CC0 - LD 4,=DD'1.5' - FIDTR 1,0,4,0 - LD 5,=DD'2' - CDTR 1,5 - RT1 CC0 -* B3D8 MXTR - LX 4,=LD'30' - LX 5,=LD'20' - MXTR 1,4,5 - STX 1,LD1 - CLCLD LD1,=LD'600' - RT1 CCE - LX 4,=LD'-30' - LX 5,=LD'-20' - MXTR 1,4,5 - STX 1,LD1 - CLCLD LD1,=LD'600' - RT1 CCE - ESPIE SET,ESPIE_EXIT,7,PARAM=MXTR1 DFP OVERFLOW FPCDXC=20 - LX R0,=LD'1' - LX R1,LDMAX - MXTR R0,R0,R1 - RT1 ABORT -MXTR1 ESPIE RESET - WTO 'ESPIE DFP MXTR OVERFLOW OK' -* B3D9 DXTR - LX 4,=LD'600' - LX 5,=LD'20' - DXTR 1,4,5 - STX 1,LD1 - CLCLD LD1,=LD'30' - RT1 CCE - LX 4,=LD'10' - LX 5,=LD'3' - DXTR 1,4,5 - STX 1,LD1 - CLCLD LD1,=LD'3.333333333333333333333333333333333' - RT1 CCE - ESPIE SET,ESPIE_EXIT,7,PARAM=DXTR1 DFP DIV FPCDXC=40 RPI 820 - LX R4,=LD'1' - LX R5,=LD'0' - DXTR R0,R4,R5 - RT1 ABORT -DXTR1 ESPIE RESET - STFPC FPCREG - CLI FPCDXC,X'40' - RT1 CCE - WTO 'ESPIE DFP DXTR DIVIDE OK' -* B3DA AXTR - LX 4,=LD'1234567890123456789012345678901234' - LX 5,=LD'1111111111111111111111111111111111' - AXTR 1,4,5 - RT1 CC2 - STX 1,LD1 - CLCLD LD1,=LD'2345679001234567900123456790012345' - RT1 CCE - LX 4,=LD'1' - LX 5,=LD'2' - AXTR 1,4,5 - RT1 CC2 - STX 1,LD1 - CLCLD LD1,=LD'3' - RT1 CCE - LX 4,=LD'1.1' - LX 5,=LD'2.2' - AXTR 1,4,5 - RT1 CC2 - STX 1,LD1 - CLCLD LD1,=LD'3.3' - RT1 CCE - LX 4,=LD'1' - LX 5,=LD'-1' - AXTR 1,4,5 - RT1 CC0 - STX 1,LD1 - CLCLD LD1,=LD'0' - RT1 CCE - LX 4,=LD'1' - LX 5,=LD'-2' - AXTR 1,4,5 - RT1 CC1 - STX 1,LD1 - CLCLD LD1,=LD'-1' - RT1 CCE - ESPIE SET,ESPIE_EXIT,7,PARAM=AXTR1 DFP OVERFLOW FPCDXC=20 - LX R0,LDMAX - LX R1,LDMAX - AXTR R0,R0,R1 - RT1 ABORT -AXTR1 ESPIE RESET - STFPC FPCREG - CLI FPCDXC,X'20' - RT1 CCE - WTO 'ESPIE DFP AXTR OVERFLOW OK' -* B3DB SXTR - LX 4,=LD'1234567890123456789012345678901234' - LX 5,=LD'1111111111111111111111111111111111' - SXTR 1,4,5 - RT1 CC2 - STX 1,LD1 - CLCLD LD1,=LD'123456779012345677901234567790123' - RT1 CCE - LX 4,=LD'1' - LX 5,=LD'1' - SXTR 1,4,5 - RT1 CC0 - STX 1,LD1 - CLCLD LD1,=LD'0' - RT1 CCE - LX 4,=LD'0' - LX 5,=LD'1' - SXTR 1,4,5 - RT1 CC1 - STX 1,LD1 - CLCLD LD1,=LD'-1' - RT1 CCE - ESPIE SET,ESPIE_EXIT,7,PARAM=SXTR1 DFP UNDERFLOW FPCDXC=10 - LX R4,LDMIN - LX R5,LDMIN - AXTR R4,R4,R5 - SXTR R4,R4,R5 - RT1 ABORT -SXTR1 ESPIE RESET - STFPC FPCREG - CLI FPCDXC,X'10' - RT1 CCE - WTO 'ESPIE DFP SXTR UNDERFLOW OK' -* B3DC LXDTR - LD 4,=DD'123' - LXDTR 1,4,0 - LX 5,=LD'123' - CXTR 1,5 - RT1 CC0 -* B3DD LDXTR - LX 4,=LD'1234567890123456.5' - LDXTR 1,0,4,0 DEFAULT NEAREST HALF EVEN - LD 5,=DD'1234567890123456' - CDTR 1,5 - RT1 CC0 - LX 4,=LD'1234567890123457.5' - LDXTR 1,0,4,0 DEFAULT NEAREST HALF EVEN - LD 5,=DD'1234567890123458' - CDTR 1,5 - RT1 CC0 - LX 4,=LD'1234567890123456.5' - LDXTR 1,8+1,4,0 ROUND TOWARD ZERO - LD 5,=DD'1234567890123456' - CDTR 1,5 - RT1 CC0 - LX 4,=LD'1234567890123457.5' - LDXTR 1,8+1,4,0 ROUND TOWARD ZERO - LD 5,=DD'1234567890123457' - CDTR 1,5 - RT1 CC0 -* B3DF FIXTR - LX 4,=LD'123' - FIXTR 1,0,4,0 - LX 5,=LD'123' - CXTR 1,5 - RT1 CC0 - LX 4,=LD'1.5' - FIXTR 1,0,4,0 - LX 5,=LD'2' - CXTR 1,5 - RT1 CC0 - LX 4,=LD'1.5' - FIXTR 1,0,4,0 - LX 5,=LD'2' - CXTR 1,5 - RT1 CC0 -* B3E0 KDTR - LD 1,=DD'1' - LD 2,=DD'2' - KDTR 1,2 - RT1 CC1 - LD 1,=DD'1' - LD 2,=DD'1' - KDTR 1,2 - RT1 CC0 - LD 1,=DD'2' - LD 2,=DD'1' - KDTR 1,2 - RT1 CC2 -* B3DE LTXTR - LX 4,=LD'1' - LTXTR 1,4 - RT1 CCH - CXTR 1,4 - RT1 CC0 - LX 4,=LD'0' - LTXTR 1,4 - RT1 CC0 - CXTR 1,4 - RT1 CC0 - LX 4,=LD'-1' - LTXTR 1,4 - RT1 CC1 - CXTR 1,4 - RT1 CC0 -* B3E1 CGDTR - LD 4,=DD'1234567890123456' - CGDTR 1,0,4 - RT1 CCH - CLG 1,=FD'1234567890123456' - RT1 CC0 - LD 4,=DD'-1234567890123456' - CGDTR 1,0,4 - RT1 CCL - CLG 1,=FD'-1234567890123456' - RT1 CC0 - LD 4,=DD'0' - CGDTR 1,0,4 - RT1 CC0 - CLG 1,=FD'0' - RT1 CC0 - LD 4,=DD'1.5' - CGDTR 1,0,4 - RT1 CCH - CLG 1,=FD'2' - RT1 CC0 - LD 1,=DD'(MAX)' RPI 791 - CGDTR 0,0,1 - RT1 CC3 -* MORE THAN HALF - LD 4,=DD'999.99' - CGDTR 1,8+0,4 RPI 533 NEAREST, HALF EVEN DEFAULT - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.99' - CGDTR 1,8+1,4 RPI 533 NEAREST, HALF TOWARD ZERO - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.99' - CGDTR 1,8+2,4 RPI 533 TOWARD +INFINITY - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.99' - CGDTR 1,8+3,4 RPI 533 TOWARD -INFINITY - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.99' - CGDTR 1,8+4,4 RPI 533 NEAREST, HALF AWAY FROM 0 - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.99' - CGDTR 1,8+5,4 RPI 533 NEAREST, HALF TOWARD 0 - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.99' - CGDTR 1,8+6,4 RPI 533 AWAY FROM ZERO - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 -* LESS THAN HALF - LD 4,=DD'999.11' - CGDTR 1,8+0,4 RPI 533 NEAREST, HALF EVEN DEFAULT - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.11' - CGDTR 1,8+1,4 RPI 533 NEAREST, HALF TOWARD ZERO - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.11' - CGDTR 1,8+2,4 RPI 533 TOWARD +INFINITY - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.11' - CGDTR 1,8+3,4 RPI 533 TOWARD -INFINITY - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.11' - CGDTR 1,8+4,4 RPI 533 NEAREST, HALF AWAY FROM 0 - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.11' - CGDTR 1,8+5,4 RPI 533 NEAREST, HALF TOWARD 0 - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.11' - CGDTR 1,8+6,4 RPI 533 AWAY FROM ZERO - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 -* ODD HALF - LD 4,=DD'999.5' - CGDTR 1,8+0,4 RPI 533 NEAREST, HALF EVEN DEFAULT - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.5' - CGDTR 1,8+1,4 RPI 533 NEAREST, HALF TOWARD ZERO - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.5' - CGDTR 1,8+2,4 RPI 533 TOWARD +INFINITY - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.5' - CGDTR 1,8+3,4 RPI 533 TOWARD -INFINITY - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.5' - CGDTR 1,8+4,4 RPI 533 NEAREST, HALF AWAY FROM 0 - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LD 4,=DD'999.5' - CGDTR 1,8+5,4 RPI 533 NEAREST, HALF TOWARD 0 - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'999.5' - CGDTR 1,8+6,4 RPI 533 AWAY FROM ZERO - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 -* EVEN HALF - LD 4,=DD'998.5' - CGDTR 1,8+0,4 RPI 533 NEAREST, HALF EVEN DEFAULT - RT1 CCH - CLG 1,=FD'998' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+1,4 RPI 533 NEAREST, HALF TOWARD ZERO - RT1 CCH - CLG 1,=FD'998' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+2,4 RPI 533 TOWARD +INFINITY - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+3,4 RPI 533 TOWARD -INFINITY - RT1 CCH - CLG 1,=FD'998' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+4,4 RPI 533 NEAREST, HALF AWAY FROM 0 - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+5,4 RPI 533 NEAREST, HALF TOWARD 0 - RT1 CCH - CLG 1,=FD'998' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+6,4 RPI 533 AWAY FROM ZERO - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 -* B3E2 CUDTR - LD 1,=DD'1' - CUDTR 0,1 - CG 0,=XL8'1' RPI 790 - RT1 CCE - LD 1,=DD'-1' - CUDTR 0,1 - CG 0,=XL8'1' RPI 790 - RT1 CCE - LD 1,=DD'1234567890123456' RPI 786 - CUDTR 0,1 - CG 0,=XL8'1234567890123456' RPI 786 - RT1 CCE -* B3E3 CSDTR - LD 1,=DD'1' - CSDTR 0,1,0 - CG 0,=PL8'1' RPI 790 - RT1 CCE - CSDTR 0,1,1 - CG 0,=XL8'000000000000001F' RPI 790 - RT1 CCE - LD 1,=DD'-1' - CSDTR 0,1,0 - CG 0,=PL8'-1' RPI 790 - RT1 CCE - CSDTR 0,1,1 - CG 0,=XL8'000000000000001D' RPI 790 - RT1 CCE - LD 1,=DD'123456789012345' - CSDTR 0,1,0 - CG 0,=PL8'123456789012345' - RT1 CCE - LD 1,=DD'-123456789012345' - CSDTR 0,1,0 - CG 0,=PL8'-123456789012345' - RT1 CCE -* B3E4 CDTR - LD 1,=DD'1' - LD 2,=DD'2' - CDTR 1,2 - RT1 CC1 - LD 1,=DD'1' - LD 2,=DD'1' - CDTR 1,2 - RT1 CC0 - LD 1,=DD'2' - LD 2,=DD'1' - CDTR 1,2 - RT1 CC2 -* B3E5 EEDTR - LD 2,=DD'1' - EEDTR 1,2 - CG 1,=FD'398' RPI 790 - RT1 CC0 - LD 2,=DD'1E1' - EEDTR 1,2 - CG 1,=FD'399' RPI 790 - RT1 CC0 - LD 2,=DD'.1' - EEDTR 1,2 - CG 1,=FD'397' RPI 790 - RT1 CC0 -* B3E7 ESDTR - LD 4,=DD'0' - ESDTR 1,4 - CG 1,=FD'0' RPI 786 - RT1 CC0 - LD 4,=DD'1' - ESDTR 1,4 - CG 1,=FD'1' - RT1 CC0 - LD 4,=DD'-1' - ESDTR 1,4 - CG 1,=FD'1' - RT1 CC0 - LD 4,=DD'12' - ESDTR 1,4 - CG 1,=FD'2' - RT1 CC0 - LD 4,=DD'1234567890123456' - ESDTR 1,4 - CG 1,=FD'16' - RT1 CC0 - LD 0,=DD'1000000' - LD 0,=XL8'2238000000100000' - ESDTR 1,0 - CG 1,=FD'7' - RT1 CC0 -* B3E8 KXTR - LX 4,=LD'1' - LX 5,=LD'2' - KXTR 4,5 - RT1 CC1 - LX 4,=DD'1' - LX 5,=DD'1' - KXTR 4,5 - RT1 CC0 - LX 4,=DD'2' - LX 5,=DD'1' - KXTR 4,5 - RT1 CC2 -* B3E9 CGXTR - LX 4,=LD'123456789012345678' - CGXTR 1,0,4 - RT1 CCH - CLG 1,=FD'123456789012345678' - RT1 CC0 - LX 4,=LD'-123456789012345678' - CGXTR 1,0,4 - RT1 CCL - CLG 1,=FD'-123456789012345678' - RT1 CC0 - LX 4,=LD'0' - CGXTR 1,0,4 - RT1 CC0 - CLG 1,=FD'0' - RT1 CC0 - LX 4,=LD'1.5' - CGXTR 1,0,4 - RT1 CCH - CLG 1,=FD'2' - RT1 CC0 - LX 1,=LD'(MAX)' RPI 791 - CGDTR 0,0,1 - RT1 CC3 -* MORE THAN HALF - LX 4,=LD'999.99' - CGXTR 1,8+0,4 RPI 533 NEAREST, HALF EVEN DEFAULT - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.99' - CGXTR 1,8+1,4 RPI 533 NEAREST, HALF TOWARD ZERO - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.99' - CGXTR 1,8+2,4 RPI 533 TOWARD +INFINITY - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.99' - CGXTR 1,8+3,4 RPI 533 TOWARD -INFINITY - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.99' - CGXTR 1,8+4,4 RPI 533 NEAREST, HALF AWAY FROM 0 - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.99' - CGXTR 1,8+5,4 RPI 533 NEAREST, HALF TOWARD 0 - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.99' - CGXTR 1,8+6,4 RPI 533 AWAY FROM ZERO - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 -* LESS THAN HALF - LX 4,=LD'999.11' - CGXTR 1,8+0,4 RPI 533 NEAREST, HALF EVEN DEFAULT - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.11' - CGXTR 1,8+1,4 RPI 533 NEAREST, HALF TOWARD ZERO - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.11' - CGXTR 1,8+2,4 RPI 533 TOWARD +INFINITY - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.11' - CGXTR 1,8+3,4 RPI 533 TOWARD -INFINITY - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.11' - CGXTR 1,8+4,4 RPI 533 NEAREST, HALF AWAY FROM 0 - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.11' - CGXTR 1,8+5,4 RPI 533 NEAREST, HALF TOWARD 0 - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.11' - CGXTR 1,8+6,4 RPI 533 AWAY FROM ZERO - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 -* ODD HALF - LX 4,=LD'999.5' - CGXTR 1,8+0,4 RPI 533 NEAREST, HALF EVEN DEFAULT - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.5' - CGXTR 1,8+1,4 RPI 533 NEAREST, HALF TOWARD ZERO - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.5' - CGXTR 1,8+2,4 RPI 533 TOWARD +INFINITY - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.5' - CGXTR 1,8+3,4 RPI 533 TOWARD -INFINITY - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.5' - CGXTR 1,8+4,4 RPI 533 NEAREST, HALF AWAY FROM 0 - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 - LX 4,=LD'999.5' - CGXTR 1,8+5,4 RPI 533 NEAREST, HALF TOWARD 0 - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LX 4,=LD'999.5' - CGXTR 1,8+6,4 RPI 533 AWAY FROM ZERO - RT1 CCH - CLG 1,=FD'1000' - RT1 CC0 -* EVEN HALF - LD 4,=DD'998.5' - CGDTR 1,8+0,4 RPI 533 NEAREST, HALF EVEN DEFAULT - RT1 CCH - CLG 1,=FD'998' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+1,4 RPI 533 NEAREST, HALF TOWARD ZERO - RT1 CCH - CLG 1,=FD'998' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+2,4 RPI 533 TOWARD +INFINITY - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+3,4 RPI 533 TOWARD -INFINITY - RT1 CCH - CLG 1,=FD'998' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+4,4 RPI 533 NEAREST, HALF AWAY FROM 0 - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+5,4 RPI 533 NEAREST, HALF TOWARD 0 - RT1 CCH - CLG 1,=FD'998' - RT1 CC0 - LD 4,=DD'998.5' - CGDTR 1,8+6,4 RPI 533 AWAY FROM ZERO - RT1 CCH - CLG 1,=FD'999' - RT1 CC0 -* B3EA CUXTR - LX 1,=LD'1' - CUXTR 0,1 - CG 0,=XL8'0' - RT1 CCE - CG 1,=XL8'1' RPI 790 - RT1 CCE - LX 1,=LD'-1' - CUXTR 0,1 - CG 0,=XL8'0' - RT1 CCE - CG 1,=XL8'1' RPI 790 - RT1 CCE - LX 1,=LD'1234567890123456789012345678901234' RPI 788 - CUXTR 0,1 - STMG 0,1,WORK - CLC WORK,=XL16'34567890123456789012345678901234' RPI 788 - RT1 CCE -* B3EB CSXTR - LX 1,=LD'1' - CSXTR 0,1,0 - CG 0,=FL8'0' - RT1 CCE - CG 1,=PL8'1' RPI 790 - RT1 CCE - CSXTR 0,1,1 - CG 0,=FL8'0' - RT1 CCE - CG 1,=XL8'000000000000001F' RPI 790 - RT1 CCE - LX 1,=LD'-1' - CSXTR 0,1,0 - CG 0,=FL8'0' - RT1 CCE - CG 1,=PL8'-1' RPI 790 - RT1 CCE - CSXTR 0,1,1 - CG 0,=FL8'0' - RT1 CCE - CG 1,=XL8'000000000000001D' RPI 790 - RT1 CCE - LX 1,=LD'1234567890123456789012345678901234' RPI 788 - CSXTR 0,1,0 - STMG 0,1,PL16 - CP PL16,=PL16'4567890123456789012345678901234' RPI 788 - RT1 CCE -* B3ED EEXTR - LX 4,=LD'1' - EEXTR 1,4 - CG 1,=FD'6176' RPI 790 - RT1 CC0 - LX 4,=LD'1E1' - EEXTR 1,4 - CG 1,=FD'6177' RPI 790 - RT1 CC0 - LX 4,=LD'.1' - EEXTR 1,4 - CG 1,=FD'6175' RPI 790 - RT1 CC0 -* B3EC CXTR - LX 4,=LD'1' - LX 5,=LD'2' - CXTR 4,5 - RT1 CC1 - LX 4,=DD'1' - LX 5,=DD'1' - CXTR 4,5 - RT1 CC0 - LX 4,=LD'2' - LX 5,=LD'1' - CXTR 4,5 - RT1 CC2 -* B3EF ESXTR - LX 4,=LD'0' - ESXTR 1,4 - CG 1,=FD'0' RPI 787 - RT1 CC0 - LX 4,=LD'1' - ESXTR 1,4 - CG 1,=FD'1' - RT1 CC0 - LX 4,=LD'-1' - ESXTR 1,4 - CG 1,=FD'1' - RT1 CC0 - LX 4,=LD'12' - ESXTR 1,4 - CG 1,=FD'2' - RT1 CC0 - LX 4,=LD'1234567890123456789012345678901234' - ESXTR 1,4 - CG 1,=FD'34' - RT1 CC0 -* B3F1 CDGTR - LG 2,=FD'1234567890123456' - CDGTR 1,2 CVT G TO DD - LD 4,=DD'1234567890123456' - CDTR 1,4 - RT1 CC0 -* B3F2 CDUTR - LG 2,=XL8'1234567890123456' - CDUTR 1,2 - LD 4,=DD'1234567890123456' - CDTR 1,4 - RT1 CC0 -* B3F3 CDSTR - LG 2,=PL8'123456789012345' - CDSTR 1,2 - LD 4,=DD'123456789012345' - CDTR 1,4 - RT1 CC0 -* B3F4 CEDTR - LD 1,=DD'.123' - LD 2,=DD'.123E1' - CEDTR 1,2 - RT1 CC1 - LD 1,=DD'.123' - LD 2,=DD'.123' - CEDTR 1,2 - RT1 CC0 - LD 1,=DD'.123E1' - LD 2,=DD'.123' - CEDTR 1,2 - RT1 CC2 -* B3F5 QADTR - LD 4,=DD'1235E-3' - LD 5,=DD'124E-2' - QADTR 1,4,5,0 F1=R4 WITH EXP= -2 AND ROUND HALF EVEN - CDTR 1,5 - RT1 CCE - LD 4,=DD'1235E-3' - LD 5,=DD'123E-2' - QADTR 1,4,5,8+1 F1=R4 WITH EXP= -2 AND ROUND TOWARD ZERO - CDTR 1,5 - RT1 CCE -* B3F6 IEDTR - LD 4,=DD'1' - LG 2,=AD(DD_BIAS) RPI790 - IEDTR 1,4,2 - LD 5,=DD'1' RPI790 - CDTR 1,5 - RT1 CC0 - LD 4,=DD'100' - LG 2,=AD(DD_BIAS) RPI 790 - IEDTR 1,4,2 - LD 5,=DD'100' RPI 790 - CDTR 1,5 - RT1 CC0 -* B3F7 LLDTR - LD 4,=DD'1235' - LG 2,=FD'3' - RRDTR 1,4,2,0 ROUND HALF EVEN F4 TO 3 SIG DIGITS - LD 5,=DD'1240' - CDTR 1,5 - RT1 CCE - LD 4,=DD'1235' - LG 2,=FD'3' - RRDTR 1,4,2,8+1 ROUND TOWARD 0 F4 TO 3 SIG DIGITS - LD 5,=DD'1230' - CDTR 1,5 - RT1 CCE -* B3F9 CXGTR - LG 2,=FD'1234567890123456' - CXGTR 1,2 CVT G TO LD - LX 4,=LD'1234567890123456' - CXTR 1,4 - RT1 CC0 -* B3FA CXUTR - LMG 2,3,=XL16'12345678901234567890123456789012' - CXUTR 1,2 - LX 4,=LD'12345678901234567890123456789012' - CXTR 1,4 - RT1 CC0 -* B3FB CXSTR - LMG 2,3,=PL16'1234567890123456789012345678901' - CXSTR 1,2 - LX 4,=LD'1234567890123456789012345678901' - CXTR 1,4 - RT1 CC0 -* B3FC CEXTR - LX 4,=LD'.123' RPI 786 FORCE -3 EXP - LX 5,=LD'.123E1' RPI 786 ROCE -2 EXP - CEXTR 4,5 - RT1 CC1 - LX 4,=DD'.123' RPI 786 - LX 5,=DD'.123' RPI 786 - CEXTR 4,5 - RT1 CC0 - LX 4,=DD'.123E1' RPI 786 - LX 5,=DD'.123' RPI 786 - CEXTR 4,5 - RT1 CC2 -* B3FD QAXTR - LX 4,=LD'1235E-3' - LX 5,=LD'124E-2' - QAXTR 1,4,5,0 F1=R4 WITH EXP= -2 ROUNDED HALF EVEN - CXTR 1,5 - RT1 CCE - LX 4,=LD'1235E-3' - LX 5,=LD'123E-2' - QAXTR 1,4,5,8+1 F1=R4 WITH EXP -2 AND ROUNDED TOWARD ZERO - CXTR 1,5 - RT1 CCE -* B3FE IEXTR - LX 4,=LD'1' - LG 2,=AD(LD_BIAS) RPI 790 - IEXTR 1,4,2 - LX 5,=LD'1' RPI 790 - CXTR 1,5 - RT1 CC0 - LX 4,=LD'100' - LG 2,=AD(LD_BIAS) RPI 790 - IEXTR 1,4,2 - LX 5,=LD'100' RPI 790 - CXTR 1,5 - RT1 CC0 -* B3FF RRXTR - LX 4,=LD'1235' - LG 2,=FD'3' - RRXTR 1,4,2,0 ROUND HALF EVEN F4 TO 3 SIG DIGITS - LX 5,=LD'1240' - CXTR 1,5 - RT1 CCE - LX 4,=LD'1235' - LG 2,=FD'3' - RRXTR 1,4,2,8+1 ROUND TOWARD 0 F4 TO 3 SIG DIGITS - LX 5,=LD'1230' - CXTR 1,5 - RT1 CCE -* ED40 SLDT - LD 4,=DD'123' - SLDT 1,4,3 - LD 5,=DD'123000' - CDTR 1,5 - RT1 CCE - LD 4,=DD'123E3' - SLDT 1,4,3 - LD 5,=DD'123000E3' - CDTR 1,5 - RT1 CCE - LD 4,=DD'1234567890123456' - SLDT 1,4,1 - LD 5,=DD'2345678901234560' - CDTR 1,5 - RT1 CCE - LD 4,=DD'1234567890123456E1' - SLDT 1,4,1 - LD 5,=DD'2345678901234560E1' - CDTR 1,5 - RT1 CCE - LD 4,=DD'1234567890123456E-1' - SLDT 1,4,1 - LD 5,=DD'2345678901234560E-1' - CDTR 1,5 - RT1 CCE -* ED41 SRDT - LD 4,=DD'1234' - SRDT 1,4,2 - LD 5,=DD'12' RPI 790 - CDTR 1,5 - RT1 CCE - LD 4,=DD'1234E5' - SRDT 1,4,2 - LD 5,=DD'12E5' RPI 790 - CDTR 1,5 - RT1 CCE -* ED48 SLXT - LX 4,=LD'123' - SLXT 1,4,3 - LX 5,=LD'123000' - CXTR 1,5 - RT1 CCE - LX 4,=LD'123E3' - SLXT 1,4,3 - LX 5,=LD'123E6' - CXTR 1,5 - RT1 CCE - LX 4,=LD'1234567890123456789012345678901234' - SLXT 1,4,1 - LX 5,=LD'2345678901234567890123456789012340' - CXTR 1,5 - RT1 CCE - LX 4,=LD'1234567890123456789012345678901234E1' - SLXT 1,4,1 - LX 5,=LD'2345678901234567890123456789012340E1' - CXTR 1,5 - RT1 CCE - LX 4,=LD'1234567890123456789012345678901234E-1' - SLXT 1,4,1 - LX 5,=LD'2345678901234567890123456789012340E-1' - CXTR 1,5 - RT1 CCE -* ED49 SRXT - LX 4,=LD'1234' - SRXT 1,4,2 - LX 5,=LD'12' RPI 790 - CXTR 1,5 - RT1 CCE - LX 4,=LD'1234E3' - SRXT 1,4,2 - LX 5,=LD'12E3' RPI 790 - CXTR 1,5 - RT1 CCE -* ED50 TDCET - LE 1,=ED'1' - TDCET 1,TDCPZ - RT1 CC0 - LE 1,=ED'0' - TDCET 1,TDCPZ - RT1 CC1 - LE 1,=ED'-0' - TDCET 1,TDCMZ - RT1 CC1 - LE 1,=ED'(MAX)' - TDCET 1,TDCPN - RT1 CC1 - LE 1,=ED'-(MAX)' - TDCET 1,TDCMN - RT1 CC1 - LE 1,=ED'1' - TDCET 1,TDCPN - RT1 CC1 - LE 1,=ED'-1' - TDCET 1,TDCMN - RT1 CC1 -* ED51 TDGET - LE 1,=LD'1' - TDGET 1,TDGPSZ - RT1 CC0 - LE 1,=ED'0' - TDGET 1,TDGPSZ - RT1 CC1 - LE 1,=ED'-0' - TDGET 1,TDGMSZ - RT1 CC1 - LE 1,=ED'1' - TDGET 1,TDGPSF - RT1 CC1 - LE 1,=ED'123456' - TDGET 1,TDGPSF - RT1 CC1 - LE 1,=ED'1234567' - TDGET 1,TDGPDF - RT1 CC1 - LE 1,=ED'(MAX)' - TDGET 1,TDGPDF - RT1 CC1 - LE 1,=ED'-1' - TDGET 1,TDGMSF - RT1 CC1 - LE 1,=ED'-123456' - TDGET 1,TDGMSF - RT1 CC1 - LE 1,=ED'-1234567' - TDGET 1,TDGMDF - RT1 CC1 - LE 1,=ED'-(MAX)' - TDGET 1,TDGMDF - RT1 CC1 -* ED54 TDCDT - LD 1,=DD'1' - TDCDT 1,TDCPZ - RT1 CC0 - LD 1,=DD'0' - TDCDT 1,TDCPZ - RT1 CC1 - LD 1,=DD'-0' - TDCDT 1,TDCMZ - RT1 CC1 - LD 1,=DD'(MAX)' - TDCDT 1,TDCPN - RT1 CC1 - LD 1,=DD'-(MAX)' - TDCDT 1,TDCMN - RT1 CC1 - LD 1,=DD'1' - TDCDT 1,TDCPN - RT1 CC1 - LD 1,=DD'-1' - TDCDT 1,TDCMN - RT1 CC1 -* ED55 TDGDT - LD 1,=DD'1' - TDGDT 1,TDGPSZ - RT1 CC0 - LD 1,=DD'0' - TDGDT 1,TDGPSZ - RT1 CC1 - LD 1,=DD'-0' - TDGDT 1,TDGMSZ - RT1 CC1 - LD 1,=DD'1' - TDGDT 1,TDGPSF - RT1 CC1 - LD 1,=DD'123456789012345' - TDGDT 1,TDGPSF - RT1 CC1 - LD 1,=DD'1234567890123456' - TDGDT 1,TDGPDF - RT1 CC1 - LD 1,=DD'(MAX)' - TDGDT 1,TDGPDF - RT1 CC1 - LD 1,=DD'-1' - TDGDT 1,TDGMSF - RT1 CC1 - LD 1,=DD'-123456789012345' - TDGDT 1,TDGMSF - RT1 CC1 - LD 1,=DD'-1234567890123456' - TDGDT 1,TDGMDF - RT1 CC1 - LD 1,=DD'-(MAX)' - TDGDT 1,TDGMDF - RT1 CC1 -* ED58 TDCXT - LX 1,=LD'1' - TDCXT 1,TDCPZ - RT1 CC0 - LX 1,=LD'0' - TDCXT 1,TDCPZ - RT1 CC1 - LX 1,=LD'-0' - TDCXT 1,TDCMZ - RT1 CC1 - LX 1,=LD'(MAX)' - TDCXT 1,TDCPN - RT1 CC1 - LX 1,=LD'-(MAX)' - TDCXT 1,TDCMN - RT1 CC1 - LX 1,=LD'1' - TDCXT 1,TDCPN - RT1 CC1 - LX 1,=LD'-1' - TDCXT 1,TDCMN - RT1 CC1 -* ED59 TDGXT - LX 1,=LD'1' - TDGXT 1,TDGPSZ - RT1 CC0 - LX 1,=LD'0' - TDGXT 1,TDGPSZ - RT1 CC1 - LX 1,=LD'-0' - TDGXT 1,TDGMSZ - RT1 CC1 - LX 1,=LD'1' - TDGXT 1,TDGPSF - RT1 CC1 - LX 1,=LD'123456789012345678901234567890123' - TDGXT 1,TDGPSF - RT1 CC1 - LX 1,=LD'1234567890123456789012345678901234' - TDGXT 1,TDGPDF - RT1 CC1 - LX 1,=LD'(MAX)' - TDGXT 1,TDGPDF - RT1 CC1 - LX 1,=LD'-1' - TDGXT 1,TDGMSF - RT1 CC1 - LX 1,=LD'-123456789012345678901234567890123' - TDGXT 1,TDGMSF - RT1 CC1 - LX 1,=LD'-1234567890123456789012345678901234' - TDGXT 1,TDGMDF - RT1 CC1 - LX 1,=LD'-(MAX)' - TDGXT 1,TDGMDF - RT1 CC1 -* -* END OF TESTS -* - RT1 END - IHAEPIE - END diff --git a/src/az390.java b/src/az390.java index c2bf985ea..3e5c2600d 100644 --- a/src/az390.java +++ b/src/az390.java @@ -419,8 +419,13 @@ public class az390 implements Runnable { * 2022-05-10 AFK #398 fix typo in error message * 2022-05-12 DSH #325 issue error 54 invalid DC field terminator if not '..' for BDEFHLPXZ * 2022-06-10 DSH z16 #423 correct rotate instruction errors reported by Dan Greiner + * 2022-06-27 DSH z16 #424 add BFP constants INF, NAN, QNAN, SNAN, DMIN + * See POP 13 pages 9-5 and 19-4 + * 2022-07-03 DSH #414 add 30 new z16 instructions + * 2022-08-01 DSH #414 correct instruction formats VRI-f VRR-j and VRR-k * 2022-10-24 jjg #451 z390 ignores CODEPAGE option for input; * replace non-printable with '.' in PRN, BAL, PCH + * 2023-07-22 AFK #504 use named constants for floating point 'special values' ***************************************************** * Global variables last rpi *****************************************************/ @@ -1791,7 +1796,9 @@ else if (tz390.op_trace_type[index]==30) && !tz390.op_name[index].equals("RSCH") && !tz390.op_name[index].equals("SCHM") && !tz390.op_name[index].equals("SAL") - && !tz390.op_name[index].equals("XSCH")) + && !tz390.op_name[index].equals("XSCH") + && !tz390.op_name[index].equals("LBEAR") // DSH #414 z16 + ) {entry=entry+" D2(B2)"; } break; @@ -2632,7 +2639,8 @@ private void process_bal_op(){ loc_len = 4; get_hex_op(1,4); get_hex_zero(2); - if (bal_op.equals("PALB") // RPI 277 + if (bal_op.equals("NNPA") // DSH #414 z16 #504 + || bal_op.equals("PALB") // RPI 277 || bal_op.equals("PCKMO") // RPI 1125 || bal_op.equals("PCC")){ // RPI 1125 get_hex_zero(2); @@ -2818,8 +2826,12 @@ private void process_bal_op(){ loc_len = 6; get_hex_op(1,2); get_hex_bdddhh2(); + if (!bal_abort && exp_next_char(',')){ // DSH #414 z16 add support for EB71 LPSWEY D1(B1) witn no second opr skip_comma(); get_hex_byte(); + } else { + get_hex_zero(2); + } obj_code = obj_code.substring(0,2) + obj_code.substring(8,10) + obj_code.substring(2,8); get_hex_op(3,2); check_end_parms(); @@ -3026,13 +3038,17 @@ private void process_bal_op(){ loc_start = loc_ctr; loc_len = 4; get_hex_op(1,4); - get_hex_reg(); + get_hex_reg(); // r1 skip_comma(); - get_hex_reg(); + get_hex_reg(); // r3 skip_comma(); - get_hex_reg(); - skip_comma(); - get_hex_reg(); + get_hex_reg(); // r2 + if (!bal_abort && exp_next_char(',')){ // DSH #414 z16 make M4 optional for RDP + skip_comma(); + get_hex_reg(); // M4 + } else { + get_hex_zero(1); + } obj_code = obj_code.substring(0,4) // oooo + obj_code.substring(5,6) // r3 + obj_code.substring(7,8) // m4 @@ -3583,25 +3599,34 @@ private void process_bal_op(){ skip_comma(); get_hex_byte(); // I3 if (tz390.opt_traceall){ // DSHX debug RXSBGT - tz390.put_trace("RNSBG/RXSBG I3=" + exp_val + "obj_code=" + obj_code); + tz390.put_trace("RISBG/RNSBG/RXSBG I3=" + exp_val + "obj_code=" + obj_code); } if (!bal_abort && bal_op.length() == 6 && bal_op.charAt(5) == 'T'){ // turn on test bit if OP=?????T obj_code = obj_code.substring(0,obj_code.length()-2) + tz390.get_hex(((int)exp_val | (int)0x80),2); // DSH z16 #423 change + to | } - skip_comma(); - get_hex_byte(); // I4 - if (!bal_abort // RPI 1164 WAS 6 - && bal_op.charAt(bal_op.length()-1) == 'Z'){ // turn on XZERO bit if OP=??????Z // RPI 1164 RISBG/RISBGN - obj_code = obj_code.substring(0,obj_code.length()-2) + tz390.get_hex(((int)exp_val | (int)0x80),2); // DSH z16 #423 change + to | - } - if (exp_text.length() > exp_index - && exp_text.charAt(exp_index) == ','){ - skip_comma(); - get_hex_byte(); // I5 - } else { - get_hex_zero(2); // I5 default 0 rotate RPI 1164 was 1 + + if (tz390.op_code[bal_op_index].length() == 9){ //$i4i5 extension for SLLHH etc. DSH #414 z16 + // extended op (get i4,i5 from op_code "oooo33i4i5" + int i4 = Integer.valueOf(tz390.op_code[bal_op_index].substring(5,7)); + int i5 = Integer.valueOf(tz390.op_code[bal_op_index].substring(7,9)); + obj_code = obj_code + tz390.get_hex(i4,2); + obj_code = obj_code + tz390.get_hex(i5,2); + } else { + skip_comma(); + get_hex_byte(); // I4 + if (!bal_abort // RPI 1164 WAS 6 + && bal_op.charAt(bal_op.length()-1) == 'Z'){ // turn on XZERO bit if OP=??????Z // RPI 1164 RISBG/RISBGN + obj_code = obj_code.substring(0,obj_code.length()-2) + tz390.get_hex(((int)exp_val | (int)0x80),2); // DSH z16 #423 change + to | + } + if (exp_text.length() > exp_index + && exp_text.charAt(exp_index) == ','){ + skip_comma(); + get_hex_byte(); // I5 + } else { + get_hex_zero(2); // I5 default 0 rotate RPI 1164 was 1 + } } } get_hex_op(3,2); // OP2 @@ -4155,6 +4180,8 @@ private void process_bal_op(){ put_obj_text(); break; case 81: // "E649=VLIP,81,737", // E649 VRIh VLIP V1,I2,I3 RPI 2202 + // map E672 and E670 VRIf into oo1230miixoo + // map E772, e786, e787 VRId into oo1230iimxoo // map V1,R3,D2(B2) into oo03bddd1x00 bal_op_ok = true; loc_ctr = (loc_ctr+1)/2*2; @@ -4162,7 +4189,9 @@ private void process_bal_op(){ loc_len = 6; get_hex_op(1,2); // oo get_hex_vreg(1); // V1 - if (tz390.op_code[bal_op_index].substring(0,4).equals("E772") // E772 VRId VERIM V1,V2,V3,I4,M5 RPI 2202 + if (tz390.op_code[bal_op_index].substring(0,4).equals("E672") // E672 VRIf VSRPR V1,V2,V3,I4,M5 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E670") // E670 VRIf VPKZR V1,V2,V3,I4,M5 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E772") // E772 VRId VERIM V1,V2,V3,I4,M5 RPI 2202 || tz390.op_code[bal_op_index].substring(0,4).equals("E786") // E786 VRId VSLD V1,V2,V3,I4 RPI 2202 || tz390.op_code[bal_op_index].substring(0,4).equals("E787")) { // E787 VRId VSRD V1,V2,V3,I4 RPI 2202 skip_comma(); @@ -4171,16 +4200,24 @@ private void process_bal_op(){ get_hex_vreg(3); // V3 get_hex_zero(1); skip_comma(); - get_hex_byte(); // I4 - if ((tz390.op_code[bal_op_index].length() == 5)) { - get_hex_op(5,1); // M5 - } else { - if (!bal_abort && exp_next_char(',')){ - skip_comma(); - get_hex_reg(); // M4 - } else { - get_hex_zero(1); - } + get_hex_byte(); + if ((tz390.op_code[bal_op_index].length() == 5)) { + get_hex_op(5,1); // M5 + } else { // I4 + if (!bal_abort && exp_next_char(',')){ + skip_comma(); + get_hex_reg(); // M5 + } else { + get_hex_zero(1); // M5 + } + } + if (tz390.op_code[bal_op_index].substring(0,4).equals("E672") // E672 VRIf VSRPR V1,V2,V3,I4,M5 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E670")){ // E670 VRIf VPKZR V1,V2,V3,I4,M5 DSH #414 z16 + // VRIf so reverse i4 and m5 + // map E672 and E670 VRIf into oo1230miixoo + obj_code = obj_code.substring(0,6) // oo1230 + + obj_code.substring(8,9) // M3 + + obj_code.substring(6,8); // I3 } } else if (tz390.op_code[bal_op_index].substring(0,4).equals("E777")) { // E777 VLId VSLDB V1,V2,V3,I4 RPI 2202 skip_comma(); @@ -4351,13 +4388,29 @@ private void process_bal_op(){ skip_comma(); get_hex_reg(); // M3 get_hex_zero(2); - } else if (tz390.op_code[bal_op_index].substring(0,4).equals("E750") // E750 VRRa VPOPCT V1,V2,M3 + } else if ( tz390.op_code[bal_op_index].substring(0,4).equals("E654") // E654 VRRk VUPKZH V1,V2,M3 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E65C") // E65C VRRk VUPKZL V1,V2,M3 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E651") // E651 VRRk VCLZDP V1,V2,M3 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E750") // E750 VRRa VPOPCT V1,V2,M3 || tz390.op_code[bal_op_index].substring(0,4).equals("E752") // E752 VRRa VCTZ V1,V2,M3 || tz390.op_code[bal_op_index].substring(0,4).equals("E753") // E752 VRRa VCLZ V1,V2,M3 || tz390.op_code[bal_op_index].substring(0,4).equals("E75F")){ // E75F VRRa VSEG V1,V2,M3 get_hex_vreg(1); // V1 skip_comma(); get_hex_vreg(2); // V2 + // DSH #414 if VRRk format oo1200m00xoo vs oo120000mx00 + if ( tz390.op_code[bal_op_index].substring(0,4).equals("E654") // E654 VRRk VUPKZH V1,V2,M3 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E65C") // E65C VRRk VUPKZL V1,V2,M3 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E651")){ // E651 VRRk VCLZDP V1,V2,M3 DSH #414 z16 + get_hex_zero(2); + if (!bal_abort && exp_next_char(',')){ + skip_comma(); + get_hex_reg(); // M3 + get_hex_zero(2); + } else { + get_hex_op(5,1); // M3 + } + } else { get_hex_zero(4); if (!bal_abort && exp_next_char(',')){ skip_comma(); @@ -4365,7 +4418,9 @@ private void process_bal_op(){ } else { get_hex_op(5,1); // M3 } - } else if (tz390.op_code[bal_op_index].substring(0,4).equals("E760") // E760 VRRc VMRL V1,V2,V3,M4 + } + } else if ( tz390.op_code[bal_op_index].substring(0,4).equals("E67D") // E67D VRRj VCSPH V1,V2,V3,M4 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E760") // E760 VRRc VMRL V1,V2,V3,M4 || tz390.op_code[bal_op_index].substring(0,4).equals("E761") // E761 VRRc VMRH V1,V2,V3,M4 || tz390.op_code[bal_op_index].substring(0,4).equals("E764") // E764 VRRc VSUM V1,V2,V3,M4 || tz390.op_code[bal_op_index].substring(0,4).equals("E765") // E765 VRRc VSUMG V1,V2,V3,M4 @@ -4400,6 +4455,22 @@ private void process_bal_op(){ get_hex_vreg(2); // V2 skip_comma(); get_hex_vreg(3); // V3 + if ( tz390.op_code[bal_op_index].substring(0,4).equals("E67D")){ + // VRRj map oo1230m00xoo DSH #414 + get_hex_zero(1); + if (!bal_abort && exp_next_char(',')){ + skip_comma(); + get_hex_reg(); // M4 + } else { + if ((tz390.op_code[bal_op_index].length() == 5)) { + get_hex_op(5,1); // M4 + } else { + get_hex_zero(1); + } + } + get_hex_zero(2); + } else { + // VRRc map oo123000mxoo get_hex_zero(3); if (!bal_abort && exp_next_char(',')){ skip_comma(); @@ -4411,7 +4482,9 @@ private void process_bal_op(){ get_hex_zero(1); } } - } else if (tz390.op_code[bal_op_index].substring(0,4).equals("E7E2") // E7E2 VRRc VFS V1,V2,V3,M4,M5 + } + } else if (tz390.op_code[bal_op_index].substring(0,4).equals("E675") // E675 VRRc VCRNF V1,V2,V3,M4,M5 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E7E2") // E7E2 VRRc VFS V1,V2,V3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E7E3") // E7E3 VRRc VFA V1,V2,V3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E7E5") // E7E5 VRRc VFD V1,V2,V3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E7E7")) { // E7E7 VRRc VFM V1,V2,V3,M4,M5 @@ -4491,7 +4564,8 @@ private void process_bal_op(){ + obj_code.substring(8,9) // m6 + obj_code.substring(7,8) // m5 + obj_code.substring(6,7); // m4 - } else if (tz390.op_code[bal_op_index].substring(0,4).equals("E762") // E762 VRRf VLVGP V1,R2,R3 RPI 2202 + } else if ( tz390.op_code[bal_op_index].substring(0,4).equals("E67C") // E67C VRRf VSCSHP V1,V2,V3 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E762") // E762 VRRf VLVGP V1,R2,R3 RPI 2202 || tz390.op_code[bal_op_index].substring(0,4).equals("E766") // E766 VRRc VCKSM V1,V2,V3 RPI 2202 || tz390.op_code[bal_op_index].substring(0,4).equals("E768") // E768 VRRc VN V1,V2,V3 RPI 2202 || tz390.op_code[bal_op_index].substring(0,4).equals("E769") // E769 VRRc VNC V1,V2,V3 RPI 2202 @@ -4556,7 +4630,11 @@ private void process_bal_op(){ + obj_code.substring(8,9) // m5 + obj_code.substring(7,8) // m4 + obj_code.substring(6,7); // m3 - } else if ( tz390.op_code[bal_op_index].substring(0,4).equals("E7C0") // E7C0 VRRa VCLFP/VCLGD V1,V2,M3,M4,M5 + } else if ( tz390.op_code[bal_op_index].substring(0,4).equals("E655") // DSH #414 VCNF V1,V2,M3,M4 + || tz390.op_code[bal_op_index].substring(0,4).equals("E65D") // DSH #414 VCFN V1,V2,M3,M4 + || tz390.op_code[bal_op_index].substring(0,4).equals("E656") // DSH #414 VCLFNH V1,V2,M3,M4 + || tz390.op_code[bal_op_index].substring(0,4).equals("E65E") // DSH #414 VCLFNL V1,V2,M3,M4 + || tz390.op_code[bal_op_index].substring(0,4).equals("E7C0") // E7C0 VRRa VCLFP/VCLGD V1,V2,M3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E7C1") // E7C1 VRRa VCDLG V1,V2,M3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E7C2") // E7C2 VRRa VCGD V1,V2,M3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E7C3") // E7C3 VRRa VCDG V1,V2,M3,M4,M5 @@ -4575,7 +4653,8 @@ private void process_bal_op(){ || tz390.op_code[bal_op_index].substring(0,4).equals("E7D9") // E7D9 VRRa VECL V1,V2,M3 || tz390.op_code[bal_op_index].substring(0,4).equals("E7DB") // E7DB VRRa VEC V1,V2,M3 || tz390.op_code[bal_op_index].substring(0,4).equals("E7DE") // E7DE VRRa VLC V1,V2,M3 - || tz390.op_code[bal_op_index].substring(0,4).equals("E7DF")) { // E7DF VRRa VLP V1,V2,M3 + || tz390.op_code[bal_op_index].substring(0,4).equals("E7DF") + ) { // E7DF VRRa VLP V1,V2,M3 get_hex_vreg(1); // V1 skip_comma(); get_hex_vreg(2); // V2 @@ -4630,7 +4709,8 @@ private void process_bal_op(){ + obj_code.substring(8,9) // m5 + obj_code.substring(7,8) // m4 + obj_code.substring(6,7); // m3 - } else if (tz390.op_code[bal_op_index].substring(0,4).equals("E780") // E780 VRRb VFEE V1,V2,V3,M4,M5 + } else if ( tz390.op_code[bal_op_index].substring(0,4).equals("E674") // E674 VRRb VSCHP V1,V2,V3,M4,M5 DSH #414 z16 + || tz390.op_code[bal_op_index].substring(0,4).equals("E780") // E780 VRRb VFEE V1,V2,V3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E781") // E781 VRRb VFENE V1,V2,V3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E782") // E782 VRRb VFAE V1,V2,V3,M4,M5 || tz390.op_code[bal_op_index].substring(0,4).equals("E795") // E795 VRRb VPKLS V1,V2,V3,M4,M5 @@ -10853,6 +10933,8 @@ private void fp_get_hex(){ * set based on explicit decimal poiint * with significant trailing decimal places * including zeros else use 0. RPI 790 + * 5. Add issue #424 BFP constants INF, NAN, QNAN, SNAN, DMIN + * See POP 13 pages 9-5 and 19-4 * * First convert string constant to positive * big_dec1 value with sufficent sig. bits. @@ -10865,80 +10947,482 @@ private void fp_get_hex(){ } fp_text = remove_blanks(fp_text); // #233 if (fp_text.charAt(0) == '('){ // RPI 367 support (MIN) and (MAX) - if (fp_text.toUpperCase().equals("(MAX)")){ + if (fp_text.toUpperCase().equals("(MAX)") && fp_sign=='+'){ // #504 switch (tz390.fp_type){ // gen (max) hex for tz390.fp_type case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 - dc_hex = "7FEFFFFFFFFFFFFF"; + dc_hex = tz390.fp_db_pos_nmax; // #504 break; case 1: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 - dc_hex = "77FCFF3FCFF3FCFF"; // RPI 407 + dc_hex = tz390.fp_dd_pos_nmax; // RPI 407 #504 break; case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp - dc_hex = "7FFFFFFFFFFFFFFF"; + dc_hex = tz390.fp_dh_pos_nmax; // #504 break; case 3: // tz390.fp_eb_type s1,e8,m23 with assumed 1 - dc_hex = "7F7FFFFF"; + dc_hex = tz390.fp_eb_pos_nmax; // #504 break; case 4: // tz390.fp_ed_type s1,cf5,bxcf8,ccf50 - dc_hex = "77F3FCFF"; // RPI 407 + dc_hex = tz390.fp_ed_pos_nmax; // RPI 407 #504 break; case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp - dc_hex = "7FFFFFFF"; + dc_hex = tz390.fp_eh_pos_nmax; // #504 break; case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 - dc_hex = "7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; + dc_hex = tz390.fp_lb_pos_nmax; // #504 break; case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 - dc_hex = "77FFCFF3FCFF3FCFF3FCFF3FCFF3FCFF"; // RPI 407 + dc_hex = tz390.fp_ld_pos_nmax; // RPI 407 #504 break; + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex + dc_hex = tz390.fp_lh_pos_nmax; // #504 + break; + case 9: // tz390.fp_lq_type = lh_type, quadword aligned RPI 1108 #504 + dc_hex = tz390.fp_lh_pos_nmax; // #504 + break; + } + return; + } else if (fp_text.toUpperCase().equals("(MAX)") && fp_sign=='-'){ // #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type // #504 + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 // #504 + dc_hex = tz390.fp_db_neg_nmax; // #504 + break; // #504 + case 1: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 // #504 + dc_hex = tz390.fp_dd_neg_nmax; // #504 + break; // #504 + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp // #504 + dc_hex = tz390.fp_dh_neg_nmax; // #504 + break; // #504 + case 3: // tz390.fp_eb_type s1,e8,m23 with assumed 1 // #504 + dc_hex = tz390.fp_eb_neg_nmax; // #504 + break; // #504 + case 4: // tz390.fp_ed_type s1,cf5,bxcf8,ccf50 // #504 + dc_hex = tz390.fp_ed_neg_nmax; // #504 + break; // #504 + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp // #504 + dc_hex = tz390.fp_eh_neg_nmax; // #504 + break; // #504 + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 // #504 + dc_hex = tz390.fp_lb_neg_nmax; // #504 + break; // #504 + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 // #504 + dc_hex = tz390.fp_ld_neg_nmax; // #504 + break; // #504 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex // #504 + dc_hex = tz390.fp_lh_neg_nmax; // #504 + break; // #504 + case 9: // tz390.fp_lq_type = lh_type, quadword aligned RPI 1108 #504 + dc_hex = tz390.fp_lh_neg_nmax; // #504 + break; // #504 + } // #504 + return; // #504 + } else if (fp_text.toUpperCase().equals("(MIN)") && fp_sign=='+'){ // #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 + dc_hex = tz390.fp_db_pos_nmin; // #504 + break; + case 1: // tz390.fp_dd_type s1,cf5,bxcf8,ccf50 + dc_hex = tz390.fp_dd_pos_nmin; // RPI 407 #504 + break; + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp + dc_hex = tz390.fp_dh_pos_nmin; // #504 + break; + case 3: // tz390.fp_eb_type s1,e7,m24 with assumed 1 + dc_hex = tz390.fp_eb_pos_nmin; // #504 + break; + case 4: // tz390.fp_ed_type s1,cf5,bxcf6,ccf20 + dc_hex = tz390.fp_ed_pos_nmin; // RPI 407 #504 + break; + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp + dc_hex = tz390.fp_eh_pos_nmin; // #504 + break; + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 + dc_hex = tz390.fp_lb_pos_nmin; // #504 + break; + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 + dc_hex = tz390.fp_ld_pos_nmin; // RPI 407 #504 + break; + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex + dc_hex = tz390.fp_lh_pos_nmin; // #504 + break; + case 9: // tz390.fp_lq_type = lh_type, quadword aligned RPI 1108 #504 + dc_hex = tz390.fp_lh_pos_nmin; // #504 + break; + } + return; + } else if (fp_text.toUpperCase().equals("(MIN)") && fp_sign=='-'){ // #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type // #504 + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 // #504 + dc_hex = tz390.fp_db_neg_nmin; // #504 + break; // #504 + case 1: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 // #504 + dc_hex = tz390.fp_dd_neg_nmin; // #504 + break; // #504 + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp // #504 + dc_hex = tz390.fp_dh_neg_nmin; // #504 + break; // #504 + case 3: // tz390.fp_eb_type s1,e8,m23 with assumed 1 // #504 + dc_hex = tz390.fp_eb_neg_nmin; // #504 + break; // #504 + case 4: // tz390.fp_ed_type s1,cf5,bxcf8,ccf50 // #504 + dc_hex = tz390.fp_ed_neg_nmin; // #504 + break; // #504 + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp // #504 + dc_hex = tz390.fp_eh_neg_nmin; // #504 + break; // #504 + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 // #504 + dc_hex = tz390.fp_lb_neg_nmin; // #504 + break; // #504 + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 // #504 + dc_hex = tz390.fp_ld_neg_nmin; // #504 + break; // #504 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex // #504 + dc_hex = tz390.fp_lh_neg_nmin; // #504 + break; // #504 + case 9: // tz390.fp_lq_type = lh_type, quadword aligned RPI 1108 #504 + dc_hex = tz390.fp_lh_neg_nmin; // #504 + break; // #504 + } // #504 + return; // #504 + } else if (fp_text.toUpperCase().equals("(DMIN)") && fp_sign=='+'){// #504 + switch (tz390.fp_type){ // gen (DMIN) hex for tz390.fp_type + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 + dc_hex = tz390.fp_db_pos_dmin; // #504 + break; + case 1: // tz390.fp_dd_type s1,cf5,bxcf8,ccf50 + dc_hex = tz390.fp_dd_pos_dmin; // RPI 407 #504 + break; + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp + dc_hex = tz390.fp_dh_pos_dmin; // #504 + break; + case 3: // tz390.fp_eb_type s1,e7,m24 with assumed 1 + dc_hex = tz390.fp_eb_pos_dmin; // #504 + break; + case 4: // tz390.fp_ed_type s1,cf5,bxcf6,ccf20 + dc_hex = tz390.fp_ed_pos_dmin; // RPI 407 #504 + break; + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp + dc_hex = tz390.fp_eh_pos_dmin; // #504 + break; + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 + dc_hex = tz390.fp_lb_pos_dmin; // #504 + break; + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 + dc_hex = tz390.fp_ld_pos_dmin; // RPI 407 #504 + break; case 8: // tz390.fp_lh_type s1,e7,m112 with split hex - dc_hex = "7FFFFFFFFFFFFFFF71FFFFFFFFFFFFFF"; + dc_hex = tz390.fp_lh_pos_dmin; // #504 break; - case 9: // tz390.fp_lq_type quad word RPI 1108 - dc_hex = "00000000000000000000000000000000"; + case 9: // tz390.fp_lq_type = lh_type, quadword aligned RPI 1108 #504 + dc_hex = tz390.fp_lh_pos_dmin; // #504 + break; + } + return; + } else if (fp_text.toUpperCase().equals("(DMIN)") && fp_sign=='-'){// #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type // #504 + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 // #504 + dc_hex = tz390.fp_db_neg_dmin; // #504 + break; // #504 + case 1: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 // #504 + dc_hex = tz390.fp_dd_neg_dmin; // #504 + break; // #504 + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp // #504 + dc_hex = tz390.fp_dh_neg_dmin; // #504 + break; // #504 + case 3: // tz390.fp_eb_type s1,e8,m23 with assumed 1 // #504 + dc_hex = tz390.fp_eb_neg_dmin; // #504 + break; // #504 + case 4: // tz390.fp_ed_type s1,cf5,bxcf8,ccf50 // #504 + dc_hex = tz390.fp_ed_neg_dmin; // #504 + break; // #504 + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp // #504 + dc_hex = tz390.fp_eh_neg_dmin; // #504 + break; // #504 + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 // #504 + dc_hex = tz390.fp_lb_neg_dmin; // #504 + break; // #504 + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 // #504 + dc_hex = tz390.fp_ld_neg_dmin; // #504 + break; // #504 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex // #504 + dc_hex = tz390.fp_lh_neg_dmin; // #504 + break; // #504 + case 9: // tz390.fp_lq_type = lh_type, quadword aligned RPI 1108 #504 + dc_hex = tz390.fp_lh_neg_dmin; // #504 + break; // #504 + } // #504 + return; // #504 + } else if (fp_text.toUpperCase().equals("(INF)") && fp_sign=='+'){ // #423 #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 + dc_hex = tz390.fp_db_pos_inf; // #504 + break; + case 1: // tz390.fp_dd_type s1,cf5,bxcf8,ccf50 + dc_hex = tz390.fp_dd_pos_inf; // #504 + break; + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 3: // tz390.fp_eb_type s1,e7,m24 with assumed 1 + dc_hex = tz390.fp_eb_pos_inf; // #504 + break; + case 4: // tz390.fp_ed_type s1,cf5,bxcf6,ccf20 + dc_hex = tz390.fp_ed_pos_inf; // #504 break; + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 + dc_hex = tz390.fp_lb_pos_inf; // #504 + break; + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 + dc_hex = tz390.fp_ld_pos_inf; // RPI 407 #504 + break; + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 9: // tz390.fp_lq_type = lh_type, quadword aligned RPI 1108 #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; } - if (fp_sign == '-'){ - dc_hex = "F" + dc_hex.substring(1); + return; + } else if (fp_text.toUpperCase().equals("(INF)") && fp_sign=='-'){ // #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type // #504 + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 // #504 + dc_hex = tz390.fp_db_neg_inf; // #504 + break; // #504 + case 1: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 // #504 + dc_hex = tz390.fp_dd_neg_inf; // #504 + break; // #504 + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 3: // tz390.fp_eb_type s1,e8,m23 with assumed 1 // #504 + dc_hex = tz390.fp_eb_neg_inf; // #504 + break; // #504 + case 4: // tz390.fp_ed_type s1,cf5,bxcf8,ccf50 // #504 + dc_hex = tz390.fp_ed_neg_inf; // #504 + break; // #504 + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 // #504 + dc_hex = tz390.fp_lb_neg_inf; // #504 + break; // #504 + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 // #504 + dc_hex = tz390.fp_ld_neg_inf; // #504 + break; // #504 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 9: // tz390.fp_lq_type = lh_type, quadword aligned // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + } // #504 + return; // #504 + } else if (fp_text.toUpperCase().equals("(NAN)") && fp_sign=='+'){ // #423 504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 + dc_hex = tz390.fp_db_pos_nan; // #504 + break; + case 1: // tz390.fp_dd_type s1,cf5,bxcf8,ccf50 + dc_hex = tz390.fp_dd_pos_nan; // #504 + break; + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 3: // tz390.fp_eb_type s1,e7,m24 with assumed 1 + dc_hex = tz390.fp_eb_pos_nan; // #504 + break; + case 4: // tz390.fp_ed_type s1,cf5,bxcf6,ccf20 + dc_hex = tz390.fp_ed_pos_nan; // #504 + break; + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 + dc_hex = tz390.fp_lb_pos_nan; // #504 + break; + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 + dc_hex = tz390.fp_ld_pos_nan; // RPI 407 #504 + break; + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 9: // tz390.fp_lq_type quad word RPI 1108 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; } return; - } else if (fp_text.toUpperCase().equals("(MIN)")){ + } else if (fp_text.toUpperCase().equals("(NAN)") && fp_sign=='-'){ // #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type // #504 + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 // #504 + dc_hex = tz390.fp_db_neg_nan; // #504 + break; // #504 + case 1: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 // #504 + dc_hex = tz390.fp_dd_neg_nan; // #504 + break; // #504 + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 3: // tz390.fp_eb_type s1,e8,m23 with assumed 1 // #504 + dc_hex = tz390.fp_eb_neg_nan; // #504 + break; // #504 + case 4: // tz390.fp_ed_type s1,cf5,bxcf8,ccf50 // #504 + dc_hex = tz390.fp_ed_neg_nan; // #504 + break; // #504 + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 // #504 + dc_hex = tz390.fp_lb_neg_nan; // #504 + break; // #504 + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 // #504 + dc_hex = tz390.fp_ld_neg_nan; // #504 + break; // #504 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 9: // tz390.fp_lq_type = lh_type, quadword aligned // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + } // #504 + return; // #504 + } else if (fp_text.toUpperCase().equals("(QNAN)") && fp_sign=='+'){// #423 #504 switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 - dc_hex = "0010000000000000"; + dc_hex = tz390.fp_db_pos_qnan; // #504 break; case 1: // tz390.fp_dd_type s1,cf5,bxcf8,ccf50 - dc_hex = "0000000000000001"; // RPI 407 + dc_hex = tz390.fp_dd_pos_qnan; // #504 break; case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp - dc_hex = "0110000000000000"; + log_error(112,fp_text + " not defined as hex fp value"); // #504 break; case 3: // tz390.fp_eb_type s1,e7,m24 with assumed 1 - dc_hex = "00800000"; + dc_hex = tz390.fp_eb_pos_qnan; // #504 break; - case 4: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 - dc_hex = "00000001"; // RPI 407 + case 4: // tz390.fp_ed_type s1,cf5,bxcf6,ccf20 + dc_hex = tz390.fp_ed_pos_qnan; // #504 break; case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp - dc_hex = "01100000"; + log_error(112,fp_text + " not defined as hex fp value"); // #504 break; case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 - dc_hex = "00010000000000000000000000000000"; + dc_hex = tz390.fp_lb_pos_qnan; // #504 break; case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 - dc_hex = "00000000000000000000000000000001"; // RPI 407 + dc_hex = tz390.fp_ld_pos_qnan; // #504 break; case 8: // tz390.fp_lh_type s1,e7,m112 with split hex - dc_hex = "01100000000000007200000000000000"; + log_error(112,fp_text + " not defined as hex fp value"); // #504 break; case 9: // tz390.fp_lq_type quad word RPI 1108 - dc_hex = "00000000000000000000000000000000"; + log_error(112,fp_text + " not defined as hex fp value"); // #504 break; } - if (fp_sign == '-'){ - dc_hex = "8" + dc_hex.substring(1); + return; + } else if (fp_text.toUpperCase().equals("(QNAN)") && fp_sign=='-'){// #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type // #504 + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 // #504 + dc_hex = tz390.fp_db_neg_qnan; // #504 + break; // #504 + case 1: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 // #504 + dc_hex = tz390.fp_dd_neg_qnan; // #504 + break; // #504 + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 3: // tz390.fp_eb_type s1,e8,m23 with assumed 1 // #504 + dc_hex = tz390.fp_eb_neg_qnan; // #504 + break; // #504 + case 4: // tz390.fp_ed_type s1,cf5,bxcf8,ccf50 // #504 + dc_hex = tz390.fp_ed_neg_qnan; // #504 + break; // #504 + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 // #504 + dc_hex = tz390.fp_lb_neg_qnan; // #504 + break; // #504 + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 // #504 + dc_hex = tz390.fp_ld_neg_qnan; // #504 + break; // #504 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 9: // tz390.fp_lq_type = lh_type, quadword aligned // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + } // #504 + return; // #504 + } else if (fp_text.toUpperCase().equals("(SNAN)") && fp_sign=='+'){// #423 #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 + dc_hex = tz390.fp_db_pos_snan; // #504 + break; + case 1: // tz390.fp_dd_type s1,cf5,bxcf8,ccf50 + dc_hex = tz390.fp_dd_pos_snan; // #504 + break; + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 3: // tz390.fp_eb_type s1,e7,m24 with assumed 1 + dc_hex = tz390.fp_eb_pos_snan; // #504 + break; + case 4: // tz390.fp_ed_type s1,cf5,bxcf6,ccf20 + dc_hex = tz390.fp_ed_pos_snan; // RPI 407 #504 + break; + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 + dc_hex = tz390.fp_lb_pos_snan; // #504 + break; + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 + dc_hex = tz390.fp_ld_pos_snan; // RPI 407 #504 + break; + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; + case 9: // tz390.fp_lq_type quad word RPI 1108 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; } return; + } else if (fp_text.toUpperCase().equals("(SNAN)") && fp_sign=='-'){// #504 + switch (tz390.fp_type){ // gen (min) hex for tz390.fp_type // #504 + case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 // #504 + dc_hex = tz390.fp_db_neg_snan; // #504 + break; // #504 + case 1: // tz390.fp_dd_type s1,cf5,bxcf6,ccf20 // #504 + dc_hex = tz390.fp_dd_neg_snan; // #504 + break; // #504 + case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 3: // tz390.fp_eb_type s1,e8,m23 with assumed 1 // #504 + dc_hex = tz390.fp_eb_neg_snan; // #504 + break; // #504 + case 4: // tz390.fp_ed_type s1,cf5,bxcf8,ccf50 // #504 + dc_hex = tz390.fp_ed_neg_snan; // #504 + break; // #504 + case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 // #504 + dc_hex = tz390.fp_lb_neg_snan; // #504 + break; // #504 + case 7: // tz390.fp_ld_type s1,cf5,bxcf12,ccf110 // #504 + dc_hex = tz390.fp_ld_neg_snan; // #504 + break; // #504 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + case 9: // tz390.fp_lq_type = lh_type, quadword aligned // #504 + log_error(112,fp_text + " not defined as hex fp value"); // #504 + break; // #504 + } // #504 + return; // #504 } else { log_error(112,"unrecognized floating point constant " + fp_text); } @@ -10953,7 +11437,7 @@ private void fp_get_hex(){ if (dc_exp > 0){ // RPI 368 adj by DC E modifer fp_big_dec1 = fp_big_dec1.movePointLeft(dc_exp); } else if (dc_exp < 0){ - fp_big_dec1 = fp_big_dec1.movePointRight(-dc_exp); + fp_big_dec1 = fp_big_dec1.movePointRight(-dc_exp); } if (fp_big_dec1.signum() > 0){ if (fp_sign == '+'){ // RPI 834 @@ -10964,68 +11448,68 @@ private void fp_get_hex(){ } else if (fp_sign == '+'){ // RPI 834 switch (tz390.fp_type){ // gen zero hex for tz390.fp_type case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 - dc_hex = "0000000000000000"; // RPI 384 + dc_hex = tz390.fp_db_pos_zero; // RPI 384 #504 return; case 1: // tz390.fp_dd_type s1,cf5,bxcf8,ccf50 // RPI 407 - dc_hex = "2238000000000000"; // RPI 384 RPI 790 + dc_hex = tz390.fp_dd_pos_zero; // RPI 384 RPI 790 #504 return; case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp - dc_hex = "0000000000000000"; // RPI 384 + dc_hex = tz390.fp_dh_pos_zero; // RPI 384 #504 return; case 3: // tz390.fp_eb_type s1,e7,m24 with assumed 1 - dc_hex = "00000000"; // RPI 384 + dc_hex = tz390.fp_eb_pos_zero; // RPI 384 #504 return; case 4: // tz390.fp_ed_type s1,cf5,bxdf6,ccf20 // RPI 407 - dc_hex = "22500000"; // RPI 384 RPI 790 + dc_hex = tz390.fp_ed_pos_zero; // RPI 384 RPI 790 #504 return; case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp - dc_hex = "00000000"; // RPI 384 + dc_hex = tz390.fp_eh_pos_zero; // RPI 384 #504 return; case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 - dc_hex = "00000000000000000000000000000000"; // RPI 384 + dc_hex = tz390.fp_lb_pos_zero; // RPI 384 #504 return; case 7: // tz390.fp_ld_type s1,cf5,bxdf12,ccf110 // RPI 407 - dc_hex = "22080000000000000000000000000000"; // RPI 384 RPI 790 + dc_hex = tz390.fp_ld_pos_zero; // RPI 384 RPI 790 #504 return; - case 8: // tz390.fp_lh_type s1,e7,m112 with split hex - dc_hex = "00000000000000000000000000000000"; // RPI 384 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex + dc_hex = tz390.fp_lh_pos_zero; // RPI 384 #504 return; case 9: // tz390.fp_lq_type quad word RPI 1108 - dc_hex = "00000000000000000000000000000000"; + dc_hex = tz390.fp_lh_pos_zero; // #504 break; } } else { // RPI 834 negative zero values switch (tz390.fp_type){ // gen zero hex for tz390.fp_type case 0: // tz390.fp_db_type s1,e11,m52 with assumed 1 - dc_hex = "8000000000000000"; // RPI 384 + dc_hex = tz390.fp_db_neg_zero; // RPI 384 #504 return; case 1: // tz390.fp_dd_type s1,cf5,bxcf8,ccf50 // RPI 407 - dc_hex = "A238000000000000"; // RPI 384 RPI 790 + dc_hex = tz390.fp_dd_neg_zero; // RPI 384 RPI 790 #504 return; case 2: // tz390.fp_dh_type s1,e7,m56 with hex exp - dc_hex = "8000000000000000"; // RPI 384 + dc_hex = tz390.fp_dh_neg_zero; // RPI 384 #504 return; case 3: // tz390.fp_eb_type s1,e7,m24 with assumed 1 - dc_hex = "80000000"; // RPI 384 + dc_hex = tz390.fp_eb_neg_zero; // RPI 384 #504 return; case 4: // tz390.fp_ed_type s1,cf5,bxdf6,ccf20 // RPI 407 - dc_hex = "A2500000"; // RPI 384 RPI 790 + dc_hex = tz390.fp_ed_neg_zero; // RPI 384 RPI 790 #504 return; case 5: // tz390.fp_eh_type s1,e7,m24 with hex exp - dc_hex = "80000000"; // RPI 384 + dc_hex = tz390.fp_eh_neg_zero; // RPI 384 #504 return; case 6: // tz390.fp_lb_type s1,e15,m112 with assumed 1 - dc_hex = "80000000000000000000000000000000"; // RPI 384 + dc_hex = tz390.fp_lb_neg_zero; // RPI 384 #504 return; case 7: // tz390.fp_ld_type s1,cf5,bxdf12,ccf110 // RPI 407 - dc_hex = "A2080000000000000000000000000000"; // RPI 384 RPI 790 + dc_hex = tz390.fp_ld_neg_zero; // RPI 384 RPI 790 #504 return; - case 8: // tz390.fp_lh_type s1,e7,m112 with split hex - dc_hex = "80000000000000000000000000000000"; // RPI 384 + case 8: // tz390.fp_lh_type s1,e7,m112 with split hex + dc_hex = tz390.fp_lh_neg_zero; // RPI 384 #504 return; case 9: // tz390.fp_lq_type quad word RPI 1108 - dc_hex = "00000000000000000000000000000000"; - break; + dc_hex = tz390.fp_lh_neg_zero; // #504 + break; } } /* diff --git a/src/tz390.java b/src/tz390.java index 54b922ecd..6dee125f9 100644 --- a/src/tz390.java +++ b/src/tz390.java @@ -327,6 +327,7 @@ public class tz390 { * 2023-06-21 AFK #485 fix O attribute value for extended mnemonics * 2023-06-22 AFK #495 fix O attribure value for vector instructions * 2023-07-02 DSH/AFK #503 add support for new z16 instructions to opcode tables + * 2023-07-16 AFK #504 create named constants for floating point 'special values' ******************************************************** * Shared z390 tables (last RPI) *****************************************************/ @@ -829,6 +830,165 @@ public class tz390 { byte fp_ld_digits = 34; byte fp_lh_digits = 32; // RPI 821 byte fp_guard_digits = 4; // RPI 1124 + /* // #504 + * Constants with special values for various fp formats // #504 + * Constants are defined as Hex strings, because that is how they are used in az390 // #504 + * Java has no native types to store 16-byte values, this solution circumvents that limitation // #504 + * // #504 + * A note about nomenclature for below constants: // #504 + * the first syllable is fp for floating point // #504 + * the second syllable encodes the length and type of floating point literal // #504 + * lengths are modelled after DC/DS: e=short, d=double, x=extended, t=tiny // #504 + * this contratst with instruction mnemonics. these use e, d, l instead of e, d, x // #504 + * floating point types are encoded as: b=binary, h=hex, d=decimal // #504 + * the third syllable encodes the sign: pos for positive and neg for negative // #504 + * the fourth syllable defines the constant being encoded. The names follow (where possible) // #504 + * the naming in figure 9.1 in Principles of Operation version 13: // #504 + * nmax = largest (in magnitude) representable normalized/ normal number // #504 + * nmin = smallest (in magnitude) representable normalized/ normal number other than zero// #504 + * dmin = smallest (in magnitude) representable unnormalized/subnormal number other than zero// #504 + * zero = zero // #504 + * inf = infinity (bfp/dfp only) // #504 + * snan = signalling not-a-number (bfp/dfp only) // #504 + * qnan = quiet not-a-number (bfp/dfp only) // #504 + * nan = default not-a-number (bfp/dfp only) // #504 + */ // #504 + String fp_eh_pos_nmax = "7FFFFFFF"; // Ehrman v2 par 33.4.2 // #504 + String fp_eh_pos_nmin = "00100000"; // Ehrman v2 par 33.4.2 // #504 + String fp_eh_pos_dmin = "00000001"; // Ehrman v2 par 33.4.2 // #504 + String fp_eh_pos_zero = "00000000"; // PoP v13 figure 9-2 // #504 + String fp_eh_neg_nmax = "FFFFFFFF"; // #504 + String fp_eh_neg_nmin = "80100000"; // #504 + String fp_eh_neg_dmin = "80000001"; // #504 + String fp_eh_neg_zero = "80000000"; // PoP v13 figure 9-2 // #504 + String fp_dh_pos_nmax = "7FFFFFFFFFFFFFFF"; // Ehrman v2 par 33.4.2 // #504 + String fp_dh_pos_nmin = "0010000000000000"; // Ehrman v2 par 33.4.2 // #504 + String fp_dh_pos_dmin = "0000000000000001"; // Ehrman v2 par 33.4.2 // #504 + String fp_dh_pos_zero = "0000000000000000"; // PoP v13 figure 9-2 // #504 + String fp_dh_neg_nmax = "FFFFFFFFFFFFFFFF"; // #504 + String fp_dh_neg_nmin = "8010000000000000"; // #504 + String fp_dh_neg_dmin = "8000000000000001"; // #504 + String fp_dh_neg_zero = "8000000000000000"; // PoP v13 figure 9-2 // #504 + String fp_lh_pos_nmax = "7FFFFFFFFFFFFFFF71FFFFFFFFFFFFFF"; // Ehrman v2 par 33.4.2 // #504 + String fp_lh_pos_nmin = "00100000000000007200000000000000"; // Ehrman v2 par 33.4.2 // #504 + String fp_lh_pos_dmin = "00000000000000007200000000000001"; // Ehrman v2 par 33.4.2 // #504 + String fp_lh_pos_zero = "00000000000000000000000000000000"; // PoP v13 figure 9-2 // #504 + String fp_lh_neg_nmax = "FFFFFFFFFFFFFFFFF1FFFFFFFFFFFFFF"; // #504 + String fp_lh_neg_nmin = "8010000000000000F200000000000000"; // #504 + String fp_lh_neg_dmin = "8000000000000000F200000000000001"; // #504 + String fp_lh_neg_zero = "80000000000000000000000000000000"; // PoP v13 figure 9-2 // #504 + String fp_tb_pos_nmax = "7BFF"; // #504 + String fp_tb_pos_nmin = "0400"; // PoP v13 page 19-3 // #504 + String fp_tb_pos_dmin = "0001"; // #504 + String fp_tb_pos_zero = "0000"; // PoP v13 figure 9-2 // #504 + String fp_tb_pos_inf = "7C00"; // #504 + String fp_tb_pos_snan = "7D00"; // #504 + String fp_tb_pos_qnan = "7F00"; // #504 + String fp_tb_pos_nan = "7E00"; // #504 + String fp_tb_neg_nmax = "FBFF"; // #504 + String fp_tb_neg_nmin = "8400"; // PoP v13 page 19-3 // #504 + String fp_tb_neg_dmin = "8001"; // #504 + String fp_tb_neg_zero = "8000"; // PoP v13 figure 9-2 // #504 + String fp_tb_neg_inf = "FC00"; // #504 + String fp_tb_neg_snan = "FD00"; // #504 + String fp_tb_neg_qnan = "FF00"; // #504 + String fp_tb_neg_nan = "FE00"; // #504 + String fp_eb_pos_nmax = "7F7FFFFF"; // Ehrman v2 par 34.2 // #504 + String fp_eb_pos_nmin = "00800000"; // Ehrman v2 par 34.2 // #504 + String fp_eb_pos_dmin = "00000001"; // Ehrman v2 par 34.2 // #504 + String fp_eb_pos_zero = "00000000"; // PoP v13 figure 9-2 // #504 + String fp_eb_pos_inf = "7F800000"; // Ehrman v2 par 34.2 // #504 + String fp_eb_pos_snan = "7FA00000"; // Ehrman v2 par 34.2 // #504 + String fp_eb_pos_qnan = "7FE00000"; // Ehrman v2 par 34.2 // #504 + String fp_eb_pos_nan = "7FC00000"; // Ehrman v2 par 34.2 // #504 + String fp_eb_neg_nmax = "FF7FFFFF"; // #504 + String fp_eb_neg_nmin = "80800000"; // #504 + String fp_eb_neg_dmin = "80000001"; // #504 + String fp_eb_neg_zero = "80000000"; // PoP v13 figure 9-2 // #504 + String fp_eb_neg_inf = "FF800000"; // #504 + String fp_eb_neg_snan = "FFA00000"; // #504 + String fp_eb_neg_qnan = "FFE00000"; // #504 + String fp_eb_neg_nan = "FFC00000"; // #504 + String fp_db_pos_nmax = "7FEFFFFFFFFFFFFF"; // Ehrman v2 par 34.2 // #504 + String fp_db_pos_nmin = "0010000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_db_pos_dmin = "0000000000000001"; // Ehrman v2 par 34.2 // #504 + String fp_db_pos_zero = "0000000000000000"; // PoP v13 figure 9-2 // #504 + String fp_db_pos_inf = "7FF0000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_db_pos_snan = "7FF4000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_db_pos_qnan = "7FFC000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_db_pos_nan = "7FF8000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_db_neg_nmax = "FFEFFFFFFFFFFFFF"; // #504 + String fp_db_neg_nmin = "8010000000000000"; // #504 + String fp_db_neg_dmin = "8000000000000001"; // #504 + String fp_db_neg_zero = "8000000000000000"; // PoP v13 figure 9-2 // #504 + String fp_db_neg_inf = "FFF0000000000000"; // #504 + String fp_db_neg_snan = "FFF4000000000000"; // #504 + String fp_db_neg_qnan = "FFFC000000000000"; // #504 + String fp_db_neg_nan = "FFF8000000000000"; // #504 + String fp_lb_pos_nmax = "7FFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; // Ehrman v2 par 34.2 // #504 + String fp_lb_pos_nmin = "00010000000000000000000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_lb_pos_dmin = "00000000000000000000000000000001"; // Ehrman v2 par 34.2 // #504 + String fp_lb_pos_zero = "00000000000000000000000000000000"; // PoP v13 figure 9-2 // #504 + String fp_lb_pos_inf = "7FFF0000000000000000000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_lb_pos_snan = "7FFF4000000000000000000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_lb_pos_qnan = "7FFFC000000000000000000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_lb_pos_nan = "7FFF8000000000000000000000000000"; // Ehrman v2 par 34.2 // #504 + String fp_lb_neg_nmax = "FFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; // #504 + String fp_lb_neg_nmin = "80010000000000000000000000000000"; // #504 + String fp_lb_neg_dmin = "80000000000000000000000000000001"; // #504 + String fp_lb_neg_zero = "80000000000000000000000000000000"; // PoP v13 figure 9-2 // #504 + String fp_lb_neg_inf = "FFFF0000000000000000000000000000"; // #504 + String fp_lb_neg_snan = "FFFF4000000000000000000000000000"; // #504 + String fp_lb_neg_qnan = "FFFFC000000000000000000000000000"; // #504 + String fp_lb_neg_nan = "FFFF8000000000000000000000000000"; // #504 + String fp_ed_pos_nmax = "77F3FCFF"; // Ehrman v2 par 35.3 // #504 + String fp_ed_pos_nmin = "04000000"; // Ehrman v2 par 35.3 // #504 + String fp_ed_pos_dmin = "00000001"; // Ehrman v2 par 35.3 // #504 + String fp_ed_pos_zero = "22500000"; // PoP v13 figure 9-2 // #504 + String fp_ed_pos_inf = "78000000"; // Ehrman v2 par 35.3 // #504 + String fp_ed_pos_snan = "7E000000"; // Ehrman v2 par 35.3 // #504 + String fp_ed_pos_qnan = "7C000000"; // Ehrman v2 par 35.3 // #504 + String fp_ed_pos_nan = "7C000000"; // Ehrman v2 par 35.3 // #504 + String fp_ed_neg_nmax = "F7F3FCFF"; // #504 + String fp_ed_neg_nmin = "84000000"; // #504 + String fp_ed_neg_dmin = "80000001"; // #504 + String fp_ed_neg_zero = "A2500000"; // PoP v13 figure 9-2 // #504 + String fp_ed_neg_inf = "F8000000"; // #504 + String fp_ed_neg_snan = "FE000000"; // #504 + String fp_ed_neg_qnan = "FC000000"; // #504 + String fp_ed_neg_nan = "FC000000"; // #504 + String fp_dd_pos_nmax = "77FCFF3FCFF3FCFF"; // Ehrman v2 par 35.3 // #504 + String fp_dd_pos_nmin = "0400000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_dd_pos_dmin = "0000000000000001"; // Ehrman v2 par 35.3 // #504 + String fp_dd_pos_zero = "2238000000000000"; // PoP v13 figure 9-3 // #504 + String fp_dd_pos_inf = "7800000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_dd_pos_snan = "7E00000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_dd_pos_qnan = "7C00000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_dd_pos_nan = "7C00000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_dd_neg_nmax = "F7FCFF3FCFF3FCFF"; // #504 + String fp_dd_neg_nmin = "8400000000000000"; // #504 + String fp_dd_neg_dmin = "8000000000000001"; // #504 + String fp_dd_neg_zero = "A238000000000000"; // PoP v13 figure 9-3 // #504 + String fp_dd_neg_inf = "F800000000000000"; // #504 + String fp_dd_neg_snan = "FE00000000000000"; // #504 + String fp_dd_neg_qnan = "FC00000000000000"; // #504 + String fp_dd_neg_nan = "FC00000000000000"; // #504 + String fp_ld_pos_nmax = "77FFCFF3FCFF3FCFF3FCFF3FCFF3FCFF"; // Ehrman v2 par 35.3 // #504 + String fp_ld_pos_nmin = "04000000000000000000000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_ld_pos_dmin = "00000000000000000000000000000001"; // Ehrman v2 par 35.3 // #504 + String fp_ld_pos_zero = "22080000000000000000000000000000"; // PoP v13 figures 20-1+20-3 // #504 + String fp_ld_pos_inf = "78000000000000000000000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_ld_pos_snan = "7E000000000000000000000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_ld_pos_qnan = "7C000000000000000000000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_ld_pos_nan = "7C000000000000000000000000000000"; // Ehrman v2 par 35.3 // #504 + String fp_ld_neg_nmax = "F7FFCFF3FCFF3FCFF3FCFF3FCFF3FCFF"; // #504 + String fp_ld_neg_nmin = "84000000000000000000000000000000"; // #504 + String fp_ld_neg_dmin = "80000000000000000000000000000001"; // #504 + String fp_ld_neg_zero = "A2080000000000000000000000000000"; // PoP v13 figures 20-1+20-3 // #504 + String fp_ld_neg_inf = "F8000000000000000000000000000000"; // #504 + String fp_ld_neg_snan = "FE000000000000000000000000000000"; // #504 + String fp_ld_neg_qnan = "FC000000000000000000000000000000"; // #504 + String fp_ld_neg_nan = "FC000000000000000000000000000000"; // #504 /* * follow fp_work_reg used to format * edl types to binary storage formats