Add generic wolfHAL Ethernet port with STM32H563ZI Nucleo board support

Author: AlexLanzano

src/port/wolfHAL/.gitignore

@@ -0,0 +1 @@
+build/

src/port/wolfHAL/Makefile

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+ROOT = $(CURDIR)/../../..
+PORT_DIR = $(ROOT)/src/port/wolfHAL
+
+BOARD_DIR = $(PORT_DIR)/boards/$(BOARD)
+
+ifeq ($(BOARD),)
+  ifeq ($(MAKECMDGOALS),clean)
+    clean:
+	rm -rf build
+    .PHONY: clean
+  else
+    $(error BOARD is required. Usage: make BOARD=stm32h563zi_nucleo)
+  endif
+else
+include $(BOARD_DIR)/board.mk
+
+SOURCE = $(PORT_DIR)/main.c
+SOURCE += $(PORT_DIR)/wolfhal_eth.c
+SOURCE += $(ROOT)/src/wolfip.c
+SOURCE += $(BOARD_SOURCE)
+
+BUILD_DIR = build/$(BOARD)
+OBJECTS = $(patsubst %.c,$(BUILD_DIR)/%.o,$(SOURCE))
+DEPENDS = $(OBJECTS:.o=.d)
+
+all: $(BUILD_DIR)/app.bin
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	@mkdir -p $(dir $@)
+	$(GCC) $(CFLAGS) -c -o $@ $<
+
+.SECONDARY:
+$(BUILD_DIR)/%.elf: $(OBJECTS) $(LINKER_SCRIPT)
+	@mkdir -p $(dir $@)
+	$(GCC) $(CFLAGS) $(LDFLAGS) -T $(LINKER_SCRIPT) -o $@ $(OBJECTS) $(LDLIBS)
+
+$(BUILD_DIR)/%.bin: $(BUILD_DIR)/%.elf
+	$(OBJCOPY) $^ -O binary $@
+
+.PHONY: clean size
+clean:
+	rm -rf build
+
+size: $(BUILD_DIR)/app.elf
+	arm-none-eabi-size $<
+
+-include $(DEPENDS)
+
+endif

src/port/wolfHAL/boards/stm32h563zi_nucleo/board.c

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+/* board.c
+ *
+ * Copyright (C) 2024-2026 wolfSSL Inc.
+ *
+ * Minimal board configuration for STM32H563ZI Nucleo-144
+ * Only sets up what's needed for wolfIP: clocks, GPIO, Ethernet, PHY.
+ *
+ * This file is part of wolfIP TCP/IP stack.
+ *
+ * wolfIP is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfIP is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include "board.h"
+#include <wolfHAL/platform/st/stm32h563xx.h>
+#include <wolfHAL/eth_phy/lan8742a.h>
+
+/* SysTick timing */
+volatile uint32_t g_tick = 0;
+
+void SysTick_Handler(void)
+{
+    g_tick++;
+}
+
+uint32_t board_get_tick(void)
+{
+    return g_tick;
+}
+
+whal_Timeout g_whalTimeout = {
+    .timeoutTicks = 1000,
+    .GetTick = board_get_tick,
+};
+
+/* Clock: PLL1 from HSI to 168 MHz */
+static whal_Clock clock = {
+    WHAL_STM32H563_RCC_PLL_DEVICE,
+
+    .cfg = &(whal_Stm32h5Rcc_Cfg) {
+        .sysClkSrc = WHAL_STM32H5_RCC_SYSCLK_SRC_PLL1,
+        .sysClkCfg = &(whal_Stm32h5Rcc_PllClkCfg) {
+            .clkSrc = WHAL_STM32H5_RCC_PLLCLK_SRC_HSI,
+            .m = 8,
+            .n = 62,
+            .p = 2,
+            .q = 2,
+            .r = 2,
+        },
+    },
+};
+
+static const whal_Stm32h5Rcc_Clk clocks[] = {
+    {WHAL_STM32H563_GPIOA_CLOCK},
+    {WHAL_STM32H563_GPIOB_CLOCK},
+    {WHAL_STM32H563_GPIOC_CLOCK},
+    {WHAL_STM32H563_GPIOD_CLOCK},
+    {WHAL_STM32H563_GPIOG_CLOCK},
+    {WHAL_STM32H563_USART2_CLOCK},
+    {WHAL_STM32H563_SBS_CLOCK},
+};
+#define CLOCK_COUNT (sizeof(clocks) / sizeof(clocks[0]))
+
+static const whal_Stm32h5Rcc_Clk eth_clocks[] = {
+    {WHAL_STM32H563_ETH_CLOCK},
+    {WHAL_STM32H563_ETHTX_CLOCK},
+    {WHAL_STM32H563_ETHRX_CLOCK},
+};
+#define ETH_CLOCK_COUNT (sizeof(eth_clocks) / sizeof(eth_clocks[0]))
+
+/* GPIO: only RMII pins */
+static whal_Gpio gpio = {
+    WHAL_STM32H563_GPIO_DEVICE,
+
+    .cfg = &(whal_Stm32h5Gpio_Cfg) {
+        .pinCfg = (whal_Stm32h5Gpio_PinCfg[PIN_COUNT]) {
+            [UART_TX_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_D, 5, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST,
+                WHAL_STM32H5_GPIO_PULL_UP, 7),
+            [UART_RX_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_D, 6, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                WHAL_STM32H5_GPIO_OUTTYPE_PUSHPULL, WHAL_STM32H5_GPIO_SPEED_FAST,
+                WHAL_STM32H5_GPIO_PULL_UP, 7),
+            [ETH_RMII_REF_CLK_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_A, 1, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+            [ETH_RMII_MDIO_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_A, 2, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+            [ETH_RMII_MDC_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_C, 1, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+            [ETH_RMII_CRS_DV_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_A, 7, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+            [ETH_RMII_RXD0_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_C, 4, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+            [ETH_RMII_RXD1_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_C, 5, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+            [ETH_RMII_TX_EN_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_G, 11, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+            [ETH_RMII_TXD0_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_G, 13, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+            [ETH_RMII_TXD1_PIN] = WHAL_STM32H5_GPIO_PIN(
+                WHAL_STM32H5_GPIO_PORT_B, 15, WHAL_STM32H5_GPIO_MODE_ALTFN,
+                0, WHAL_STM32H5_GPIO_SPEED_HIGH,
+                WHAL_STM32H5_GPIO_PULL_NONE, 11),
+        },
+        .pinCount = PIN_COUNT,
+    },
+};
+
+/* Timer: SysTick at 1 ms */
+static whal_Timer timer = {
+    WHAL_CORTEX_M33_SYSTICK_DEVICE,
+
+    .cfg = &(whal_SysTick_Cfg) {
+        .cyclesPerTick = 168000000 / 1000,
+        .clkSrc = WHAL_SYSTICK_CLKSRC_SYSCLK,
+        .tickInt = WHAL_SYSTICK_TICKINT_ENABLED,
+    },
+};
+
+/* Ethernet MAC */
+#define ETH_TX_DESC_COUNT 4
+#define ETH_RX_DESC_COUNT 4
+#define ETH_TX_BUF_SIZE   1536
+#define ETH_RX_BUF_SIZE   1536
+
+static whal_Stm32h5Eth_TxDesc eth_tx_descs[ETH_TX_DESC_COUNT]
+    __attribute__((aligned(16)));
+static whal_Stm32h5Eth_RxDesc eth_rx_descs[ETH_RX_DESC_COUNT]
+    __attribute__((aligned(16)));
+static uint8_t eth_tx_bufs[ETH_TX_DESC_COUNT * ETH_TX_BUF_SIZE]
+    __attribute__((aligned(4)));
+static uint8_t eth_rx_bufs[ETH_RX_DESC_COUNT * ETH_RX_BUF_SIZE]
+    __attribute__((aligned(4)));
+
+whal_Eth g_whalEth = {
+    WHAL_STM32H563_ETH_DEVICE,
+
+    .macAddr = {0x00, 0x80, 0xE1, 0x00, 0x00, 0x01},
+    .cfg = &(whal_Stm32h5Eth_Cfg) {
+        .txDescs = eth_tx_descs,
+        .txBufs = eth_tx_bufs,
+        .txDescCount = ETH_TX_DESC_COUNT,
+        .txBufSize = ETH_TX_BUF_SIZE,
+        .rxDescs = eth_rx_descs,
+        .rxBufs = eth_rx_bufs,
+        .rxDescCount = ETH_RX_DESC_COUNT,
+        .rxBufSize = ETH_RX_BUF_SIZE,
+        .timeout = &g_whalTimeout,
+    },
+};
+
+/* Ethernet PHY (LAN8742A) */
+whal_EthPhy g_whalEthPhy = {
+    .eth = &g_whalEth,
+    .addr = BOARD_ETH_PHY_ADDR,
+    .driver = &whal_Lan8742a_Driver,
+
+    .cfg = &(whal_Lan8742a_Cfg) {
+        .timeout = &g_whalTimeout,
+    },
+};
+
+/* UART: USART2 on ST-Link VCP */
+whal_Uart g_whalUart = {
+    WHAL_STM32H563_USART2_DEVICE,
+
+    .cfg = &(whal_Stm32h5Uart_Cfg) {
+        .brr = WHAL_STM32H5_UART_BRR(168000000, 115200),
+        .timeout = &g_whalTimeout,
+    },
+};
+
+/* Flash: needed for latency configuration before clock increase */
+static whal_Flash flash = {
+    WHAL_STM32H563_FLASH_DEVICE,
+
+    .cfg = &(whal_Stm32h5Flash_Cfg) {
+        .startAddr = 0x08000000,
+        .size = 0x200000,
+        .timeout = &g_whalTimeout,
+    },
+};
+
+/* 5 wait states + WRHIGHFREQ=2 for 168 MHz */
+#define FLASH_LATENCY_168MHZ ((2 << 4) | 5)
+
+whal_Error board_init(void)
+{
+    whal_Error err;
+    size_t i;
+
+    /* Set flash latency before increasing clock speed */
+    err = whal_Stm32h5Flash_Ext_SetLatency(&flash, FLASH_LATENCY_168MHZ);
+    if (err)
+        return err;
+
+    err = whal_Clock_Init(&clock);
+    if (err)
+        return err;
+
+    for (i = 0; i < CLOCK_COUNT; i++) {
+        err = whal_Clock_Enable(&clock, &clocks[i]);
+        if (err)
+            return err;
+    }
+
+    /* Select RMII mode in SBS_PMCR before enabling ETH clocks */
+    *(volatile uint32_t *)0x44000500 =
+        (*(volatile uint32_t *)0x44000500 & ~(7UL << 21)) | (4UL << 21);
+
+    for (i = 0; i < ETH_CLOCK_COUNT; i++) {
+        err = whal_Clock_Enable(&clock, &eth_clocks[i]);
+        if (err)
+            return err;
+    }
+
+    err = whal_Gpio_Init(&gpio);
+    if (err)
+        return err;
+
+    err = whal_Uart_Init(&g_whalUart);
+    if (err)
+        return err;
+
+    err = whal_Eth_Init(&g_whalEth);
+    if (err)
+        return err;
+
+    err = whal_EthPhy_Init(&g_whalEthPhy);
+    if (err)
+        return err;
+
+    err = whal_Timer_Init(&timer);
+    if (err)
+        return err;
+
+    err = whal_Timer_Start(&timer);
+    if (err)
+        return err;
+
+    return WHAL_SUCCESS;
+}
+
+whal_Error board_deinit(void)
+{
+    whal_Error err;
+    size_t i;
+
+    err = whal_Timer_Stop(&timer);
+    if (err)
+        return err;
+
+    err = whal_Timer_Deinit(&timer);
+    if (err)
+        return err;
+
+    err = whal_EthPhy_Deinit(&g_whalEthPhy);
+    if (err)
+        return err;
+
+    err = whal_Eth_Deinit(&g_whalEth);
+    if (err)
+        return err;
+
+    err = whal_Uart_Deinit(&g_whalUart);
+    if (err)
+        return err;
+
+    err = whal_Gpio_Deinit(&gpio);
+    if (err)
+        return err;
+
+    for (i = 0; i < ETH_CLOCK_COUNT; i++) {
+        err = whal_Clock_Disable(&clock, &eth_clocks[i]);
+        if (err)
+            return err;
+    }
+
+    for (i = 0; i < CLOCK_COUNT; i++) {
+        err = whal_Clock_Disable(&clock, &clocks[i]);
+        if (err)
+            return err;
+    }
+
+    err = whal_Clock_Deinit(&clock);
+    if (err)
+        return err;
+
+    return WHAL_SUCCESS;
+}