From 356f0335ac5d541e0d140e842997fc2f5e25cba1 Mon Sep 17 00:00:00 2001 From: ga Date: Thu, 18 Jun 2026 09:55:12 +0100 Subject: [PATCH 1/2] Fix Makefile. --- examples/adc/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/examples/adc/Makefile b/examples/adc/Makefile index ed84f60..0f30955 100644 --- a/examples/adc/Makefile +++ b/examples/adc/Makefile @@ -3,7 +3,7 @@ SRC := flash_adc8.v flash_adc8_tb.v SRC_SPICE := flash_adc8.cir HDL_INSTANCE := flash_adc8_tb.dut -SPICEBIND_DIR := $(shell spicebind-vpi-path) +SPICEBIND_DIR := ../../spicebind OUT := flash_adc8_tb.vvp From f53a7f5861df776f3398e0bd3092619311db315b Mon Sep 17 00:00:00 2001 From: ga Date: Thu, 18 Jun 2026 10:00:28 +0100 Subject: [PATCH 2/2] Add an example with transistors. --- examples/adder_mos/README.md | 24 +++++++++++ examples/adder_mos/adder_mos.cir | 71 ++++++++++++++++++++++++++++++++ examples/adder_mos/clean | 1 + examples/adder_mos/plot.sp | 7 ++++ examples/adder_mos/run | 4 ++ examples/adder_mos/tb.v | 34 +++++++++++++++ 6 files changed, 141 insertions(+) create mode 100644 examples/adder_mos/README.md create mode 100644 examples/adder_mos/adder_mos.cir create mode 100755 examples/adder_mos/clean create mode 100644 examples/adder_mos/plot.sp create mode 100755 examples/adder_mos/run create mode 100644 examples/adder_mos/tb.v diff --git a/examples/adder_mos/README.md b/examples/adder_mos/README.md new file mode 100644 index 0000000..7d9a983 --- /dev/null +++ b/examples/adder_mos/README.md @@ -0,0 +1,24 @@ +## A four-bit CMOS adder and Verilog testbench, +derived from Ngspice's adder_mos.cir example circuit. + + +## To compile the testbench: +``` +iverilog -o tb.vvp tb.v +``` + +## Run the simulation - this takes several seconds: + +``` +./run +``` + +## Plot results: +``` +ngspice plot.sp +``` + +## Tidy up: +``` +./clean +``` \ No newline at end of file diff --git a/examples/adder_mos/adder_mos.cir b/examples/adder_mos/adder_mos.cir new file mode 100644 index 0000000..e1d024a --- /dev/null +++ b/examples/adder_mos/adder_mos.cir @@ -0,0 +1,71 @@ + ADDER - 4 BIT ALL-NAND-GATE BINARY ADDER +* Adapted from Ngspice: examples/digital/compare/adder_mos.cir + +* use BSIM3 model with default parameters +.model n1 nmos level=49 version=3.3.0 +.model p1 pmos level=49 version=3.3.0 + +*** SUBCIRCUIT DEFINITIONS +.SUBCKT NAND in1 in2 out VDD +* NODES: INPUT(2), OUTPUT, VCC +M1 out in2 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p +M2 net.1 in2 0 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p +M3 out in1 Vdd Vdd p1 W=7.5u L=0.35u pd=13.5u ad=22.5p ps=13.5u as=22.5p +M4 out in1 net.1 0 n1 W=3u L=0.35u pd=9u ad=9p ps=9u as=9p +.ENDS NAND + +.SUBCKT ONEBIT 1 2 3 4 5 6 +* NODES: INPUT(2), CARRY-IN, OUTPUT, CARRY-OUT, VCC +X1 1 2 7 6 NAND +X2 1 7 8 6 NAND +X3 2 7 9 6 NAND +X4 8 9 10 6 NAND +X5 3 10 11 6 NAND +X6 3 11 12 6 NAND +X7 10 11 13 6 NAND +X8 12 13 4 6 NAND +X9 11 7 5 6 NAND +.ENDS ONEBIT + +.SUBCKT TWOBIT 1 2 3 4 5 6 7 8 9 +* NODES: INPUT - BIT0(2) / BIT1(2), OUTPUT - BIT0 / BIT1, +* CARRY-IN, CARRY-OUT, VCC +X1 1 2 7 5 10 9 ONEBIT +X2 3 4 10 6 8 9 ONEBIT +.ENDS TWOBIT + +.SUBCKT FOURBIT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 +* NODES: INPUT - BIT0(2) / BIT1(2) / BIT2(2) / BIT3(2), +* OUTPUT - BIT0 / BIT1 / BIT2 / BIT3, CARRY-IN, CARRY-OUT, VCC +X1 1 2 3 4 9 10 13 16 15 TWOBIT +X2 5 6 7 8 11 12 16 14 15 TWOBIT +.ENDS FOURBIT + +*** POWER +VCC 99 0 DC 3.3V + +*** DEFINE NOMINAL CIRCUIT +X1 a0 b0 a1 b1 a2 b2 a3 b3 y[0] y[1] y[2] y[3] 0 13 99 FOURBIT + +*** ALL INPUTS +VA[0] a0 0 EXTERNAL +VB[0] b0 0 EXTERNAL +VA[1] a1 0 EXTERNAL +VB[1] b1 0 EXTERNAL +VA[2] a2 0 EXTERNAL +VB[2] b2 0 EXTERNAL +VA[3] a3 0 EXTERNAL +VB[3] b3 0 EXTERNAL + +* Dummy output nodes for plotting + +r0 y[0] y0 1 +r1 y[1] y1 1 +r2 y[2] y2 1 +r3 y[3] y3 1 + +.option noinit acct norefvalue +.save a0 b0 a1 b1 a2 b2 a3 b3 y0 y1 y2 y3 y[0] y[1] y[2] y[3] 13 +.TRAN 10n 10m + +.END diff --git a/examples/adder_mos/clean b/examples/adder_mos/clean new file mode 100755 index 0000000..7bef931 --- /dev/null +++ b/examples/adder_mos/clean @@ -0,0 +1 @@ +rm -rf *.raw *.vvp *~ diff --git a/examples/adder_mos/plot.sp b/examples/adder_mos/plot.sp new file mode 100644 index 0000000..96d82ad --- /dev/null +++ b/examples/adder_mos/plot.sp @@ -0,0 +1,7 @@ +*ng_script +* Script to plot tesults of Spicebind MOS adder simulation. + +load dump.raw +plot v(a0) v(b0)+4 v(a1)+8 v(b1)+12 v(a2)+16 v(b2)+20 v(a3)+24 v(b3)+28 +* plot the outputs, use offset to plot on top of each other +plot y0 v(y1)+4 v(y2)+8 v(y3)+12 v(13)+16 diff --git a/examples/adder_mos/run b/examples/adder_mos/run new file mode 100755 index 0000000..af8d7d5 --- /dev/null +++ b/examples/adder_mos/run @@ -0,0 +1,4 @@ +export SPICE_NETLIST=adder_mos.cir +export HDL_INSTANCE=adder_tb.dut +export VCC=3.3 +vvp -m ../../spicebind/spicebind_vpi.vpi tb.vvp diff --git a/examples/adder_mos/tb.v b/examples/adder_mos/tb.v new file mode 100644 index 0000000..0b30a64 --- /dev/null +++ b/examples/adder_mos/tb.v @@ -0,0 +1,34 @@ +/* Testbench for 4-bit adder made with spicebind. */ + +`timescale 1ns / 1ns + +module adder(a, b, y); + input wire [3:0]a; + input wire [3:0]b; + output wire [3:0]y; +endmodule + +module adder_tb; + reg [3:0]a; + reg [3:0] b; + wire [3:0] y; + integer ai, bi; + + adder dut(a, b, y); + + initial begin + for (ai = 0; ai < 16; ai = ai + 1) begin + a = ai; + for (bi = 0; bi < 16; bi = bi + 1) begin + b = bi; + #10; + if (y != a + b) begin + $display("Fail: %d + %d = %d!", a, b, y); + $finish; + end; + end; + end; + $display("Adder OK"); + $finish; + end; // initial begin +endmodule