Repository navigation
Expand file tree
/
Copy pathinnovus - code.v
More file actions
431 lines (373 loc) · 14.5 KB
/
Copy pathinnovus - code.v
File metadata and controls
431 lines (373 loc) · 14.5 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
`timescale 1ns / 1ps
module innovus (start,clk1,count,I,read_i,read_d,A,B,L,S);
input start,clk1;
input [31:0] I,L;
output [31:0] A,B;
output read_i,read_d;
output [15:0] count,S;
wire [2:0] operation;
wire [2:0] rs1, rs2, rd;
wire [6:0] opcode;
wire [31:0] Z, acc, F;
wire ALUon;
wire mux_signal;
wire pc_signal;
wire [0:7] FR;
decoder DEC(.din(I),
.dout0(rs1),
.dout1(rs2),
.dout2(rd),
.dout3(opcode),
.dout4(S));
multiplexer MUX(.dout(F),
.din0(Z),
.din1(L),
.select(mux_signal),
.clk(clk1));
program_counter PC(.out(count),
.in(S),
.pc_signal(pc_signal),
.clk(clk1),
.start(start));
register_bank RB(.destination_reg1_d(F),
.destination_reg2_d(acc),
.destination_reg3_d(S),
.source_reg1_d(A),
.source_reg2_d(B),
.destination_reg_a(rd),
.source_reg1_a(rs1),
.source_reg2_a(rs2),
.clk(clk1),
.start(start),
.operation(operation));
arithmatic_logic_unit ALU(.dout0(Z),
.FR(FR),
.dout5(acc),
.din0(A),
.din1(B),
.select(opcode),
.clk(clk1),
.enable(ALUon));
control_signals CS (.read_i(read_i),
.ALUon(ALUon),
.read_d(read_d),
.mux_signal(mux_signal),
.pc_signal(pc_signal),
.I(I),
.FR(FR),
.clk1(clk1),
.start(start),
.operation(operation));
endmodule
////////////////////////////////////////////////////////////////////////////
module decoder(din,
dout0,
dout1,
dout2,
dout3,
dout4);
input [31:0] din;
output reg[2:0] dout0, dout1, dout2;
output reg[6:0] dout3;
output reg[15:0] dout4;
always@(din)
begin
dout0 <= din[24:22];
dout1 <= din[21:19];
dout2 <= din[18:16];
dout3 <= din[31:25];
dout4 <= din[15:0];
end
endmodule
//////////////////////////////////////////////////////////////////////////////
module program_counter(out,
in,
pc_signal,
clk,
start);
input[15:0] in;
output reg[15:0] out;
input pc_signal, clk, start;
reg [2:0] TEMP;
always@(posedge clk)
begin
if(start == 1'b1)
begin
out <= 16'h0000;
TEMP <= 3'b001;
end
else
begin
if (TEMP == 3'b101)
begin
if (pc_signal == 1'b0) begin out <= in; TEMP <= 3'b001; end
else if (pc_signal == 1'b1) begin out <= out + 1; TEMP <= 3'b001; end
else begin out <= out; TEMP <= 3'b001; end
end
else TEMP <= TEMP + 1;
end
end
endmodule
//////////////////////////////////////////////////////////////////////////////////
module arithmatic_logic_unit (dout0,
FR,
dout5,
din0,
din1,
select,
clk,
enable);
input [31:0] din0, din1;
output reg[31:0] dout0, dout5;
output reg [0:7] FR;
input [6:0] select;
input clk, enable;
always @(posedge clk)
begin
if(enable == 1'b1)
begin
if (select == 7'b0000001) begin dout0 <= din0 + din1; FR <= 8'b01000000; end
else if(select == 7'b0000010) begin dout0 <= din0 - din1; FR <= 8'b01000000; end
else if(select == 7'b0000011) begin dout0 <= din0 & din1; FR <= 8'b01000000; end
else if(select == 7'b0000100) begin dout0 <= din0 | din1; FR <= 8'b01000000; end
else if(select == 7'b0000101) begin
if( din0 < din1 ) begin FR <= 8'b00010000; end
else begin FR <= 8'b00000001; end
end
else if(select == 7'b0000110) begin if( din0 > din1 ) begin FR <= 8'b00000001; end
else begin FR <= 8'b00010000; end
end
else if(select == 7'b0000111) begin FR <= 8'b01000000; end
else if(select == 7'b0001000) begin FR <= 8'b00000000; end
else if(select == 7'b0001001) begin dout0 <= dout0; dout5 <= dout5; FR <= FR; end
else if(select == 7'b0001010) begin dout0 <= (din0 >> 4)|(din0 << 32-4); FR <= 8'b01000000; end
else if(select == 7'b0001011) begin dout0 <= (din0 << 4)|(din0 >> 32-4); FR <= 8'b01000000; end
else if(select == 7'b0001100) begin
if(din0 == 0) begin FR <= 8'b00100000; end
else begin FR <= 8'b00000000; end
end
else if(select == 7'b0001101) begin
if(din0 != 0) begin FR <= 8'b00100000; end
else begin FR <= 8'b00000000; end
end
else if(select == 7'b0001110) begin
if(din0 == din1) begin FR <= 8'b00100000; end
else begin FR <= 8'b00000000; end
end
else if(select == 7'b0001111) begin
if(din0 != din1) begin FR <= 8'b00100000; end
else begin FR <= 8'b00000000; end
end
else if(select == 7'b0010000) begin FR <= 8'b00100000; end
else if(select == 7'b0010001) begin {dout5[31:0],dout0[31:0]} <= din0*din1; FR <= 8'b00001000; end
else if(select == 7'b0010010) begin dout0[31:0] <= din0/din1; FR <= 8'b01000000; end
else if(select == 7'b0010011) begin dout0[31:0] <= din0%din1; FR <= 8'b01000000; end
else if(select == 7'b0010100) begin dout0 <= ~din0; FR <= 8'b01000000; end
else if(select == 7'b0010101) begin dout0 <= din0; FR <= 8'b01000000; end
else if(select == 7'b0010110) begin
if(FR[7] == 1'b1) begin FR <= 8'b00100001; end
else begin FR <= 8'b00010000; end
end
else if(select == 7'b0010111) begin
if(FR[3] == 1'b1) begin FR <= 8'b00110000; end
else begin FR <= 8'b00000001; end
end
else if(select == 7'b0011000) begin FR <= 8'b00000100; end
else if(select == 7'b0011001) begin FR <= 8'b00000010; end
else begin dout0 <= dout0; FR <= FR; end
end
end
endmodule
///////////////////////////////////////////////////////////////////////////
module multiplexer(dout,
din0,
din1,
select,
clk);
input [31:0] din0, din1;
output reg [31:0] dout;
input select, clk;
always@ (posedge clk)
begin
if (select == 1'b0) dout <= din0;
else if (select == 1'b1) dout <= din1;
else dout <= dout;
end
endmodule
/////////////////////////////////////////////////////////////////////////////
module register_bank (destination_reg1_d,
destination_reg2_d,
destination_reg3_d,
source_reg1_d,
source_reg2_d,
destination_reg_a,
source_reg1_a,
source_reg2_a,
clk,
start,
operation);
output reg [31:0] source_reg1_d, source_reg2_d;
input [31:0] destination_reg1_d, destination_reg2_d;
input [15:0] destination_reg3_d;
input [2:0] destination_reg_a, source_reg1_a, source_reg2_a;
input [2:0] operation;
input clk, start;
reg [31:0] regbank[7:0];
reg [31:0] TEMP;
integer i;
always @ (posedge clk)
begin
if(start == 1'b1)
for(i=0; i<8; i=i+1) regbank [i] <= 32'h00000000;
else
begin
if (operation == 3'b000)
begin
regbank[destination_reg_a] <= destination_reg1_d;
end
else if (operation == 3'b001)
begin
regbank[destination_reg_a] <= destination_reg1_d;
regbank[destination_reg_a + 1] <= destination_reg2_d;
end
else if (operation == 3'b010)
begin
TEMP = regbank[destination_reg_a];
TEMP = {destination_reg3_d , TEMP[15:0]};
regbank[destination_reg_a] = TEMP;
TEMP = 32'h00000000;
end
else if (operation == 3'b011)
begin
TEMP = regbank[destination_reg_a];
TEMP = {TEMP[31:16] , destination_reg3_d};
regbank[destination_reg_a] = TEMP;
TEMP = 32'h00000000;
end
else if (operation == 3'b100)
begin
source_reg1_d <= source_reg1_d;
source_reg2_d <= source_reg2_d;
end
else if (operation == 3'b101)
begin
source_reg1_d <= regbank[source_reg1_a];
source_reg2_d <= regbank[source_reg2_a];
end
else begin end
end
end
endmodule
///////////////////////////////////////////////////////////////////////////////
module control_signals(read_i,
ALUon,
read_d,
mux_signal,
pc_signal,
I,
FR,
clk1,
start,
operation);
output reg read_i,ALUon,read_d,mux_signal,pc_signal;
output reg [2:0] operation;
input [31:0] I;
input clk1,start;
input [0:7] FR;
reg [2:0] state;
always @(posedge clk1)
begin
if(start == 1'b1) state <= 3'b001;
else
begin
if(state == 3'b000)
begin
if(start == 1'b1) state <= 3'b001;
else if(start == 1'b0) state <= 3'b000;
else state <= 3'b000;
end
else if(state == 3'b001) state <= 3'b010;
else if(state == 3'b010) state <= 3'b011;
else if(state == 3'b011) state <= 3'b100;
else if(state == 3'b100) state <= 3'b101;
else if(state == 3'b101)
begin
if ( I == 32'h12000000 ) state <= 3'b000;
else state <= 3'b001;
end
else state <= 3'b000;
end
end
always @(state)
begin
if(state == 3'b000)
begin
read_i <= 0;
ALUon <= 0;
read_d <= read_d;
mux_signal <= mux_signal;
operation = 3'b100;
pc_signal <= pc_signal;
end
else if(state == 3'b001)
begin
read_i <= 1;
ALUon <= 0;
read_d <= read_d;
mux_signal <= mux_signal;
operation = 3'b100;
pc_signal <= pc_signal;
end
else if(state == 3'b010)
begin
read_i <= 0;
ALUon <= 0;
read_d <= read_d;
mux_signal <= mux_signal;
operation = 3'b101;
pc_signal <= pc_signal;
end
else if(state == 3'b011)
begin
read_i <= 0;
ALUon <= 1;
if(I[31:25] == 7'b0000111) read_d <= 1'b1;
else if(I[31:25] == 7'b0001000) read_d <= 1'b0;
mux_signal <= mux_signal;
operation = 3'b100;
pc_signal <= pc_signal;
end
else if(state == 3'b100)
begin
read_i <= 0;
ALUon <= 0;
read_d <= read_d;
if(I[31:25] == 7'b0000111) mux_signal <= 1'b1;
else mux_signal <= 1'b0;
operation = 3'b100;
pc_signal <= pc_signal;
end
else if(state == 3'b101)
begin
read_i <= 0;
ALUon <= 0;
read_d <= read_d;
mux_signal <= mux_signal;
if(FR[2] == 0) begin pc_signal <= 1'b1; end
else if(FR[2] == 1) begin pc_signal <= 1'b0; end
else begin pc_signal <= pc_signal; end
if(FR[1] == 1) operation = 3'b000;
else if(FR[4] == 1) operation = 3'b001;
else if(FR[5] == 1) operation = 3'b010;
else if(FR[6] == 1) operation = 3'b011;
end
else begin
read_i <= 0;
ALUon <= 0;
read_d <= read_d;
mux_signal <= mux_signal;
operation = 3'b100;
pc_signal <= pc_signal;
end
end
endmodule