diff --git a/external/atomic_queue/include/atomic_queue/defs.h b/external/atomic_queue/include/atomic_queue/defs.h
index a279dcf8d..24fb5dfc2 100644
--- a/external/atomic_queue/include/atomic_queue/defs.h
+++ b/external/atomic_queue/include/atomic_queue/defs.h
@@ -31,6 +31,12 @@ static inline void spin_loop_pause() noexcept {
      defined(__ARM_ARCH_8A__) || \
      defined(__aarch64__))
     asm volatile ("yield" ::: "memory");
+#elif defined(__riscv)
+#if defined(__riscv_zihintpause)
+    asm volatile ("pause" ::: "memory");
+#else
+    /* Encoding of the pause instruction, will be treated as nop if not supported by hardware */
+    asm volatile (".4byte 0x100000F");
 #else
     asm volatile ("nop" ::: "memory");
 #endif
diff --git a/src/external/cpuid/platform/src/platform/config.hpp b/src/external/cpuid/platform/src/platform/config.hpp
index b50390edc..a196ce53f 100644
--- a/src/external/cpuid/platform/src/platform/config.hpp
+++ b/src/external/cpuid/platform/src/platform/config.hpp
@@ -55,6 +55,10 @@
 #define PLATFORM_MIPS 1
 #define PLATFORM_CLANG_MIPS 1
 #define PLATFORM_GCC_COMPATIBLE_MIPS 1
+#elif defined(__riscv)
+#define PLATFORM_RISCV 1
+#define PLATFORM_CLANG_RISCV 1
+#define PLATFORM_GCC_COMPATIBLE_RISCV 1
 #elif defined(__asmjs__)
 #define PLATFORM_ASMJS 1
 #define PLATFORM_CLANG_ASMJS 1
@@ -75,6 +79,10 @@
 #define PLATFORM_MIPS 1
 #define PLATFORM_GCC_MIPS 1
 #define PLATFORM_GCC_COMPATIBLE_MIPS 1
+#elif defined(__riscv)
+#define PLATFORM_RISCV 1
+#define PLATFORM_GCC_RISCV 1
+#define PLATFORM_GCC_COMPATIBLE_RISCV 1
 #endif
 #elif defined(_MSC_VER)
 #define PLATFORM_MSVC 1