A lot of chips now support serial spi interfaces generally used for external memory like quad and octospi. There are also alternate protocols like Hyperbus that are defined on some supported peripherals, although it is not clear if that makes sense to support in a generic way here. The functionality doesn't fit strictly to the standard SPI traits, each transaction requiring more detail generally about the nature of each transaction. It may be helpful to define a standard interface for these types of peripherals. Opening a discussion about how best to support those types of buses.
A lot of chips now support serial spi interfaces generally used for external memory like quad and octospi. There are also alternate protocols like Hyperbus that are defined on some supported peripherals, although it is not clear if that makes sense to support in a generic way here. The functionality doesn't fit strictly to the standard SPI traits, each transaction requiring more detail generally about the nature of each transaction. It may be helpful to define a standard interface for these types of peripherals. Opening a discussion about how best to support those types of buses.