diff --git a/fastino_phy.py b/fastino_phy.py
index 02836b7..aa3167b 100644
--- a/fastino_phy.py
+++ b/fastino_phy.py
@@ -206,26 +206,26 @@ def __init__(self, platform):
                 ResetSignal("spi") | have_align_err | have_crc_err,  # RED
             )),
         ]
-        self.specials += [
-            Instance(
-                "SB_IO",
-                p_PIN_TYPE=C(0b010000, 6),  # output registered DDR
-                p_IO_STANDARD="SB_LVCMOS",
-                i_OUTPUT_CLK=ClockSignal("link"),
-                #i_CLOCK_ENABLE=1,
-                o_PACKAGE_PIN=platform.request("test_point", 0),
-                i_D_OUT_0=1,
-                i_D_OUT_1=0),
-            Instance(
-                "SB_IO",
-                p_PIN_TYPE=C(0b010000, 6),  # output registered DDR
-                p_IO_STANDARD="SB_LVCMOS",
-                i_OUTPUT_CLK=ClockSignal("word"),
-                #i_CLOCK_ENABLE=1,
-                o_PACKAGE_PIN=platform.request("test_point", 1),
-                i_D_OUT_0=1,
-                i_D_OUT_1=0),
-        ]
+        # self.specials += [
+        #     Instance(
+        #         "SB_IO",
+        #         p_PIN_TYPE=C(0b010000, 6),  # output registered DDR
+        #         p_IO_STANDARD="SB_LVCMOS",
+        #         i_OUTPUT_CLK=ClockSignal("link"),
+        #         #i_CLOCK_ENABLE=1,
+        #         o_PACKAGE_PIN=platform.request("test_point", 0),
+        #         i_D_OUT_0=1,
+        #         i_D_OUT_1=0),
+        #     Instance(
+        #         "SB_IO",
+        #         p_PIN_TYPE=C(0b010000, 6),  # output registered DDR
+        #         p_IO_STANDARD="SB_LVCMOS",
+        #         i_OUTPUT_CLK=ClockSignal("word"),
+        #         #i_CLOCK_ENABLE=1,
+        #         o_PACKAGE_PIN=platform.request("test_point", 1),
+        #         i_D_OUT_0=1,
+        #         i_D_OUT_1=0),
+        # ]
 
 
 if __name__ == "__main__":