From 9713d4dca1ec11a009b0dd3df80abd92e0449bf0 Mon Sep 17 00:00:00 2001 From: pointerliu Date: Wed, 6 May 2026 16:37:16 +0800 Subject: [PATCH] csr_regfile: Fix SBE/UBE when S/U-mode disabled According to RISC-V privileged spec, SBE must be read-only 0 when S-mode is not supported, and UBE must be read-only 0 when U-mode is not supported. Previously MBE was mirrored to SBE and UBE unconditionally, which could set them to 1 even when the corresponding privilege mode was absent. Now the mirroring is conditional on CVA6Cfg.RVS and CVA6Cfg.RVU respectively, hardwiring to 0 when the mode is not supported. --- core/csr_regfile.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/core/csr_regfile.sv b/core/csr_regfile.sv index 6d268b8ca4..5d1b233d10 100644 --- a/core/csr_regfile.sv +++ b/core/csr_regfile.sv @@ -1559,8 +1559,8 @@ module csr_regfile mstatus_d.wpri2 = 1'b0; mstatus_d.wpri0 = 1'b0; // Mirror MBE - mstatus_d.sbe = mstatus_d.mbe; - mstatus_d.ube = mstatus_d.mbe; + mstatus_d.sbe = CVA6Cfg.RVS ? mstatus_d.mbe : 1'b0; + mstatus_d.ube = CVA6Cfg.RVU ? mstatus_d.mbe : 1'b0; // this register has side-effects on other registers, flush the pipeline flush_o = 1'b1; end @@ -1568,8 +1568,8 @@ module csr_regfile if (CVA6Cfg.XLEN == 32) begin mstatus_d.mbe = ((csr_wdata & riscv::MSTATUSH_MBE) != 0); // Mirror MBE - mstatus_d.sbe = mstatus_d.mbe; - mstatus_d.ube = mstatus_d.mbe; + mstatus_d.sbe = CVA6Cfg.RVS ? mstatus_d.mbe : 1'b0; + mstatus_d.ube = CVA6Cfg.RVU ? mstatus_d.mbe : 1'b0; // this register has side-effects on other registers, flush the pipeline flush_o = 1'b1; end else begin