+The module receives a structured input named **`rvfi_to_iti`**, which encapsulates all the necessary signals to:
+
+* determine the **instruction type (`itype`)** using fields such as `opcode`, `branch_valid`, etc.,
+* supply relevant metadata to the encoder like `cycle`, `privilege level`, `pc`, etc.
+
+Changes were also made to the `cva6_rvfi` module to collect the signals required by the ITI and to properly resynchronize them, since they may originate from different stages of the processor pipeline. This justifies the use of a structured interface to ensure reliable and consistent data transfer to the ITI.
+
+---
+
+### Multiple-Retirement Mode
+
+In **multiple-retirement mode**, the ITI groups instructions into **blocks**, based on the occurrence of *special* instructions , typically those altering the control flow (e.g., jumps, exceptions, interrupts).
+
+The ITI outputs the following signals to the encoder in this mode:
+
+* `iret`: number of half-words for the retired instructions in the current block,
+* `iaddr`: address of the first instruction in the block,
+* `ilastsize`: size of the last instruction in the block.
+
+To support this, the ITI adopts a **systolic-like architecture** made up of `block_retirement` submodules. There are `Nr_commit_ports` such submodules, each able to:
+
+* detect special instructions independently,
+* initiate a new block if necessary,
+* propagate control and data signals (like `special`, `iaddr`, and incremented `iret`) along a chain.
+
+This design enables the generation of **multiple blocks in a single cycle** when several special instructions retire simultaneously.
+
+
+
+
+
+
+
+
+---
+### Single-Retirement Mode
+
+In **single-retirement mode**, the ITI module forwards the trace information **instruction by instruction**, without grouping them into blocks.
+
+In this configuration:
+
+* There is no need to track special instructions or segment blocks.
+* The encoder receives a simple feed of retired instructions, making this mode well-suited for simpler architectures.
+
+
+
+
+
+
+
+
+---
+### Full System Overview
+
+The overall role of the ITI module in the trace infrastructure is summarized in the following diagram:
+
+
+
+
+
+
+---
+### Continuous Integration for ITI
+
+The CI (Continuous Integration) test for the ITI is contained in Instr_tracing_test.sh and consist of running a simulation on ariane_testharness with the previous test iti_test.sh and extracting the iti.trace. Then it run the regressionFlow from the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec) and compare both files.
+We cleaned both file to compare what is comparable ,we exclude the start and the end because it's not matching based spike version
+
+
+## 2. Encoder + Encapsulator
+
+### Collaboration and Reference Design
+
+For this module, we collaborate with the University of Bologna by integrating their version of the encoder, available
+[here](https://github.com/pulp-platform/rv_tracer)
+
+Their repository is well-documented and serves as a solid foundation. The encoder design is aligned with the **E-Trace specification** and leverages an ITI running in **multiple-retirement mode** to emit **trace packets**. These packets are structured according to the **instruction delta trace algorithm** described in the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec) (Figure 1), which provides a model for encoding deltas (non-linearities) in the control flow.
+
+Each data trace outputed by the ITI, whether block-based or instruction-based, is interpreted to identify these deltas and transmit them in the form of trace packets. These packets vary in format and size depending on the instruction type and control flow transitions.
+
+---
+
+### Custom Implementation and Simplification
+
+While their encoder provides a baseline, it remains under active development. In its current state, its behavior (in terms of number of packets emitted, their contents, or supported options) differs from the Reference Flow.
+
+As a result, we opted to build a simplified version derived from the original architecture. This internal encoder:
+
+* Expects **instruction-by-instruction traces** as input,
+* Supports only **Nr\_commit\_ports = 1** (single commit port),
+* Implements only a **basic subset** of the E-Trace functionality.
+
+This choice facilitates initial validation and integration, though we remain open to switching back to a mature multiple-retirement encoder once available.
+
+Below is a high-level architectural diagram of the current encoder setup (here `N=1`):
+
+
+
+
+
+
+---
+
+### Submodules Description
+
+The encoder is composed of several key submodules:
+
+### Submodules Description
+
+The encoder is composed of several key submodules:
+
+* **Priority**:
+ This submodule constitutes the core of the *Instruction Delta Trace Algorithm*. It is responsible for analyzing control flow transitions across instructions and determining the format and/or subformat of trace packets to be emitted.
+
+
+
+
+
+
+
+ The logic is driven by three categories of input signals that represent the state of the instruction stream at different points in time:
+ - **lc**: *Last Cycle* - information from the previous retired instruction,
+ - **tc**: *This Cycle* - information from the currently retiring instruction,
+ - **nc**: *Next Cycle* - information from the next instruction.
+
+ > Some signals are intentionally absent for the sake of understanding
+
+ Using these signals, the `Priority` module identifies the relevant **deltas** (e.g., taken branches, jumps, exceptions) and selects the appropriate **packet format and/or subformat**, which will subsequently guide the `Packet_Emitter`.
+
+
+
+ > For more details, refer to [Chapter 7 (Instruction Trace Encoder Output Packet)](https://github.com/riscv-non-isa/riscv-trace-spec) (2025), or consult the corresponding encoder section in the [University of Bologna's implementation](https://github.com/pulp-platform/rv_tracer).
+
+
+* **Packet_Emitter**:
+ This submodule is responsible for **constructing and filling the trace packet** to be emitted. It plays a central role in materializing the output of the delta trace algorithm into a well-structured packet format compliant with the E-Trace specification.
+
+
+
+
+
+
+
+ Similar to the `Priority` module, it receives multiple input signals that span across different time domains (*lc*,*tc*,*nc*).
+
+ However, the most important **inputs** for this submodule is the **packet format and/or subformat**, which is deteminated by the `Priority` module. This format/subformat dictates the structure and contents of the packet's payload. Also **ppccd** means privilege change, precise context change or context change with discontinuity.
+
+ Based on this, the `Packet_Emitter` output:
+ - The **payload** which contains all the fields expected for this packet,
+ - The **packet length** (in bytes), depending on the format/subformat and data,
+ - A **branch_map_flush** signal that is used to flush the `branch_map` field. This ensures the `branch_map` is ready to accurately track future branches for the next packet.
+
+ > For a complete description of each packet type and its associated payload content, refer to [Chapter 7 (Instruction Trace Encoder Output Packet)](https://github.com/riscv-non-isa/riscv-trace-spec) of the E-Trace specification (2025).
+
+* **Filter**:
+ The `Filter` submodule is responsible for **selectively enabling or disabling instruction tracing** (with the qualified signal) based on configurable events defined through **Control Registers**. By filtering out irrelevant or redundant instructions, it can significantly improves trace analysis efficiency and bandwidth usage.
+
+
+
+
+
+
+
+ The filtering mechanism supports a variety of events, including:
+
+ - **Range Address**: Enables tracing **only when the instruction address (`iaddr`) falls within a specified address window**, defined by a `lower_addr` and a `higher_addr` boundary.
+ - **Stop Event**: Immediately halts instruction tracing when triggered.
+ - **Selected Privilege Level**: Enables or disables tracing depending on the **current privilege level** (e.g., user, supervisor, machine mode).
+ - **Other Events**: Filtering can also be triggered by **exceptions**, **interrupts**, or other **context-specific conditions**.
+
+
+* **Branch\_Map**:
+ The `Branch_Map` submodule acts as a **history buffer** for recently executed branch instructions. It plays a crucial role in the generation of compressed trace packets by allowing the encoder to **reconstruct control-flow paths** through a compact representation.
+
+
+
+
+
+
+ This module maintains two key outputs:
+
+ - **`branch_map`**: a **bitfield** representing the history of up to 31 conditional branches. For each branch, a **bit is added to the right**:
+ - `0` if the branch was **taken**,
+ - `1` if the branch was **not taken**.
+
+ - **`branches`**: an **integer count** of how many branches are currently stored in the map (max: **31**). This counter helps determine the valid width of the `branch_map` field and guides packet formatting/decoding.
+
+ The branch_map is updated as instructions retire. Once the maximum depth is reached or a flush is triggered (e.g., via `branch_map_flush` from the `Packet_Emitter`), the map is cleared to allow tracking of the next sequence.
+
+ Here is an illustrative example, taken from [E-Trace Specification – Chapter 12, Example 4](https://github.com/riscv-non-isa/riscv-trace-spec).
+
+
+
+
+
+
+
+
+---
+
+### Encapsulation Module
+
+This module was developed by the **University of Bologna**, and we reused the `encapsulator.sv` module **as-is**, without any modifications. We chose **not to integrate the other submodules** provided in the original repository, as they are designed for the **ATB (Advanced Trace Bus)** protocol. In our case, we rely on a different trace output interface, named **DPTI (Digilent Parallel Transfer Interface)**, making the use of those ATB-specific modules unnecessary. [Here](https://github.com/pulp-platform/rv_encapsulator) is the repository of the encapsulator from the **University of Bologna**.
+
+The **encapsulator** is placed directly after the encoder and is responsible for wrapping each trace packet into a **standardized encapsulation format** as defined by the [encapsulation specification](https://github.com/riscv-non-isa/e-trace-encap).
+
+This format ensures **interoperability**, provides **framing rules**, and facilitates **packet-level synchronization** in the *transmission channel* interface. Each encapsulated packet in this implementation is **fixed at 320 bits (40 bytes)** and includes this field groups:
+
+- **Header (8 bits)**:
+ Includes a `length` field (5 bits) specifying the payload size in bytes, a `flow` field (2 bits) which is currently set to `00` (no multi-sink used yet), and an `extend` bit (1 bit) which is set to `1`, indicating the presence of a timestamp (T ? in the figure bellow).
+
+- **Timestamp (`T * 8` bits)**:
+ The timestamp is included in our packets and is **fixed at 8 bytes (64 bits)**. Its presence is governed by the `extend` bit in the header.
+
+- **Payload (1–248 bits)**:
+ Contains the actual trace packet, emmited by the encoder with `packet_payload_o`.
+
+An illustration of the encapsulation structure is shown below:
+
+
+
+
+
+
+
+
+Once encapsulated, the packets are written into a **FIFO buffer**, where they await transmission through the trace communication channel.
+
+This design enables modular evolution: improvements or full spec-compliance in the encoder can be adopted later without altering the overall encapsulation and transmission stages.
+
+
+> While the [encapsulation specification](https://github.com/riscv-non-isa/e-trace-encap) also defines support for **source IDs** , **null packets** (e.g., `null.idle`, `null.alignment`), and **synchronization sequences**, these features are **not yet implemented** in the current prototype.
+
+### Continuous Integration for Encoder + Encapsulator
+
+The CI (Continuous Integration) test for the Encoder and Encapsulator is also contained in Instr_tracing_test.sh and consists in running a simulation on ariane_testharness with the previous test iti_test.sh and extracting the `encoded.trace`, it will convert them in decaspulated csv format with the Decapsuler. Then it runs the regressionFlow from the [E-Trace specification](https://github.com/riscv-non-isa/riscv-trace-spec) and compare both files.
+We cleaned both file to compare what is comparable, again we exclude the start and the end because it's not matching based spike version.
+
+
+---
+
+
+## 3. Transmission Channel (TC) via DPTI
+
+
+
+
Figure: Digilent Genesys2 development board
+
+
+Picture from [Digilent Reference Manual](digilent.com/reference/programmable-logic/genesys-2/reference-manual)
+
+Since most onboard peripherals (UART, SPI, etc.) are already used by the `ariane_xilinx` platform, we use the **FTDI FT2232H**'s DPTI interface exposed on the **USB-JTAG bridge (J17)**:
+
+
+
+
Figure: USB-JTAG bridge
+
+
+Picture from [Digilent Reference Manual](digilent.com/reference/programmable-logic/genesys-2/reference-manual)
+
+- **DPTI/DSPI header** on J17 provides:
+ - A **Digilent Parallel Transfer Interface (DPTI)** channel
+ - A generic SPI channel (not used here due to limited bandwidth)
+
+We selected **DPTI** because it is a **mature, out‑of‑the‑box solution** full driver support from Digilent Adept ([Adept Drivers & Utilities](https://digilent.com/reference/software/adept/)).
+
+---
+
+### FT2232H Ports in Genesys 2
+
+The FT2232H chip offers two independent channels but in the Top platform `ariane_xilinx` both of them are used :
+
+| Port | Default Use in `ariane_xilinx`|
+|-------|-------------------------------|
+| Port A| Bitstream injection |
+| Port B| Debug Module interface |
+
+Because both channels are occupied, we have two deployment options:
+
+1. **Re-purpose Port B**
+ - **Disconnect the Debug Module** in `ariane_xilinx.sv`.
+ - Update `genesys.xdc` to add DPTI pin constraints (e.g., check the [default constraint file](https://github.com/Digilent/digilent-xdc/blob/master/Genesys-2-Master.xdc) section DPTI).
+ - Inject your program via the on‑chip **bootrom**, modify the Makefile in `corev_apu/fpga/src/bootrom` accordingly.
+
+2. **Add an FT2232H MiniModule**
+ - Use a standard [FT2232H Mini Module](https://ftdichip.com/products/ft2232h-mini-module/) connected to two PMOD headers.
+ - This gives you two **additional** FT2232H channels without touching the existing Port A/B setup.
+
+
+
+
Figure: FT2232H MiniModule wired to Genesys2 PMODs
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+> For more details on the wiring, check these resources:
+> - [FT2232H Datasheet](https://ftdichip.com/wp-content/uploads/2024/09/DS_FT2232H.pdf), Table 3.1
+> - [FT2232H Mini Module Datasheet](https://ftdichip.com/wp-content/uploads/2020/07/DS_FT2232H_Mini_Module.pdf), Table 3.1 and Table 3.2 and USB Bus-powered section.
+
+---
+
+### Platform Modifications
+
+
+
+
+
+
+
+
+1. **DPTI Controller**
+ - Add `dpti_ctrl.vhd` to handle **frame send/receive** over DPTI. This module is provided by Digilent and can be found in the [**Digilent Adept SDK**](https://lp.digilent.com/complete-adept-runtime-download), under `samples/dpti/DptiDemo/logic/dpti_ctrl.vhd`.
+ - Protocol: **8-bit parallel**, synchronous/asynchronous, running at **60 MHz**, allowing for up to **480 Mbps** throughput.
+ - The controller requires a clock. It is instantiated in the platform using `xlnx_dpti_clk` located in `cva6/corev_apu/fpga/xilinx/xlnx_dpti_clk`. Alternatively, it can be added to the Vivado project using a Clock Wizard. An example configuration is available in `samples/dpti/DptiDemo/logic/clk_wiz_0.v`.
+
+2. **Packet Slicer**
+ - Our trace packets are **320 bits** (40 bytes).
+ - Insert `slicer_DPTI.sv` to segment each packet into **40 eight‑bit frames** for DPTI transport.
+
+3. **PMOD Pin Mapping & Constraints**
+ - PMOD pins used must support external clock (C‑capable). Follow [UG472](https://docs.amd.com/v/u/en-US/ug472_7Series_Clocking) (Vivado) guidelines.
+ - Example excerpt from `genesys2.xdc`:
+ ```xdc
+ ## PMOD Header JA
+ #set_property -dict { PACKAGE_PIN U27 IOSTANDARD LVCMOS33 } [get_ports prog_clko]; #IO_L13P_T2_MRCC_14 Sch=ja_p[1]
+ #set_property -dict { PACKAGE_PIN U28 IOSTANDARD LVCMOS33 } [get_ports prog_oen]; #IO_L13N_T2_MRCC_14 Sch=ja_n[1]
+ #set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 } [get_ports prog_rdn]; #IO_L12P_T1_MRCC_14 Sch=ja_p[2]
+ #set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 } [get_ports prog_rxen]; #IO_L12N_T1_MRCC_14 Sch=ja_n[2]
+ #set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports prog_siwun]; #IO_L5P_T0_D06_14 Sch=ja_p[3]
+ #set_property -dict { PACKAGE_PIN T23 IOSTANDARD LVCMOS33 } [get_ports prog_spien]; #IO_L5N_T0_D07_14 Sch=ja_n[3] // Not needed here
+ #set_property -dict { PACKAGE_PIN T20 IOSTANDARD LVCMOS33 } [get_ports prog_txen]; #IO_L4P_T0_D04_14 Sch=ja_p[4]
+ #set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports prog_wrn]; #IO_L4N_T0_D05_14 Sch=ja_n[4]
+
+ ## PMOD Header JB
+ #set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { prog_d[0] }]; #IO_L17P_T2_A14_D30_14 Sch=jb_p[1]
+ #set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { prog_d[1] }]; #IO_L17N_T2_A13_D29_14 Sch=jb_n[1]
+ #set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { prog_d[2] }]; #IO_L18P_T2_A12_D28_14 Sch=jb_p[2]
+ #set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { prog_d[3] }]; #IO_L18N_T2_A11_D27_14 Sch=jb_n[2]
+ #set_property -dict { PACKAGE_PIN T25 IOSTANDARD LVCMOS33 } [get_ports { prog_d[4] }]; #IO_L14P_T2_SRCC_14 Sch=jb_p[3]
+ #set_property -dict { PACKAGE_PIN U25 IOSTANDARD LVCMOS33 } [get_ports { prog_d[5] }]; #IO_L14N_T2_SRCC_14 Sch=jb_n[3]
+ #set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { prog_d[6] }]; #IO_L21P_T3_DQS_14 Sch=jb_p[4]
+ #set_property -dict { PACKAGE_PIN U23 IOSTANDARD LVCMOS33 } [get_ports { prog_d[7] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jb_n[4]
+ ```
+ - Ensure **V3V3** pins are tied to **VIO** in the MiniModule.
+
+4. **FT2232H Configuration**
+ - Use **FT_Prog** (or equivalent) to set the MiniModule into **USB FIFO mode**.
+ - ⚠️ Digilent Adept drivers validate a protected EEPROM region not writable via FT_Prog.
+ - Either use Digilent reprogramming executable
+ - Or adapt the C++ receiver to be compatible with the FTDI drivers.
+
+
+
+
Figure: Valid EEPROM for DPTI
+
+
+---
+
+### Bitstream Build & Deployment
+
+Once hardware wiring and constraints are in place with ITI, Encoder, Encapsulator, etc. :
+> We used Vivado version: 2018.2
+```bash
+make clean
+make fpga TARGET=cv32a6_imac_sv32
+```
+
+Then upload the generated ariane_xilinx.bit via Vivado Lab or your preferred hardware manager.
+
+---
+## 4. Software-Side Reception
+
+The trace reception is handled on a **Linux-based host PC**, which is connected either to the **FTDI MiniModule** or directly to the **Genesys2 board via port J17**.
+
+To enable communication via **DPTI (Digilent Parallel Trace Interface)**, you must first install the [**Digilent Adept SDK**](https://lp.digilent.com/complete-adept-runtime-download), specifically version `2.4.2`. This provides the required runtime libraries and development headers. The receiver code needs a C++17 version for `std::optional`.
+
+---
+
+### Setup Instructions
+
+1. **Install Adept SDK**
+
+ * Ensure the Digilent API is installed and correctly configured.
+ * The official Digilent SDK and documentation provide a guide.
+
+2. **Configure and Compile the Receiver**
+
+ * The receiver code is located in `Receiver_DPTI.cpp`.
+ * You must **edit the `Makefile`** to match the paths to the Adept libraries and headers.
+
+ * Refer to the README files in `digilent.adept.sdk_2.4.2/samples` for more informations .
+ * Then compile the program with:
+
+ ```bash
+ make clean
+ make
+ ```
+
+3. **Device Detection and Debugging**
+
+ * The receiver includes debug function, such as `Scan_Device`, which:
+
+ * Lists connected FTDI devices
+ * Displays their names
+
+4. **Configure BOARD\_NAME**
+
+ * You must update the `BOARD_NAME` field in `Receiver_DPTI.cpp` to match the actual serial string of your connected device.
+ * Example:
+
+ ```cpp
+ char* BOARD_NAME = (char*) "#tpt_0001#ptc_0002#210300075227";
+ ```
+ * After editing the file, recompile:
+
+ ```bash
+ make clean
+ make
+ ```
+
+5. **Running the Receiver**
+
+ * Launch the receiver with:
+
+ ```bash
+ ./Receiver_DPTI
+ ```
+ * The program proceeds in **two phases**:
+
+ * **Acquisition Phase**: Data is streamed and stored in raw format. Stop the acquisition with `SIGINT` (Ctrl+C).
+ * **Decapsulation Phase**: The raw binary packets are parsed and converted into human-readable CSV format.
+
+
+
+
+
Figure: Valid execution ./Receiver_DPTI
+
+
+---
+
+### Output Files
+
+Two output files are generated in the `receiver_data/` directory:
+
+* `YYYYMMDD_hhmm_raw_file.txt` - the raw encapsulated packets
+* `YYYYMMDD_hhmm_data.csv` - the decoded content in CSV format
+
+These CSV files can be supplied to a decoder for further analysis.
+
+>Currently, no custom decoder is implemented. We use the reference decoder provided in the Reference Flow repository to interpret the trace contents. The University of Bologna released a version of their decoder on 3rd July 2025, but we have not evaluated it yet.
+
+---
+
+## 5. Decoder
+
+At this stage, we have **not yet implemented** our own decoder. Instead, we rely on the **Reference Flow decoder** provided by the E‑Trace specification.
+
+#### Running the Reference Flow
+
+To perform decoding, you first need to run the full reference flow regression so that it can generate the files from the program binary required by its version of Spike(in the `referenceFlow`). In addition, your compiled program must be renamed with a `.riscv` extension so that the flow recognizes it as RISC‑V input and it need to be place in `referenceFlow/tests/test_files`.
+
+1. **Prepare your binary**
+ ```bash
+ cp path/to/your_program.elf referenceFlow/tests/test_files/your_program.riscv
+ ```
+2. **Execute the full reference flow**
+```bash
+cd referenceFlow
+./scripts/run_regression.sh \
+ -t itype3_debug \
+ --annotate \
+ --debug\
+ tests/test_files/your_program.riscv
+```
+
+ * `-t`: Specify the test suite used, here we choose `itype3_debug` to match our encoder and `_debug` to add more information in packets like `full_address mode`
+ * `--annotate`: This flag is optionnal and using it create annotated version of output files , usefull for understanding/debugging
+ * `--debug`: This flag is optionnal and using it will print in the terminal more informations about each stage
+
+### Decoding the Trace
+Once the reference flow regression has run successfully (and generated the files needed), you can invoke the decoder step:
+
+```bash
+cd referenceFlow
+./scripts/decoder_model.py \
+ -u regression_YYYYMMDD_hhmmss/itype3_debug/your_program.decoder.ucf \
+ -c regression_YYYYMMDD_hhmmss/itype3_debug/hardware.scf \
+ -i TRACE_OUTPUT
+
+```
+ * `-u`: user_config, this file is generated with the first regression, inside there are information about debug flags, object-files, encoder configuration, etc
+ * `-c`: static_config, this file is also generated but correspond to test suite you choose, inside there are informations about default values (size of fields, encoder options, etc)
+ * `-i`: This file is the output of the encoder by default :`regression_YYYYMMDD_hhmmss/itype3_debug/your_program.te_inst_raw` but you can use the trace from the receiver, it support CSV format and raw format (needs to be a real binary in this case)
+
+ If everything matches, meaning there are no difference between the captured trace and the reference Trace, you will obtain an output file like this:
+
+
+
+
Figure: Excerpt from decoded trace
+
+
+
+⚠️ Mismatches can occur if, for example:
+
+* The platform's address map (CrossBar) doesn't align with your binary's load addresses
+
+* The encoder fails to emit a packet (e.g., due to a bug in the encoder)
+
+* There is receiver desynchronization or signal glitches during trace capture
+
+### Current Limitations & Future Work
+When we load the program via the onboard Debug Module, you will notice "trace pollution" : extra instructions corresponding to debug and JTAG activity appear in the trace. One way to mitigate this is to use the Filter submodule in the encoder to suppress unwanted instructions. However:
+
+**Problem:** We have not yet exposed the APB path needed to drive the Filter's control registers at runtime.
+
+**Next Steps:** Extend the encoder to include an APB interface for the Filter module, allowing dynamic trace filtering before encapsulation.
+
+
+## 6. Debug Automation & VSCode Setup
+
+This section presents a set of **automation tools and configurations** developed to streamline the debug process using **Visual Studio Code (VSCode)**. The goal is to make it easy to:
+
+* **Compile user programs** into a binary format compatible with the **CV32A6** core
+* **Launch OpenOCD** using the expected configuration (`ariane.cfg`)
+* **Start GDB** in **remote debug mode**, attached to the target via OpenOCD
+
+---
+
+### VSCode Integration
+
+To integrate these operations directly within the VSCode interface, we make use of two special configuration files:
+
+* `.vscode/launch.json` - defines how to start a debugging session
+* `.vscode/tasks.json` - defines custom build and terminal commands
+
+With this setup, you can use the built-in **debug pane** of VSCode to:
+
+* Upload and connect to the board
+* Step through code using breakpoints and GDB integration
+
+These files must be placed inside a `.vscode/` directory at the root of the project.
+
+---
+
+### File Overview
+
+**launch.json**
+
+```json
+{
+ "version": "0.2.0",
+ "configurations": [
+ {
+ "name": "Debug FPGA via OpenOCD",
+ "type": "cppdbg",
+ "targetArchitecture": "x86_64",
+ "request": "launch",
+ "program": "${workspaceFolder}/Prog_compiled",
+ "miDebuggerServerAddress": "localhost:3333",
+ "useExtendedRemote": true,
+ "miDebuggerPath": "toolchain/bin/riscv-none-elf-gdb",
+ "stopAtEntry": true,
+ "stopAtConnect": true,
+ "cwd": "${workspaceFolder}",
+ "environment": [],
+ "externalConsole": false,
+ "MIMode": "gdb",
+ "preLaunchTask": "build-and-start-openocd",
+ "postRemoteConnectCommands": [
+ {
+ "text": "source ${workspaceFolder}/gdb_init.txt"
+ }
+ ]
+ }
+ ]
+ }
+```
+
+**tasks.json**
+
+```json
+{
+ "version": "2.0.0",
+ "tasks": [
+
+ {
+ "label": "build-exec",
+ "type": "shell",
+ "command": "riscv-none-elf-gcc",
+ "args": [
+ "-g", "-T", "custom_linker.ld",
+ "-march=rv32imac_zicsr",
+ "-lgcc", "-fvisibility=hidden",
+ "-mcmodel=medany", "-mabi=ilp32",
+ "-nostartfiles", "crt.S", "syscalls.c", "test.c",
+ "-o", "Prog_compiled"
+ ],
+ "problemMatcher": [],
+ "group": {
+ "kind": "build",
+ "isDefault": true
+ }
+ },
+ {
+ "label": "start openocd",
+ "type": "shell",
+ "command": "bash",
+ "args": [
+ "-c",
+ "nohup gnome-terminal -- bash -c \"openocd -f ariane.cfg; exec bash\""
+ ],
+ "problemMatcher": []
+ },
+ {
+ "label": "build-and-start-openocd",
+ "dependsOn": ["build-exec", "start openocd"]
+ }
+ ]
+ }
+
+
+```
+
+These configurations are adaptable to your own build system or directory structure.
+
+---
+
+### Additional Resources
+
+* [VSCode Debugging Documentation](https://code.visualstudio.com/docs/debugtest/debugging)
+* [VSCode Task Configuration](https://code.visualstudio.com/docs/debugtest/tasks)
diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile b/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile
new file mode 100644
index 0000000000..50517ba22e
--- /dev/null
+++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile
@@ -0,0 +1,30 @@
+# Copyright 2025 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Author: Maxime Colson - Thales
+
+# Makefile to build the receiver executable
+# You need to properly install Digilent Adept and correctly link adept sdk lib
+CC = g++
+INC ?= $(HOME)/runtime_adept/digilent.adept.sdk_2.4.2
+LIBDIR = /usr/lib64/digilent/adept
+TARGETS = Receiver_DPTI
+CFLAGS = -I $(INC) -L $(LIBDIR) -ldpti -ldmgr -Wall -Wextra -g
+
+all: $(TARGETS)
+
+Receiver_DPTI: Receiver_DPTI.cpp
+ $(CC) -o Receiver_DPTI Receiver_DPTI.cpp $(CFLAGS)
+
+.PHONY: clean
+
+clean:
+ rm -f $(TARGETS)
+
+clean_all:
+ rm -f $(TARGETS)
+ rm -rf receiver_data
diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp b/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp
new file mode 100644
index 0000000000..51290d38d6
--- /dev/null
+++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp
@@ -0,0 +1,455 @@
+// Copyright (c) 2025 Thales DIS design services SAS
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+// Author: Maxime Colson - Thales
+// Date: 17/06/2025
+// Contributors:
+// Côme Allart - Thales
+
+// This code is designed to receive encapsulated packets emitted by an instruction encoder (See e-trace-encap).
+// It captures them in two formats: raw and decapsulated (.csv).
+// These files can then be passed to a decoder (e.g., riscv-trace-spec/referenceFlow/scripts/decoder_model.py).
+
+// To properly use this receiver, you need a Digilent FPGA board using the DPTI module from the Adept SDK.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dpcdecl.h"
+#include "dmgr.h"
+#include "dpti.h"
+
+volatile sig_atomic_t stop = 0;
+
+void handle_sigint(int) { stop = 1; }
+
+const size_t NR_PKT = 20;
+const size_t PACKET_SIZE = 40;
+const size_t BLOCK_SIZE = NR_PKT * PACKET_SIZE;
+
+typedef BYTE packet_t[PACKET_SIZE];
+typedef std::array sample_t;
+
+uint64_t extract_bits(const packet_t &packet, std::size_t bit_offset,
+ std::size_t bit_length) { // FIXME add assertion to prevent desynchro segfault
+ uint64_t result = 0xdead; // We use 'dead' as an indicator to quickly detect if a desynchro happened during the aquisition (without stoping decapsulation)
+ if (bit_length <= 64) {
+ result = 0;
+ for (std::size_t i = 0; i < bit_length; ++i) {
+ std::size_t global_bit = bit_offset + i;
+ std::size_t byte_index = global_bit / 8;
+ std::size_t bit_index = 7 - (global_bit % 8);
+ uint64_t bit = (packet[byte_index] >> bit_index) & 0x1;
+ result = (result << 1) | bit;
+ }
+ }
+ return result;
+}
+
+template struct PrintableOption : public std::optional {
+ PrintableOption(std::optional &o) : std::optional(o) {}
+ PrintableOption(T &v) : std::optional(v) {}
+ PrintableOption(uint64_t v) : std::optional(v) {}
+ PrintableOption() : std::optional() {}
+
+ friend std::ostream &operator<<(std::ostream &s, const PrintableOption &o) {
+ if (o.has_value())
+ s << unsigned(*o);
+ else
+ s << "_";
+
+ return s;
+ }
+};
+
+struct BitExtractor {
+ const packet_t &packet;
+ bool is_backward;
+ size_t i;
+
+ BitExtractor(const packet_t &packet, bool backward)
+ : packet(packet), is_backward(backward),
+ i(backward ? PACKET_SIZE * 8 : 0) {}
+
+ uint64_t operator()(size_t bits) { return extract(bits); }
+ uint64_t to(size_t bit) { return extract_to(bit); }
+
+ uint64_t extract_to(size_t bit) { return extract(i - bit); }
+ uint64_t extract(size_t bits) {
+ if (is_backward)
+ i -= bits;
+
+ uint64_t result = extract_bits(packet, i, bits);
+
+ if (!is_backward)
+ i += bits;
+
+ return result;
+ }
+};
+
+struct Trace {
+ bool P_Time; // MSB
+ uint8_t P_ID; // 2 bits after MSB
+ uint8_t P_Size; // 5bits after P_ID
+ uint64_t P_Timestamp; // 64 bits after P_Size
+ PrintableOption format; // 2bits LSB
+ PrintableOption subformat; // 2bits before LSB if format=3
+ PrintableOption address; // start of payload
+ PrintableOption branch; // F3SF0 (5) F3SF1 (5) else NDF
+ PrintableOption branches; // F1 (3)
+ PrintableOption branch_map; // F1 (4 : branches)
+ PrintableOption branch_count; // NDF
+ PrintableOption branch_fmt; // NDF
+ PrintableOption context; // NDF
+ PrintableOption ecause; //F3SF1 (8) F3SF1T (70)
+ PrintableOption ienable; //F3SF3 (5)
+ PrintableOption encoder_mode;//F3SF3 (6)
+ PrintableOption interrupt; // F3SF1(9) F3SF1T(71)
+ PrintableOption irreport; // F2 (5) F1(5)
+ PrintableOption irdepth; //if call/ret F2(6:2^cal) F1(6:2^cal) else NDF
+ PrintableOption notify; // F2(3) F1(3)
+ PrintableOption ioptions; //F3SF3 (8:15)
+ PrintableOption privilege; // F3SF0 (6) F3SF1 (6) F3SF2 (5)
+ PrintableOption qual_status;// F3SF3(7)
+ PrintableOption time; //if time F3SF0(8:72) F3SF1(8:72) F3SF2(7:71) //FIXME encoder could have time in last position
+ PrintableOption thaddr; // F3SF1(40) F3SF1_t(104)
+ PrintableOption tval; //F3SF1 (41:73) F3SF1_t(105:137)
+ PrintableOption updiscon;// F2(4)
+ PrintableOption denable;// NDF here
+ PrintableOption dloss;// NDF here
+ PrintableOption doptions;// NDF here
+ uint8_t size_branch_map;
+
+ Trace(const packet_t &packet, bool time_flag, bool call_flag) {
+ size_branch_map = 0;
+
+ BitExtractor header_extractor(packet, false);
+ BitExtractor payload_extractor(packet, true);
+
+ // Header of encapsulated packet :
+ P_Time = header_extractor(1);
+ P_ID = header_extractor(2);
+ P_Size = header_extractor(5);
+ size_t P_Start = (PACKET_SIZE - P_Size) * 8;
+ P_Timestamp = header_extractor(64);
+
+ // Extraction of fields contained in the payload :
+ format = payload_extractor(2);
+ if (format == 3) {
+ subformat = payload_extractor(2);
+ }
+
+ if (format == 3 && subformat.has_value()) {
+ switch (subformat.value()) {
+ case 0: { // F3SF0
+ branch = payload_extractor(1);
+ privilege = payload_extractor(2);
+ if (time_flag) {
+ time = payload_extractor(64);
+ }
+ address = payload_extractor.to(P_Start);
+ break;
+ }
+ case 1: { // F3SF1
+ branch = payload_extractor(1);
+ privilege = payload_extractor(2);
+ if (time_flag) {
+ time = payload_extractor(64);
+ }
+ ecause = payload_extractor(32);
+ interrupt = payload_extractor(1);
+ thaddr = payload_extractor(1);
+ tval = payload_extractor(32);
+ address = payload_extractor.to(P_Start);
+ break;
+ }
+ case 2: { // F3SF2
+ privilege = payload_extractor(2);
+ if (time_flag) {
+ time = payload_extractor(64);
+ }
+ break;
+ }
+ case 3: { // F3SF3
+ ienable = payload_extractor(1);
+ encoder_mode = payload_extractor(1);
+ qual_status = payload_extractor(2);
+ ioptions = payload_extractor(7);
+ break;
+ }
+ }
+ }
+
+ // F2
+ if (format == 2) {
+ notify = payload_extractor(1);
+ updiscon = payload_extractor(1);
+ irreport = payload_extractor(1);
+ if (call_flag) { // FIXME addapt to call_counter_size
+ irdepth = payload_extractor(1); // if = 0 else 2^call_counter_size
+ }
+ address = payload_extractor.to(P_Start);
+ }
+
+ // F1
+ if (format == 1) {
+ branches = payload_extractor(5);
+ if(branches==0) {
+ size_branch_map = 31;
+ } else if (branches == 1) {
+ size_branch_map = 1;
+ } else if (branches <= 3) {
+ size_branch_map = 3;
+ } else if (branches <= 7) {
+ size_branch_map = 7;
+ } else if (branches <= 15) {
+ size_branch_map = 15;
+ } else {
+ size_branch_map = 31;
+ }
+
+ branch_map = payload_extractor(size_branch_map);
+
+ if (branches != 0) {
+ notify = payload_extractor(1);
+ updiscon = payload_extractor(1);
+ irreport = payload_extractor(1);
+ if (call_flag) { // FIXME addapt to call_counter_size
+ irdepth = payload_extractor(1); // if = 0 else 2^call_counter_size
+ }
+ address = payload_extractor.to(P_Start);
+ }
+ }
+ }
+
+ static std::string csvHeader() {
+ return std::string(
+ "format,subformat,address,branch,branches,branch_map,branch_count,"
+ "branch_fmt,context,ecause,ienable,encoder_mode,interrupt,irreport,"
+ "irdepth,notify,ioptions,privilege,qual_status,time,thaddr,tval,"
+ "updiscon,denable,dloss,doptions");
+ }
+
+ friend std::ostream &operator<<(std::ostream &s, Trace const &trace) {
+ trace.put_str(s);
+ return s;
+ }
+
+ std::ostream &put_str(std::ostream &s) const {
+ s << format << "," << subformat << ",";
+
+ s << std::hex << std::nouppercase << address << std::dec << ",";
+
+ s << branch << "," << branches << "," << branch_map << "," << branch_count
+ << "," << branch_fmt << ",";
+
+ s << context << "," << ecause << "," << ienable << "," << encoder_mode
+ << "," << interrupt << ",";
+
+ s << irreport << "," << irdepth << "," << notify << "," << ioptions << ","
+ << privilege << "," << qual_status << ",";
+
+ s << std::hex << std::nouppercase << time << std::dec << ",";
+
+ s << thaddr << "," << tval << "," << updiscon << "," << denable << ","
+ << dloss << "," << doptions ;
+
+ return s;
+ }
+
+ std::string toCSVLine() {
+ std::ostringstream oss;
+ oss << *this;
+ return oss.str();
+ }
+};
+
+std::string getTime () {
+ auto now = std::chrono::system_clock::now();
+ std::time_t t = std::chrono::system_clock::to_time_t(now);
+ std::tm tm = *std::localtime(&t);
+ std::ostringstream ts;
+ ts << std::put_time(&tm, "%Y%m%d_%H%M");
+ std::string timestamp = ts.str();
+
+ return timestamp;
+}
+
+void Scan_Device (){
+ int indexmax;
+ DmgrEnumDevices(&indexmax);
+ std::cout << indexmax < transaction_DPTI(uint32_t peripheral_handle) {
+ bool Transaction;
+ int error;
+ auto sample_ptr = std::make_unique();
+ Transaction = DptiIO(peripheral_handle, NULL, 0, (BYTE *) sample_ptr.get(), BLOCK_SIZE, false);
+
+ if (!Transaction) {
+ error = DmgrGetLastError();
+ if (error == ercTransferCancelled) {
+ throw std::runtime_error("data transfer timed out");
+ } else {
+ throw std::runtime_error("data transfer failed code : " + std::to_string(error));
+ }
+ }
+ return sample_ptr;
+}
+
+int main() {
+ // Change this field according to your board / encoder
+ char *BOARD_NAME = (char*)"#tpt_0001#ptc_0002#210300075227";
+ const int32_t PORT = 1; // 0 or 1
+ const bool TIME_FLAG = 1;
+ const bool CALL_FLAG = 0;
+
+ uint32_t peripheral_handle;
+ peripheral_handle = hifInvalid;
+ size_t counter = 0;
+ std::vector> all_data;
+ //Scan_Device();
+ const std::string out_dir = "receiver_data";
+
+ if (!std::filesystem::exists(out_dir)) {
+ std::filesystem::create_directory(out_dir);
+ }
+
+ std::string timestamp= getTime();
+
+ // File paths
+ std::string raw_path = out_dir + "/" + timestamp + "_raw_file.txt";
+ std::string csv_path = out_dir + "/" + timestamp + "_data.csv";
+
+ std::ofstream raw_file(raw_path);
+ std::ofstream csvFile(csv_path);
+
+
+
+ // Initialisation of the DPTI Channel
+ try {
+ peripheral_handle = init_DPTI(BOARD_NAME, PORT);
+ } catch (const std::exception &e) {
+ if (peripheral_handle != hifInvalid) {
+ DptiDisable(peripheral_handle);
+ DmgrClose(peripheral_handle);
+ }
+ std::cerr << "ERROR Init : " << e.what() << std::endl;
+ return 1;
+ }
+
+
+ // Capture loop
+ signal(SIGINT, handle_sigint);
+ std::cout << "\nLoop (Ctrl+C to exit)\n\n";
+ auto capture_start = std::chrono::high_resolution_clock::now();
+ while (!stop) {
+ try {
+ auto sample_ptr = transaction_DPTI(peripheral_handle);
+ all_data.push_back(std::move(sample_ptr));
+
+ std::cout << "\rIteration : " << counter << " " << std::flush;
+ counter += NR_PKT;
+ } catch (const std::exception &e) {
+ std::cerr << "ERROR Transaction : " << e.what() << std::endl;
+ break;
+ }
+ }
+ auto capture_end = std::chrono::high_resolution_clock::now();
+
+ std::chrono::duration capture_delta_time =
+ capture_end - capture_start;
+ double capture_delta_time_sec = capture_delta_time.count();
+ double throughput = (counter * PACKET_SIZE * 8) / capture_delta_time_sec;
+ if (throughput < 1e6) {
+ std::cout << "\n\nThroughput : " << std::fixed << std::setprecision(2)
+ << throughput / 1e3 << " Kb/s";
+ } else {
+ std::cout << "\n\nThroughput : " << std::fixed << std::setprecision(2)
+ << throughput / 1e6 << " Mb/s";
+ }
+ std::cout << "\t\tCapturing took :" << capture_delta_time_sec << "s\n";
+
+ // Writing output : Raw / Decapsulated csv
+ auto write_start = std::chrono::high_resolution_clock::now();
+ if (csvFile.is_open() && raw_file.is_open()) {
+ csvFile << Trace::csvHeader() << "\n";
+ for (const auto &sample_ptr : all_data) {
+ for (const packet_t &packet : *sample_ptr) {
+ Trace trace(packet, TIME_FLAG, CALL_FLAG);
+ csvFile << trace.toCSVLine() << "\n";
+ for (size_t k = 0; k < PACKET_SIZE; ++k) {
+ raw_file << std::uppercase << std::hex << std::setw(2)
+ << std::setfill('0') << (unsigned)packet[k];
+ }
+ raw_file << "\n";
+ }
+ }
+ std::cout
+ << "\n========================SUCCESS_WRITE========================\n";
+ }
+ auto write_end = std::chrono::high_resolution_clock::now();
+ std::chrono::duration write_delta_time = write_end - write_start;
+ double write_delta_time_sec = write_delta_time.count();
+ std::cout << "\nWriting Took : " << write_delta_time_sec << "s\n";
+
+ auto raw_size = std::filesystem::file_size(raw_path);
+ auto csv_size = std::filesystem::file_size(csv_path);
+ std::cout << "\nRaw file size: " << raw_size / 1e6 << " Mbytes\t";
+ std::cout << "CSV file size: " << csv_size / 1e6 << " Mbytes\n";
+
+ DptiDisable(peripheral_handle);
+ DmgrClose(peripheral_handle);
+
+ std::cout
+ << "\n========================SUCCESS_CLOSE========================\n\n";
+
+ return 0;
+}
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh b/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh
new file mode 100644
index 0000000000..0bbd3ed316
--- /dev/null
+++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh
@@ -0,0 +1,34 @@
+#!/usr/bin/env bash
+# Copyright 2025 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Author: Maxime Colson - Thales
+# THis script remove lines above the start packet 3.3
+
+if [ $# -ne 1 ]; then
+ echo "Usage!: $0 file/to/clean.csv"
+ exit 1
+fi
+# This script will clean the csv trace by starting the trace at the first packet after reset
+input_file="$1"
+output_file="${input_file%.csv}_cleaned.csv"
+temp_file=$(mktemp)
+
+awk 'found || /^3,3,_,_,/ {found=1; print}' "$input_file" > "$temp_file"
+
+{
+ printf "format,subformat,address,branch,branches,branch_map,branch_count,"
+ printf "branch_fmt,context,ecause,ienable,encoder_mode,interrupt,irreport,"
+ printf "irdepth,notify,ioptions,privilege,qual_status,time,thaddr,tval,"
+ printf "updiscon,denable,dloss,doptions\n"
+
+ cat "$temp_file"
+} > "$output_file"
+
+rm "$temp_file"
+
+echo "File Cleaned : $output_file"
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh b/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh
new file mode 100644
index 0000000000..68355bf883
--- /dev/null
+++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh
@@ -0,0 +1,39 @@
+# Copyright 2025 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Author: Maxime Colson - Thales
+
+#Script to automate the aquisition process for the receiver
+
+NR_PKTS=(1 2 10 20 50 100 200)
+DURATION=5
+
+LOG_FILE="log_$(date +'%Y%m%d_%H%M%S').txt"
+echo "Fichier de log : $LOG_FILE"
+
+echo -e "NR_PKT\tThroughput (Mb/s)" > "$LOG_FILE"
+
+capture_fct() {
+ ./Receiver_DPTI &
+ PID=$!
+ sleep "$DURATION"
+ kill -SIGINT "$PID"
+ sleep 2
+}
+
+for i in "${NR_PKTS[@]}"; do
+ echo "=== NR_PKT = $i ==="
+ sed -i "s/const int NR_PKT = [0-9]\+;/const int NR_PKT = $i;/" Receiver_DPTI.cpp
+ make > /dev/null || { echo "Compilation échouée à $i"; exit 1; }
+
+ OUTPUT=$(capture_fct | grep -oP 'Throughput\s*:\s*\K[0-9.]+' )
+ echo "$i : $OUTPUT" | tee -a "$LOG_FILE"
+
+done
+
+python3 script.py "$LOG_FILE"
+
diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py b/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py
new file mode 100644
index 0000000000..2b3f1ef61e
--- /dev/null
+++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py
@@ -0,0 +1,59 @@
+# Copyright 2025 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Author: Maxime Colson - Thales
+
+#Script to plot data from run_timeout.sh aquisition with receiver
+
+import sys
+import matplotlib.pyplot as plt
+
+def parse_log(file_path):
+ nr_pkts = []
+ throughputs = []
+ with open(file_path) as f:
+ for line in f:
+ line = line.strip()
+ if not line or ':' not in line or line.startswith('NR_PKT'):
+ continue
+ try:
+ pkt_str, tp_str = line.split(':')
+ pkt = int(pkt_str.strip())
+ tp = float(tp_str.strip())
+ nr_pkts.append(pkt)
+ throughputs.append(tp)
+ except ValueError:
+ continue
+ return nr_pkts, throughputs
+
+def main():
+ if len(sys.argv) != 2:
+ print(f"Usage: {sys.argv[0]} ")
+ sys.exit(1)
+
+ log_file = sys.argv[1]
+ nr_pkts, throughputs = parse_log(log_file)
+
+ if not nr_pkts:
+ print("Aucune donnée valide trouvée dans le fichier.")
+ sys.exit(1)
+
+ print("\nNR_PKT\tThroughput (Mb/s)")
+ for pkt, tp in zip(nr_pkts, throughputs):
+ print(f"{pkt}\t{tp}")
+
+ plt.figure()
+ plt.plot(nr_pkts, throughputs, marker='o')
+ plt.xlabel("Nombre de paquets (NR_PKT)")
+ plt.ylabel("Throughput (Mb/s)")
+ plt.title("NR_PKT vs Throughput")
+ plt.grid(True)
+ plt.tight_layout()
+ plt.show()
+
+if __name__ == "__main__":
+ main()
diff --git a/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh b/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh
new file mode 100644
index 0000000000..3dcaa82005
--- /dev/null
+++ b/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh
@@ -0,0 +1,27 @@
+#!/usr/bin/env bash
+# Copyright 2025 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Author: Maxime Colson - Thales
+capture_fct() {
+ ./Receiver_DPTI &
+ PID=$!
+ sleep 5
+ kill -SIGINT "$PID"
+ sleep 2
+}
+
+NR_PKTS=(10 20 50 100 200)
+
+for i in "${NR_PKTS[@]}"; do
+ echo "=== $i ==="
+
+ sed -i "s/const int NR_PKT = [0-9]\+;/const int NR_PKT = $i;/" Receiver_DPTI.cpp
+ make -s
+ capture_fct >> log2.txt
+
+done
diff --git a/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE b/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE
new file mode 100644
index 0000000000..3931d9e54f
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE
@@ -0,0 +1,176 @@
+SOLDERPAD HARDWARE LICENSE version 0.51
+
+This license is based closely on the Apache License Version 2.0, but is not
+approved or endorsed by the Apache Foundation. A copy of the non-modified
+Apache License 2.0 can be found at http://www.apache.org/licenses/LICENSE-2.0.
+
+As this license is not currently OSI or FSF approved, the Licensor permits any
+Work licensed under this License, at the option of the Licensee, to be treated
+as licensed under the Apache License Version 2.0 (which is so approved).
+
+This License is licensed under the terms of this License and in particular
+clause 7 below (Disclaimer of Warranties) applies in relation to its use.
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+"License" shall mean the terms and conditions for use, reproduction, and
+distribution as defined by Sections 1 through 9 of this document.
+
+"Licensor" shall mean the Rights owner or entity authorized by the Rights owner
+that is granting the License.
+
+"Legal Entity" shall mean the union of the acting entity and all other entities
+that control, are controlled by, or are under common control with that entity.
+For the purposes of this definition, "control" means (i) the power, direct or
+indirect, to cause the direction or management of such entity, whether by
+contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the
+outstanding shares, or (iii) beneficial ownership of such entity.
+
+"You" (or "Your") shall mean an individual or Legal Entity exercising
+permissions granted by this License.
+
+"Rights" means copyright and any similar right including design right (whether
+registered or unregistered), semiconductor topography (mask) rights and
+database rights (but excluding Patents and Trademarks).
+
+"Source" form shall mean the preferred form for making modifications, including
+but not limited to source code, net lists, board layouts, CAD files,
+documentation source, and configuration files.
+
+"Object" form shall mean any form resulting from mechanical transformation or
+translation of a Source form, including but not limited to compiled object
+code, generated documentation, the instantiation of a hardware design and
+conversions to other media types, including intermediate forms such as
+bytecodes, FPGA bitstreams, artwork and semiconductor topographies (mask
+works).
+
+"Work" shall mean the work of authorship, whether in Source form or other
+Object form, made available under the License, as indicated by a Rights notice
+that is included in or attached to the work (an example is provided in the
+Appendix below).
+
+"Derivative Works" shall mean any work, whether in Source or Object form, that
+is based on (or derived from) the Work and for which the editorial revisions,
+annotations, elaborations, or other modifications represent, as a whole, an
+original work of authorship. For the purposes of this License, Derivative Works
+shall not include works that remain separable from, or merely link (or bind by
+name) or physically connect to or interoperate with the interfaces of, the Work
+and Derivative Works thereof.
+
+"Contribution" shall mean any design or work of authorship, including the
+original version of the Work and any modifications or additions to that Work or
+Derivative Works thereof, that is intentionally submitted to Licensor for
+inclusion in the Work by the Rights owner or by an individual or Legal Entity
+authorized to submit on behalf of the Rights owner. For the purposes of this
+definition, "submitted" means any form of electronic, verbal, or written
+communication sent to the Licensor or its representatives, including but not
+limited to communication on electronic mailing lists, source code control
+systems, and issue tracking systems that are managed by, or on behalf of, the
+Licensor for the purpose of discussing and improving the Work, but excluding
+communication that is conspicuously marked or otherwise designated in writing
+by the Rights owner as "Not a Contribution."
+
+"Contributor" shall mean Licensor and any individual or Legal Entity on behalf
+of whom a Contribution has been received by Licensor and subsequently
+incorporated within the Work.
+
+2. Grant of License. Subject to the terms and conditions of this License, each
+Contributor hereby grants to You a perpetual, worldwide, non-exclusive,
+no-charge, royalty-free, irrevocable license under the Rights to reproduce,
+prepare Derivative Works of, publicly display, publicly perform, sublicense,
+and distribute the Work and such Derivative Works in Source or Object form and
+do anything in relation to the Work as if the Rights did not exist.
+
+3. Grant of Patent License. Subject to the terms and conditions of this
+License, each Contributor hereby grants to You a perpetual, worldwide,
+non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this
+section) patent license to make, have made, use, offer to sell, sell, import,
+and otherwise transfer the Work, where such license applies only to those
+patent claims licensable by such Contributor that are necessarily infringed by
+their Contribution(s) alone or by combination of their Contribution(s) with the
+Work to which such Contribution(s) was submitted. If You institute patent
+litigation against any entity (including a cross-claim or counterclaim in a
+lawsuit) alleging that the Work or a Contribution incorporated within the Work
+constitutes direct or contributory patent infringement, then any patent
+licenses granted to You under this License for that Work shall terminate as of
+the date such litigation is filed.
+
+4. Redistribution. You may reproduce and distribute copies of the Work or
+Derivative Works thereof in any medium, with or without modifications, and in
+Source or Object form, provided that You meet the following conditions:
+
+ You must give any other recipients of the Work or Derivative Works a copy
+ of this License; and
+
+ You must cause any modified files to carry prominent notices stating that
+ You changed the files; and
+
+ You must retain, in the Source form of any Derivative Works that You
+ distribute, all copyright, patent, trademark, and attribution notices from
+ the Source form of the Work, excluding those notices that do not pertain to
+ any part of the Derivative Works; and
+
+ If the Work includes a "NOTICE" text file as part of its distribution, then
+ any Derivative Works that You distribute must include a readable copy of
+ the attribution notices contained within such NOTICE file, excluding those
+ notices that do not pertain to any part of the Derivative Works, in at
+ least one of the following places: within a NOTICE text file distributed as
+ part of the Derivative Works; within the Source form or documentation, if
+ provided along with the Derivative Works; or, within a display generated by
+ the Derivative Works, if and wherever such third-party notices normally
+ appear. The contents of the NOTICE file are for informational purposes only
+ and do not modify the License. You may add Your own attribution notices
+ within Derivative Works that You distribute, alongside or as an addendum to
+ the NOTICE text from the Work, provided that such additional attribution
+ notices cannot be construed as modifying the License. You may add Your own
+ copyright statement to Your modifications and may provide additional or
+ different license terms and conditions for use, reproduction, or
+ distribution of Your modifications, or for any such Derivative Works as a
+ whole, provided Your use, reproduction, and distribution of the Work
+ otherwise complies with the conditions stated in this License.
+
+5. Submission of Contributions. Unless You explicitly state otherwise, any
+Contribution intentionally submitted for inclusion in the Work by You to the
+Licensor shall be under the terms and conditions of this License, without any
+additional terms or conditions. Notwithstanding the above, nothing herein shall
+supersede or modify the terms of any separate license agreement you may have
+executed with Licensor regarding such Contributions.
+
+6. Trademarks. This License does not grant permission to use the trade names,
+trademarks, service marks, or product names of the Licensor, except as required
+for reasonable and customary use in describing the origin of the Work and
+reproducing the content of the NOTICE file.
+
+7. Disclaimer of Warranty. Unless required by applicable law or agreed to in
+writing, Licensor provides the Work (and each Contributor provides its
+Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+KIND, either express or implied, including, without limitation, any warranties
+or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+PARTICULAR PURPOSE. You are solely responsible for determining the
+appropriateness of using or redistributing the Work and assume any risks
+associated with Your exercise of permissions under this License.
+
+8. Limitation of Liability. In no event and under no legal theory, whether in
+tort (including negligence), contract, or otherwise, unless required by
+applicable law (such as deliberate and grossly negligent acts) or agreed to in
+writing, shall any Contributor be liable to You for damages, including any
+direct, indirect, special, incidental, or consequential damages of any
+character arising as a result of this License or out of the use or inability to
+use the Work (including but not limited to damages for loss of goodwill, work
+stoppage, computer failure or malfunction, or any and all other commercial
+damages or losses), even if such Contributor has been advised of the
+possibility of such damages.
+
+9. Accepting Warranty or Additional Liability. While redistributing the Work or
+Derivative Works thereof, You may choose to offer, and charge a fee for,
+acceptance of support, warranty, indemnity, or other liability obligations
+and/or rights consistent with this License. However, in accepting such
+obligations, You may act only on Your own behalf and on Your sole
+responsibility, not on behalf of any other Contributor, and only if You agree
+to indemnify, defend, and hold each Contributor harmless for any liability
+incurred by, or claims asserted against, such Contributor by reason of your
+accepting any such warranty or additional liability.
+
+END OF TERMS AND CONDITIONS
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_encapsulator-main/README.md b/corev_apu/instr_tracing/rv_encapsulator-main/README.md
new file mode 100644
index 0000000000..6668722375
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_encapsulator-main/README.md
@@ -0,0 +1,2 @@
+The encapsulator is a modified version of https://github.com/pulp-platform/rv_encapsulator
+This directory (`rv_encapsulator-main`) is temporary and will soon be replaced by a submodule.
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv b/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv
new file mode 100644
index 0000000000..32af59527f
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv
@@ -0,0 +1,50 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/*
+all the type associated params are commented because the type is not required for trace encoders
+supporting only instruction tracing
+*/
+
+package encap_pkg;
+
+ localparam H_LEN = 8; // header length
+ //localparam SRCID_LEN = 7; // not used because only one source in system
+ //localparam TYPE_LEN = 8;
+ localparam PAYLOAD_LEN = 248 /*- TYPE_LEN - (SRCID_LEN % 8)*/; // trace_payload_len
+ localparam T_LEN = 64; // timestamp length: mcycle length is always 64
+ localparam FLOW_LEN = 2;
+ localparam P_LEN = 5;
+ localparam MAX_LEN = 264; // max length for payload to slice
+
+ typedef struct packed {
+ logic extend;
+ logic [FLOW_LEN-1:0] flow;
+ logic [P_LEN-1:0] length;
+ } header_s;
+
+ typedef struct packed {
+ //logic [TYPE_LEN-1:0] type; // omitted because only instruction trace available
+ logic [PAYLOAD_LEN-1:0] trace_payload;
+ } payload_s;
+
+ typedef struct packed {
+ header_s header;
+ //logic [SRCID_LEN-1:0] srcid;
+ logic [T_LEN-1:0] timestamp;
+ payload_s payload;
+ } encap_fifo_entry_s;
+
+endpackage
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv b/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv
new file mode 100644
index 0000000000..e93c8ba864
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv
@@ -0,0 +1,75 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/* ENCAPSULATOR */
+/*
+this module generates the header and payload necessary based on the protocol used
+*/
+
+module encapsulator (
+ // inputs
+ input logic clk_i,
+ input logic valid_i,
+ input logic [encap_pkg::P_LEN-1:0] packet_length_i,
+ input logic [encap_pkg::FLOW_LEN-1:0] flow_i,
+ input logic timestamp_present_i,
+ //input logic srcid_i,
+ input logic [encap_pkg::T_LEN-1:0] timestamp_i,
+ //input logic [encap_pkg::TYPE_LEN-1:0] type_i,
+ input logic [encap_pkg::PAYLOAD_LEN-1:0] trace_payload_i,
+
+ // outputs
+ output logic valid_o,
+ output encap_pkg::encap_fifo_entry_s encap_fifo_entry_o
+);
+ // pragma translate_off
+ int f;
+ initial begin
+ f = $fopen("encaps.traces", "w");
+ end
+ final $fclose(f);
+ // pragma translate_on
+
+always_comb begin
+ // initialization
+ valid_o = '0;
+ encap_fifo_entry_o = '0;
+
+ // assignments
+ if (valid_i) begin
+ valid_o = '1;
+ // header
+ encap_fifo_entry_o.header.length = packet_length_i;
+ encap_fifo_entry_o.header.flow = flow_i;
+ encap_fifo_entry_o.header.extend = timestamp_present_i;
+ // srcID
+ //encap_fifo_entry_o.srcid = srcid_i;
+ // timestamp
+ encap_fifo_entry_o.timestamp = timestamp_i;
+ // payload
+ encap_fifo_entry_o.payload.trace_payload = trace_payload_i;
+ end
+end
+// pragma translate_off
+always_ff @(posedge clk_i) begin
+ if (valid_o) begin
+ $fwrite(
+ f,
+ "%h\n",encap_fifo_entry_o);
+ end
+end
+// pragma translate_on
+
+endmodule
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/LICENSE b/corev_apu/instr_tracing/rv_tracer-main/LICENSE
new file mode 100644
index 0000000000..3931d9e54f
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/LICENSE
@@ -0,0 +1,176 @@
+SOLDERPAD HARDWARE LICENSE version 0.51
+
+This license is based closely on the Apache License Version 2.0, but is not
+approved or endorsed by the Apache Foundation. A copy of the non-modified
+Apache License 2.0 can be found at http://www.apache.org/licenses/LICENSE-2.0.
+
+As this license is not currently OSI or FSF approved, the Licensor permits any
+Work licensed under this License, at the option of the Licensee, to be treated
+as licensed under the Apache License Version 2.0 (which is so approved).
+
+This License is licensed under the terms of this License and in particular
+clause 7 below (Disclaimer of Warranties) applies in relation to its use.
+
+TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
+
+1. Definitions.
+
+"License" shall mean the terms and conditions for use, reproduction, and
+distribution as defined by Sections 1 through 9 of this document.
+
+"Licensor" shall mean the Rights owner or entity authorized by the Rights owner
+that is granting the License.
+
+"Legal Entity" shall mean the union of the acting entity and all other entities
+that control, are controlled by, or are under common control with that entity.
+For the purposes of this definition, "control" means (i) the power, direct or
+indirect, to cause the direction or management of such entity, whether by
+contract or otherwise, or (ii) ownership of fifty percent (50%) or more of the
+outstanding shares, or (iii) beneficial ownership of such entity.
+
+"You" (or "Your") shall mean an individual or Legal Entity exercising
+permissions granted by this License.
+
+"Rights" means copyright and any similar right including design right (whether
+registered or unregistered), semiconductor topography (mask) rights and
+database rights (but excluding Patents and Trademarks).
+
+"Source" form shall mean the preferred form for making modifications, including
+but not limited to source code, net lists, board layouts, CAD files,
+documentation source, and configuration files.
+
+"Object" form shall mean any form resulting from mechanical transformation or
+translation of a Source form, including but not limited to compiled object
+code, generated documentation, the instantiation of a hardware design and
+conversions to other media types, including intermediate forms such as
+bytecodes, FPGA bitstreams, artwork and semiconductor topographies (mask
+works).
+
+"Work" shall mean the work of authorship, whether in Source form or other
+Object form, made available under the License, as indicated by a Rights notice
+that is included in or attached to the work (an example is provided in the
+Appendix below).
+
+"Derivative Works" shall mean any work, whether in Source or Object form, that
+is based on (or derived from) the Work and for which the editorial revisions,
+annotations, elaborations, or other modifications represent, as a whole, an
+original work of authorship. For the purposes of this License, Derivative Works
+shall not include works that remain separable from, or merely link (or bind by
+name) or physically connect to or interoperate with the interfaces of, the Work
+and Derivative Works thereof.
+
+"Contribution" shall mean any design or work of authorship, including the
+original version of the Work and any modifications or additions to that Work or
+Derivative Works thereof, that is intentionally submitted to Licensor for
+inclusion in the Work by the Rights owner or by an individual or Legal Entity
+authorized to submit on behalf of the Rights owner. For the purposes of this
+definition, "submitted" means any form of electronic, verbal, or written
+communication sent to the Licensor or its representatives, including but not
+limited to communication on electronic mailing lists, source code control
+systems, and issue tracking systems that are managed by, or on behalf of, the
+Licensor for the purpose of discussing and improving the Work, but excluding
+communication that is conspicuously marked or otherwise designated in writing
+by the Rights owner as "Not a Contribution."
+
+"Contributor" shall mean Licensor and any individual or Legal Entity on behalf
+of whom a Contribution has been received by Licensor and subsequently
+incorporated within the Work.
+
+2. Grant of License. Subject to the terms and conditions of this License, each
+Contributor hereby grants to You a perpetual, worldwide, non-exclusive,
+no-charge, royalty-free, irrevocable license under the Rights to reproduce,
+prepare Derivative Works of, publicly display, publicly perform, sublicense,
+and distribute the Work and such Derivative Works in Source or Object form and
+do anything in relation to the Work as if the Rights did not exist.
+
+3. Grant of Patent License. Subject to the terms and conditions of this
+License, each Contributor hereby grants to You a perpetual, worldwide,
+non-exclusive, no-charge, royalty-free, irrevocable (except as stated in this
+section) patent license to make, have made, use, offer to sell, sell, import,
+and otherwise transfer the Work, where such license applies only to those
+patent claims licensable by such Contributor that are necessarily infringed by
+their Contribution(s) alone or by combination of their Contribution(s) with the
+Work to which such Contribution(s) was submitted. If You institute patent
+litigation against any entity (including a cross-claim or counterclaim in a
+lawsuit) alleging that the Work or a Contribution incorporated within the Work
+constitutes direct or contributory patent infringement, then any patent
+licenses granted to You under this License for that Work shall terminate as of
+the date such litigation is filed.
+
+4. Redistribution. You may reproduce and distribute copies of the Work or
+Derivative Works thereof in any medium, with or without modifications, and in
+Source or Object form, provided that You meet the following conditions:
+
+ You must give any other recipients of the Work or Derivative Works a copy
+ of this License; and
+
+ You must cause any modified files to carry prominent notices stating that
+ You changed the files; and
+
+ You must retain, in the Source form of any Derivative Works that You
+ distribute, all copyright, patent, trademark, and attribution notices from
+ the Source form of the Work, excluding those notices that do not pertain to
+ any part of the Derivative Works; and
+
+ If the Work includes a "NOTICE" text file as part of its distribution, then
+ any Derivative Works that You distribute must include a readable copy of
+ the attribution notices contained within such NOTICE file, excluding those
+ notices that do not pertain to any part of the Derivative Works, in at
+ least one of the following places: within a NOTICE text file distributed as
+ part of the Derivative Works; within the Source form or documentation, if
+ provided along with the Derivative Works; or, within a display generated by
+ the Derivative Works, if and wherever such third-party notices normally
+ appear. The contents of the NOTICE file are for informational purposes only
+ and do not modify the License. You may add Your own attribution notices
+ within Derivative Works that You distribute, alongside or as an addendum to
+ the NOTICE text from the Work, provided that such additional attribution
+ notices cannot be construed as modifying the License. You may add Your own
+ copyright statement to Your modifications and may provide additional or
+ different license terms and conditions for use, reproduction, or
+ distribution of Your modifications, or for any such Derivative Works as a
+ whole, provided Your use, reproduction, and distribution of the Work
+ otherwise complies with the conditions stated in this License.
+
+5. Submission of Contributions. Unless You explicitly state otherwise, any
+Contribution intentionally submitted for inclusion in the Work by You to the
+Licensor shall be under the terms and conditions of this License, without any
+additional terms or conditions. Notwithstanding the above, nothing herein shall
+supersede or modify the terms of any separate license agreement you may have
+executed with Licensor regarding such Contributions.
+
+6. Trademarks. This License does not grant permission to use the trade names,
+trademarks, service marks, or product names of the Licensor, except as required
+for reasonable and customary use in describing the origin of the Work and
+reproducing the content of the NOTICE file.
+
+7. Disclaimer of Warranty. Unless required by applicable law or agreed to in
+writing, Licensor provides the Work (and each Contributor provides its
+Contributions) on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+KIND, either express or implied, including, without limitation, any warranties
+or conditions of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A
+PARTICULAR PURPOSE. You are solely responsible for determining the
+appropriateness of using or redistributing the Work and assume any risks
+associated with Your exercise of permissions under this License.
+
+8. Limitation of Liability. In no event and under no legal theory, whether in
+tort (including negligence), contract, or otherwise, unless required by
+applicable law (such as deliberate and grossly negligent acts) or agreed to in
+writing, shall any Contributor be liable to You for damages, including any
+direct, indirect, special, incidental, or consequential damages of any
+character arising as a result of this License or out of the use or inability to
+use the Work (including but not limited to damages for loss of goodwill, work
+stoppage, computer failure or malfunction, or any and all other commercial
+damages or losses), even if such Contributor has been advised of the
+possibility of such damages.
+
+9. Accepting Warranty or Additional Liability. While redistributing the Work or
+Derivative Works thereof, You may choose to offer, and charge a fee for,
+acceptance of support, warranty, indemnity, or other liability obligations
+and/or rights consistent with this License. However, in accepting such
+obligations, You may act only on Your own behalf and on Your sole
+responsibility, not on behalf of any other Contributor, and only if You agree
+to indemnify, defend, and hold each Contributor harmless for any liability
+incurred by, or claims asserted against, such Contributor by reason of your
+accepting any such warranty or additional liability.
+
+END OF TERMS AND CONDITIONS
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/README.md b/corev_apu/instr_tracing/rv_tracer-main/README.md
new file mode 100644
index 0000000000..b9a88a29eb
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/README.md
@@ -0,0 +1,2 @@
+The encoder is a modified version of https://github.com/pulp-platform/rv_tracer
+This directory (`rv_tracer-main`) is temporary and will soon be replaced by a submodule.
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv b/corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv
new file mode 100644
index 0000000000..fefb0053a6
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv
@@ -0,0 +1,187 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+// uncomment to enable 64bits arch support
+// `define TE_ARCH64
+
+package te_pkg;
+ localparam PRIV_LEN = 2; // depends on CPU implementation
+ localparam INST_LEN = 32;
+ localparam PTYPE_LEN = 4; // is it F + SF? spec not clear
+ localparam P_LEN = 5;
+ localparam PAYLOAD_LEN = 248;
+ localparam TRIGGER_LEN = 4;
+ localparam CTYPE_LEN = 2;
+`ifdef TE_ARCH64 // 64bit arch specific parameters
+ localparam XLEN = 64;
+ // APB addresses to access registers
+ // the value is added to the peripheral address
+ /* FILTER */
+ // cause
+ localparam CAUSE_UPPER = 8'h5;
+ localparam CAUSE_LOWER = 8'h6;
+ localparam CAUSE_MATCH = 8'h7;
+ // tvec
+ localparam TVEC_UPPER_L = 8'h8; // least significant bits
+ localparam TVEC_UPPER_M = 8'h9; // most significant bits
+ localparam TVEC_LOWER_L = 8'ha; // least significant bits
+ localparam TVEC_LOWER_M = 8'hb; // most significant bits
+ localparam TVEC_MATCH_L = 8'hc; // least significant bits
+ localparam TVEC_MATCH_M = 8'hd; // most significant bits
+ // tval
+ localparam TVAL_UPPER_L = 8'he; // least significant bits
+ localparam TVAL_UPPER_M = 8'hf; // most significant bits
+ localparam TVAL_LOWER_L = 8'h10; // least significant bits
+ localparam TVAL_LOWER_M = 8'h11; // most significant bits
+ localparam TVAL_MATCH_L = 8'h12; // least significant bits
+ localparam TVAL_MATCH_M = 8'h13; // most significant bits
+ // iaddr
+ localparam IADDR_UPPER_L = 8'h16; // least significant bits
+ localparam IADDR_UPPER_M = 8'h17; // most significant bits
+ localparam IADDR_LOWER_L = 8'h18; // least significant bits
+ localparam IADDR_LOWER_M = 8'h19; // most significant bits
+ localparam IADDR_MATCH_L = 8'h1a; // least significant bits
+ localparam IADDR_MATCH_M = 8'h1b; // most significant bits
+`else // 32bit arch
+ localparam XLEN = 32;
+ // APB addresses to access registers
+ // APB addresses to access registers
+ // the value is added to the peripheral address
+ /* FILTER */
+ // cause
+ localparam CAUSE_UPPER = 8'h5;
+ localparam CAUSE_LOWER = 8'h6;
+ localparam CAUSE_MATCH = 8'h7;
+ // tvec
+ localparam TVEC_UPPER = 8'h8;
+ localparam TVEC_LOWER = 8'ha;
+ localparam TVEC_MATCH = 8'hc;
+ // tval
+ localparam TVAL_UPPER = 8'he;
+ localparam TVAL_LOWER = 8'h10;
+ localparam TVAL_MATCH = 8'h12;
+ // iaddr
+ localparam IADDR_UPPER = 8'h16;
+ localparam IADDR_LOWER = 8'h18;
+ localparam IADDR_MATCH = 8'h1a;
+`endif
+ /* both archs parameters */
+ // localparams for resync counter
+ localparam CYCLE_MODE = 0;
+ localparam PACKET_MODE = 1;
+ // localparams for irreport and irdepth
+ localparam CALL_COUNTER_SIZE = '0;
+ localparam RETURN_STACK_SIZE = '0;
+ // localparams for branch map - defined by spec
+ localparam BRANCH_MAP_LEN = 31;
+ localparam BRANCH_COUNT_LEN = 5;
+ // localparams for filter mode
+ localparam RANGE_MODE = 1'b0;
+ localparam EQUAL_MODE = 1'b1;
+ // localparam for time signal
+ localparam TIME_LEN = 64;
+ // localparam for itype
+ localparam ITYPE_LEN = 3;
+ // localparam for iretire
+ localparam IRETIRE_LEN = 32;
+
+ // common APB addresses to access registers
+ /* FILTER */
+ // input and mode
+ localparam CAUSE_ENABLE_MODE = 8'h0;
+ localparam TVEC_ENABLE_MODE = 8'h1;
+ localparam TVAL_ENABLE_MODE = 8'h2;
+ localparam PRIV_ENABLE_MODE = 8'h3;
+ localparam IADDR_ENABLE_MODE = 8'h4;
+ // priv
+ localparam PRIV_RANGE = 8'h14;
+ localparam PRIV_MATCH = 8'h15;
+ /* TRACE MANAGEMENT */
+ localparam TRACE_STATE = 8'h1c;
+ localparam LOSSLESS_TRACE = 8'h1d;
+ localparam SHALLOW_TRACE = 8'h1e;
+ /* PACKET EMITTER */
+ localparam NO_TIME = 8'h1f;
+ localparam NO_CONTEXT = 8'h20;
+ localparam DELTA_ADDRESS = 8'h21;
+ localparam FULL_ADDRESS = 8'h22;
+ localparam IMPLICIT_EXCEPTION = 8'h23;
+ localparam SIJUMP = 8'h24;
+ localparam IMPLICIT_RETURN = 8'h25;
+ localparam BRANCH_PREDICTION = 8'h26;
+ localparam JUMP_TARGET_CACHE = 8'h27;
+
+// packet types
+typedef enum logic[1:0] {
+ F_OPT_EXT = 2'h0,
+ F_DIFF_DELTA = 2'h1,
+ F_ADDR_ONLY = 2'h2,
+ F_SYNC = 2'h3
+} format_e;
+
+// subformats available for type 3 packets (F_SYNC)
+typedef enum logic[1:0] {
+ SF_START = 2'h0,
+ SF_TRAP = 2'h1,
+ SF_CONTEXT = 2'h2,
+ SF_SUPPORT = 2'h3
+} f_sync_subformat_e;
+
+// subformats available for type 0 packets (F_OPT_EXT)
+// used a struct for future extensions
+typedef enum logic[0:0] {
+ SF_PBC = 1'h0, // correctly predicted branches
+ SF_JTC = 1'h1 // jump target cache in spec
+} f_opt_ext_subformat_e;
+
+// qual_status values necessary for format 3 subformat 3
+// packet payload
+typedef enum logic[1:0] {
+ NO_CHANGE = 2'h0,
+ ENDED_REP = 2'h1,
+ TRACE_LOST = 2'h2,
+ ENDED_NTR = 2'h3
+} qual_status_e;
+
+// struct to determine the ioptions enabled/disabled
+// for format 3 subformat 3 packets
+typedef struct packed {
+ logic delta_address_en;
+ logic full_address_en;
+ logic implicit_exception_en;
+ logic sijump_en;
+ logic implicit_return_en;
+ logic branch_prediction_en;
+ logic jump_target_cache_en;
+} ioptions_s;
+
+// enum that expresses the packet format and
+// subformat to better readability
+typedef enum logic[3:0] {
+ F0SF0 = 4'h0,
+ F0SF1 = 4'h1,
+ F1 = 4'h4,
+ F2 = 4'h8,
+ F3SF0 = 4'hC,
+ F3SF1 = 4'hD,
+ F3SF2 = 4'hE,
+ F3SF3 = 4'hF
+} it_packet_type_e; // "it" stands for "instruction trace"
+
+/*TODO:
+ doptions struct for data tracing
+ refer to page 36 of the spec */
+
+endpackage
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv
new file mode 100644
index 0000000000..f28730ac7f
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv
@@ -0,0 +1,106 @@
+// Copyright 2018 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+
+// `include "common_cells/assertions.svh"
+
+/// A trailing zero counter / leading zero counter.
+/// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB)
+/// Set MODE to 1 for leading zero counter => cnt_o is the number of leading zeros (from the MSB)
+/// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains
+/// the maximum number of zeros - 1. For example:
+/// in_i = 000_0000, empty_o = 1, cnt_o = 6 (mode = 0)
+/// in_i = 000_0001, empty_o = 0, cnt_o = 0 (mode = 0)
+/// in_i = 000_1000, empty_o = 0, cnt_o = 3 (mode = 0)
+/// Furthermore, this unit contains a more efficient implementation for Verilator (simulation only).
+/// This speeds up simulation significantly.
+module lzc #(
+ /// The width of the input vector.
+ parameter int unsigned WIDTH = 2,
+ /// Mode selection: 0 -> trailing zero, 1 -> leading zero
+ parameter bit MODE = 1'b0,
+ /// Dependent parameter. Do **not** change!
+ ///
+ /// Width of the output signal with the zero count.
+ parameter int unsigned CNT_WIDTH = cf_math_pkg::idx_width(WIDTH)
+) (
+ /// Input vector to be counted.
+ input logic [WIDTH-1:0] in_i,
+ /// Count of the leading / trailing zeros.
+ output logic [CNT_WIDTH-1:0] cnt_o,
+ /// Counter is empty: Asserted if all bits in in_i are zero.
+ output logic empty_o
+);
+
+ if (WIDTH == 1) begin : gen_degenerate_lzc
+
+ assign cnt_o[0] = !in_i[0];
+ assign empty_o = !in_i[0];
+
+ end else begin : gen_lzc
+
+ localparam int unsigned NumLevels = $clog2(WIDTH);
+
+ // `ifndef COMMON_CELLS_ASSERTS_OFF
+ // `ASSERT_INIT(width_0, WIDTH > 0, "input must be at least one bit wide")
+ // `endif
+
+ logic [WIDTH-1:0][NumLevels-1:0] index_lut;
+ logic [2**NumLevels-1:0] sel_nodes;
+ logic [2**NumLevels-1:0][NumLevels-1:0] index_nodes;
+
+ logic [WIDTH-1:0] in_tmp;
+
+ // reverse vector if required
+ always_comb begin : flip_vector
+ for (int unsigned i = 0; i < WIDTH; i++) begin
+ in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i];
+ end
+ end
+
+ for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut
+ assign index_lut[j] = (NumLevels)'(unsigned'(j));
+ end
+
+ for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : g_levels
+ if (unsigned'(level) == NumLevels - 1) begin : g_last_level
+ for (genvar k = 0; k < 2 ** level; k++) begin : g_level
+ // if two successive indices are still in the vector...
+ if (unsigned'(k) * 2 < WIDTH - 1) begin : g_reduce
+ assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2] | in_tmp[k * 2 + 1];
+ assign index_nodes[2 ** level - 1 + k] = (in_tmp[k * 2] == 1'b1)
+ ? index_lut[k * 2] :
+ index_lut[k * 2 + 1];
+ end
+ // if only the first index is still in the vector...
+ if (unsigned'(k) * 2 == WIDTH - 1) begin : g_base
+ assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2];
+ assign index_nodes[2 ** level - 1 + k] = index_lut[k * 2];
+ end
+ // if index is out of range
+ if (unsigned'(k) * 2 > WIDTH - 1) begin : g_out_of_range
+ assign sel_nodes[2 ** level - 1 + k] = 1'b0;
+ assign index_nodes[2 ** level - 1 + k] = '0;
+ end
+ end
+ end else begin : g_not_last_level
+ for (genvar l = 0; l < 2 ** level; l++) begin : g_level
+ assign sel_nodes[2 ** level - 1 + l] =
+ sel_nodes[2 ** (level + 1) - 1 + l * 2] | sel_nodes[2 ** (level + 1) - 1 + l * 2 + 1];
+ assign index_nodes[2 ** level - 1 + l] = (sel_nodes[2 ** (level + 1) - 1 + l * 2] == 1'b1)
+ ? index_nodes[2 ** (level + 1) - 1 + l * 2] :
+ index_nodes[2 ** (level + 1) - 1 + l * 2 + 1];
+ end
+ end
+ end
+
+ assign cnt_o = NumLevels > unsigned'(0) ? index_nodes[0] : {($clog2(WIDTH)) {1'b0}};
+ assign empty_o = NumLevels > unsigned'(0) ? ~sel_nodes[0] : ~(|in_i);
+
+ end : gen_lzc
+
+// `ifndef COMMON_CELLS_ASSERTS_OFF
+// `ASSERT_INIT(width_0, WIDTH >= 1, "The WIDTH must at least be one bit wide!")
+// `endif
+
+endmodule : lzc
diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv
new file mode 100644
index 0000000000..c920c876a2
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv
@@ -0,0 +1,911 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/* TOP LEVEL MODULE */
+
+module rv_tracer #(
+ //parameter IRETIRE_LEN = 32, // set to 1 for single retirement
+ parameter N = 1, // max number of special inst retired in a cycle, the input port number depends on this value
+ parameter ONLY_BRANCHES = 0, // special inst are branches or not
+ parameter APB_ADDR_WIDTH = 32 // address width for APB interface
+)
+(
+ input logic clk_i,
+ input logic rst_ni,
+
+ input logic [N-1:0] valid_i, // used for multiple retirement
+
+ /* data from the CPU */
+ // mandatory inputs
+ input logic [N-1:0][te_pkg::ITYPE_LEN-1:0] itype_i, // termination type of block
+ input logic [te_pkg::XLEN-1:0] cause_i,
+ input logic [te_pkg::XLEN-1:0] tval_i,
+ input logic [te_pkg::PRIV_LEN-1:0] priv_i,
+ input logic [N-1:0][te_pkg::XLEN-1:0] iaddr_i, // pc of 1st inst in block
+ input logic [N-1:0][te_pkg::IRETIRE_LEN-1:0] iretire_i, // length of block in halfwords
+ input logic [N-1:0] ilastsize_i, // length of last inst in 2^ilastsize halfword
+ // non mandatory inputs
+ input logic [te_pkg::TIME_LEN-1:0] time_i,
+ //input logic [:0] context_i,
+ //input logic [te_pkg::CTYPE_LEN-1:0] ctype_i, // spec says it's 1 or 2 bit wide
+ //input logic [te_pkg::TRIGGER_LEN-1:0] trigger_i, // must be supported CPU side
+
+ // support inputs
+ input logic [te_pkg::XLEN-1:0] tvec_i, // tvec_q, contains trap handler address
+ input logic [te_pkg::XLEN-1:0] epc_i, // epc_q, required for format 3 subformat 1
+ input logic encapsulator_ready_i, // non mandatory
+
+ // APB interface inputs
+ input logic [APB_ADDR_WIDTH-1:0] paddr_i,
+ input logic pwrite_i,
+ input logic psel_i,
+ input logic penable_i,
+ input logic [31:0] pwdata_i,
+
+ // outputs
+ // info needed for the encapsulator
+ output logic [N-1:0] packet_valid_o,
+ output te_pkg::it_packet_type_e [N-1:0] packet_type_o,
+ output logic [N-1:0][te_pkg::P_LEN-1:0] packet_length_o, // in bytes
+ output logic [N-1:0][te_pkg::PAYLOAD_LEN-1:0] packet_payload_o,
+ // sideband signals
+ output logic stall_o,
+
+ // APB interface outputs
+ output logic pready_o,
+ output logic [31:0] prdata_o
+);
+
+ /* signals for management */
+ // registers
+ logic trace_activated;
+ logic trace_enable;
+ logic nocontext;
+ logic notime;
+ logic encoder_mode;
+ // filter
+ logic trigger_trace_on; // hardwired to 0?
+ logic trigger_trace_off; // hardwired to 0?
+ //logic qualified; // is it needed or I can use qualified_d?
+ logic trace_req_deactivate;
+ // priority
+ te_pkg::format_e packet_format[N-1:0];
+ te_pkg::f_sync_subformat_e packet_f_sync_subformat[N-1:0];
+ te_pkg::f_opt_ext_subformat_e packet_f_opt_ext_subformat[N-1:0];
+ logic thaddr[N-1:0];
+ logic lc_tc_mux[N-1:0];
+ te_pkg::qual_status_e qual_status[N-1:0];
+ logic nc_branch_map_flush;
+ logic [te_pkg::BRANCH_MAP_LEN-1:0] branch_map;
+ logic [te_pkg::BRANCH_COUNT_LEN-1:0] branch_count;
+ logic resync_rst;
+ // packet emitter
+ logic packet_valid[N-1:0];
+ // resync counter
+ logic [N-1:0] packet_emitted;
+ // not classified
+ logic nc_branch_map_empty;
+ logic clk_gated;
+ logic turn_on_tracer_d, turn_on_tracer_q;
+ logic lossless_trace;
+ logic shallow_trace;
+
+ // we have three phases, called last cycle (lc), this cycle (tc) and next
+ // cycle (nc), based on which we make decision whether we need to emit a
+ // packet or not.
+ logic tc_branch_map_empty;
+ logic [N-1:0] tc_resync;
+ logic [N-1:0] nc_exc_only;
+ logic [N-1:0] nc_ppccd_br;
+ logic [$clog2(te_pkg::XLEN):0] keep_bits[N-1:0];
+ logic [te_pkg::XLEN-1:0] addr_to_compress[N-1:0];
+
+ logic [1:0][N-1:0][te_pkg::IRETIRE_LEN-1:0] iretired_tab;
+ logic [2:0] exception_tab;
+ logic [2:0] interrupt_tab;
+ logic [2:0][te_pkg::XLEN-1:0] cause_tab;
+ logic [1:0][te_pkg::XLEN-1:0] tvec_tab;
+ logic [2:0][te_pkg::XLEN-1:0] tval_tab;
+ logic [1:0][N-1:0][te_pkg::ITYPE_LEN-1:0] itype_tab;
+ logic [1:0][te_pkg::PRIV_LEN-1:0] priv_tab;
+ logic [1:0][N-1:0][te_pkg::XLEN-1:0] address_tab;
+ logic [2:0][te_pkg::XLEN-1:0] epc_tab;
+ logic [1:0][te_pkg::TIME_LEN-1:0] time_tab;
+ logic [2:0][N-1:0] updiscon_tab;
+ logic [2:0][N-1:0] qualified_tab;
+
+ logic [N-1:0][te_pkg::IRETIRE_LEN-1:0] tc_iretired, nc_iretired;
+ logic lc_exception, tc_exception, nc_exception;
+ logic lc_interrupt, tc_interrupt, nc_interrupt;
+ logic [te_pkg::XLEN-1:0] lc_cause, tc_cause, nc_cause;
+ logic [te_pkg::XLEN-1:0] tc_tvec, nc_tvec;
+ logic [te_pkg::XLEN-1:0] lc_tval, tc_tval, nc_tval;
+ logic [N-1:0][te_pkg::ITYPE_LEN-1:0] tc_itype, nc_itype;
+ logic [te_pkg::PRIV_LEN-1:0] tc_priv, nc_priv;
+ logic [N-1:0][te_pkg::XLEN-1:0] tc_address, nc_address;
+ logic [te_pkg::XLEN-1:0] lc_epc, tc_epc, nc_epc;
+ logic [te_pkg::TIME_LEN-1:0] tc_time, nc_time;
+ logic [N-1:0] lc_updiscon, tc_updiscon, nc_updiscon;
+ logic [N-1:0] lc_qualified, tc_qualified, nc_qualified;
+
+
+ logic tc_first_qualified;
+ logic tc_final_qualified;
+ logic [N-1:0] updiscon;
+ logic [N-1:0][te_pkg::XLEN-1:0] address;
+ logic [N-1:0] qualified;
+
+
+ logic [N-1:0] valid0_d, valid0_q;
+ logic privchange_d, privchange_q;
+ // logic context_change_d, context_change_q; // non mandatory
+ // logic precise_context_report_d, precise_context_report_q; // requires ctype signal CPU side
+ // logic context_report_as_disc_d, context_report_as_disc_q; // ibidem
+ // logic no_context_report_d, no_context_report_q; // ibidem
+ // logic imprecise_context_report_d, imprecise_context_report_q; // ibidem
+ logic gt_max_resync_d, gt_max_resync_q;
+ logic et_max_resync_d, et_max_resync_q;
+ logic branch_map_full_d, branch_map_full_q;
+ //logic branch_misprediction_d, branch_misprediction_q; // non mandatory
+ logic trace_activated_d, trace_activated_q;
+ logic enc_activated_d, enc_activated_q;
+ logic enc_deactivated_d, enc_deactivated_q;
+ //logic packets_lost_d, packets_lost_q; // non mandatory
+ te_pkg::ioptions_s enc_config_d, enc_config_q;
+ logic enc_config_change_d, enc_config_change_q;
+ logic branch_d, branch_q;
+ logic branch_taken_d, branch_taken_q;
+
+ // branch_map inputs
+ logic [N-1:0] branch_valid;
+ logic [N-1:0] branch_taken;
+
+ // te_reg output to filter input
+ logic cause_filter;
+ logic [te_pkg::XLEN-1:0] upper_cause;
+ logic [te_pkg::XLEN-1:0] lower_cause;
+ logic [te_pkg::XLEN-1:0] match_cause;
+ logic cause_mode;
+ logic tvec_filter;
+ logic [te_pkg::XLEN-1:0] upper_tvec;
+ logic [te_pkg::XLEN-1:0] lower_tvec;
+ logic [te_pkg::XLEN-1:0] match_tvec;
+ logic tvec_mode;
+ logic tval_filter;
+ logic [te_pkg::XLEN-1:0] upper_tval;
+ logic [te_pkg::XLEN-1:0] lower_tval;
+ logic [te_pkg::XLEN-1:0] match_tval;
+ logic tval_mode;
+ logic priv_lvl_filter;
+ logic [te_pkg::PRIV_LEN-1:0] upper_priv;
+ logic [te_pkg::PRIV_LEN-1:0] lower_priv;
+ logic [te_pkg::PRIV_LEN-1:0] match_priv;
+ logic priv_lvl_mode;
+ logic iaddr_filter;
+ logic [te_pkg::XLEN-1:0] upper_iaddr;
+ logic [te_pkg::XLEN-1:0] lower_iaddr;
+ logic [te_pkg::XLEN-1:0] match_iaddr;
+ logic iaddr_mode;
+
+ /* the following commented section has non mandatory signals
+ for now it's commented
+ */
+ /* combinatorial network to define the following
+ signals from ctype:
+ - tc_no_context_report_i -> ctype == 0
+ - tc_precise_context_report_i -> ctype == 2
+ - tc_context_report_as_disc_i -> ctype == 3
+ - tc_imprecise_context_report_i -> ctype == 1
+ - nc_precise_context_report_i -> ctype == 2
+ - nc_context_report_as_disc_i -> ctype == 3*/
+ /*
+ always_comb begin : ctype_manager
+ case(ctype_i)
+ 2'h0: // no report - add signal
+ tc_no_context_report = '1;
+ 2'h1:
+ tc_imprecise_context_report = '1;
+ 2'h2:
+ tc_precise_context_report = '1;
+ 2'h3:
+ tc_context_report_as_disc = '1;
+ endcase
+ end
+ */
+
+ /*TODO: create a trigger decoder that produces:
+ - trigger_trace_on -> 2
+ - trigger_trace_off -> 3
+ - trigger_notify -> 4
+ */
+ // maybe it's enough to define values and hardwire them to 0
+
+ /* ASSIGNMENT */
+ /* hardwired assignments */
+ assign trigger_trace_on = '0;
+ assign trigger_trace_off = '0;
+
+ /* FFs inputs */
+ assign valid0_d = valid_i;
+ assign trace_activated_d = trace_activated;
+ assign enc_activated_d = trace_activated_d && ~trace_activated_q;
+ assign enc_deactivated_d = ~trace_activated_d && trace_activated_q;
+ assign enc_config_change_d = enc_config_d != enc_config_q;
+
+ /* next cycle */
+ assign nc_branch_map_empty = nc_branch_map_flush || (tc_branch_map_empty /*&& ~branch_q*/);
+
+ // output
+ assign packet_valid_o = packet_emitted;
+ // sideband
+ assign stall_o = ~encapsulator_ready_i && lossless_trace;
+
+ // other
+ assign branch_taken_d = |branch_taken;
+
+ // first and final qualified
+ assign tc_first_qualified = trace_activated && |tc_qualified && !lc_qualified && trace_enable;
+ assign tc_final_qualified = trace_activated && |lc_qualified && !tc_qualified && trace_enable;
+
+ always_ff @( posedge clk_i, negedge rst_ni ) begin
+ if(~rst_ni) begin
+ iretired_tab <= '0;
+ exception_tab <= '0;
+ interrupt_tab <= '0;
+ cause_tab <= '0;
+ tvec_tab <= '0;
+ tval_tab <= '0;
+ itype_tab <= '0;
+ priv_tab <= '0;
+ address_tab <= '0;
+ epc_tab <= '0;
+ time_tab <= '0;
+ updiscon_tab <= '0;
+ qualified_tab <= '0;
+ end else begin
+ if (|valid_i) begin
+ iretired_tab <= {iretired_tab[0], iretire_i};
+ exception_tab <= {exception_tab[1:0], itype_i[0] == 1};
+ interrupt_tab <= {interrupt_tab[1:0], itype_i[0] == 2};
+ cause_tab <= {cause_tab[1:0],cause_i};
+ tvec_tab <= {tvec_tab[0], tvec_i};
+ tval_tab <= {tval_tab [1:0], tval_i};
+ itype_tab <= {itype_tab[0], itype_i};
+ priv_tab <= {priv_tab[0], priv_i};
+ address_tab <= {address_tab[0], address};
+ epc_tab <= {epc_tab[1:0], epc_i};
+ time_tab <= {time_tab[0], time_i};
+ updiscon_tab <= {updiscon_tab[1:0], updiscon};
+ qualified_tab <={qualified_tab[1:0], qualified};
+ end
+ end
+
+ end
+ //lc asignements
+ assign lc_exception = exception_tab[2];
+ assign lc_interrupt = interrupt_tab[2];
+ assign lc_cause = cause_tab[2];
+ assign lc_tval = tval_tab[2];
+ assign lc_epc = epc_tab[2];
+ assign lc_updiscon = updiscon_tab[2];
+ assign lc_qualified = qualified_tab[2];
+ // tc assignements
+ assign tc_iretired = iretired_tab[1];
+ assign tc_exception = exception_tab[1];
+ assign tc_interrupt = interrupt_tab[1];
+ assign tc_cause= cause_tab[1];
+ assign tc_tvec = tvec_tab[1];
+ assign tc_tval = tval_tab[1];
+ assign tc_itype = itype_tab[1];
+ assign tc_priv = priv_tab[1];
+ assign tc_address = address_tab[1];
+ assign tc_epc = epc_tab[1];
+ assign tc_time = time_tab[1];
+ assign tc_updiscon = updiscon_tab[1];
+ assign tc_qualified = qualified_tab[1];
+
+ // nc assignements
+ assign nc_iretired = iretired_tab[0];
+ assign nc_exception = exception_tab[0];
+ assign nc_interrupt = interrupt_tab[0];
+ assign nc_cause= cause_tab[0];
+ assign nc_tvec = tvec_tab[0];
+ assign nc_tval = tval_tab[0];
+ assign nc_itype = itype_tab[0];
+ assign nc_priv = priv_tab[0];
+ assign nc_address = address_tab[0];
+ assign nc_epc = epc_tab[0];
+ assign nc_time = time_tab[0];
+ assign nc_updiscon = updiscon_tab[0];
+ assign nc_qualified = qualified_tab[0];
+
+ //FIXME need cleaning
+ // not static assignments
+ always_comb begin
+ // init
+ branch_valid = '0;
+ branch_taken = '0;
+
+ privchange_d = privchange_q;
+ // context_change_d = context_change_q;
+ // precise_context_report_d = precise_context_report_q; // requires ctype signal CPU side
+ // context_report_as_disc_d = context_report_as_disc_q; //ibidem
+ // no_context_report_d = no_context_report_q; // ibidem
+ // imprecise_context_report_d = imprecise_context_report_q; // ibidem
+ branch_d = branch_q;
+
+ // itype, iretired and address
+ // it works for all three cases
+ for (int i = 0; i < N; i++) begin
+ if (valid_i[i]) begin
+ address[i] = iaddr_i[i];
+ //FIXME we remove block reconstruction address
+ //address[i] = iaddr_i[i]+2*(iretire_i[i] - 2**ilastsize_i[i]);
+ end
+ end
+ //FIXME weird timing here nc for erveryone ?
+ // assigning branch map inputs
+ for (int i = 0; i < N; i++) begin
+ if (nc_itype[i] == 4 || nc_itype[i] == 5) begin
+ branch_valid[i] = '1;
+ end
+ if (nc_itype[i] == 5) begin
+ branch_taken[i] = '1;
+ end
+ end
+
+ // updiscon
+ if (N == 1 || (N > 1 && ONLY_BRANCHES)) begin
+ if (qualified[0]) begin
+ updiscon[0] = itype_i[0] == 6;
+ end
+ end
+ // wait for this case
+ if (N > 1 && !ONLY_BRANCHES) begin
+ for (int i = 0; i < N; i++) begin
+ if (qualified[i]) begin
+ updiscon[i] = itype_i[i] == 6;
+ end
+ end
+ end
+
+ // updating registers values
+ if (|valid_i) begin
+ privchange_d = (nc_priv != tc_priv) && |valid_i;
+ // context_change_d; // TODO
+ //precise_context_report_d; // requires ctype signal CPU side
+ //context_report_as_disc_d; //ibidem
+ //no_context_report_d; // ibidem
+ //imprecise_context_report_d; // ibidem
+ branch_d = |branch_valid;
+ end
+
+ if (!turn_on_tracer_q) begin
+ turn_on_tracer_d = |valid_i && nc_qualified;
+ end
+ end
+
+ /* MODULES INSTANTIATION */
+ // one instance for all 3 cases
+
+
+ /* MAPPED REGISTERS */
+ te_reg #(
+ .APB_ADDR_WIDTH(APB_ADDR_WIDTH)
+ ) i_te_reg(
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .trace_req_off_i ('0),
+ .trace_req_on_i (turn_on_tracer_q), // trigger_trace_on // from trigger unit
+ .encapsulator_ready_i(encapsulator_ready_i),
+ .cause_filter_o (cause_filter),
+ .upper_cause_o (upper_cause),
+ .lower_cause_o (lower_cause),
+ .match_cause_o (match_cause),
+ .cause_mode_o (cause_mode),
+ .tvec_filter_o (tvec_filter),
+ .upper_tvec_o (upper_tvec),
+ .lower_tvec_o (lower_tvec),
+ .match_tvec_o (match_tvec),
+ .tvec_mode_o (tvec_mode),
+ .tval_filter_o (tval_filter),
+ .upper_tval_o (upper_tval),
+ .lower_tval_o (lower_tval),
+ .match_tval_o (match_tval),
+ .tval_mode_o (tval_mode),
+ .priv_lvl_filter_o (priv_lvl_filter),
+ .upper_priv_o (upper_priv),
+ .lower_priv_o (lower_priv),
+ .match_priv_o (match_priv),
+ .priv_lvl_mode_o (priv_lvl_mode),
+ .iaddr_filter_o (iaddr_filter),
+ .upper_iaddr_o (upper_iaddr),
+ .lower_iaddr_o (lower_iaddr),
+ .match_iaddr_o (match_iaddr),
+ .iaddr_mode_o (iaddr_mode),
+ .trace_enable_o (trace_enable),
+ .trace_activated_o (trace_activated),
+ .nocontext_o (nocontext),
+ .notime_o (notime),
+ .encoder_mode_o (encoder_mode),
+ .configuration_o (enc_config_d),
+ .lossless_trace_o (lossless_trace),
+ .shallow_trace_o (shallow_trace),
+ .clk_gated_o (clk_gated),
+ .paddr_i (paddr_i),
+ .pwrite_i (pwrite_i),
+ .psel_i (psel_i),
+ .penable_i (penable_i),
+ .pwdata_i (pwdata_i),
+ .pready_o (pready_o),
+ .prdata_o (prdata_o)
+ );
+
+ /* BRANCH MAP */
+ te_branch_map #(
+ .N(N)
+ ) i_te_branch_map(
+ .clk_i (clk_gated),
+ .rst_ni (rst_ni),
+ .valid_i (branch_valid & nc_qualified & valid0_q),
+ .branch_taken_i(branch_taken),
+ .flush_i (nc_branch_map_flush),
+ //.branch_taken_prediction_i(), // non mandatory
+ .map_o (branch_map),
+ .branches_o (branch_count),
+ //.pbc_o(), // non mandatory - branch prediction mode
+ //.misprediction_o(), // non mandatory - ibidem
+ .is_full_o (branch_map_full_d),
+ .is_empty_o (tc_branch_map_empty)
+ );
+
+ /* RESYNC COUNTER */
+ te_resync_counter #(
+ .N(N),
+ .MODE(te_pkg::CYCLE_MODE), // count cycles
+ .MAX_VALUE(13'h1FFF) // 8192
+ ) i_te_resync_counter( // for testing we keep the def settings
+ .clk_i (clk_gated),
+ .rst_ni (rst_ni),
+ .trace_enabled_i (trace_enable),
+ .packet_emitted_i(packet_emitted),
+ .resync_rst_i (resync_rst),
+ .gt_resync_max_o (gt_max_resync_d),
+ .et_resync_max_o (et_max_resync_d)
+ );
+
+ // N instances for all 3 cases
+
+ /* FILTER */
+ generate
+ if (ONLY_BRANCHES) begin
+ for (genvar i = 0; i < N; i++) begin
+ te_filter i_te_filter(
+ .trace_enable_i (trace_enable || trace_activated), // tracks 1st branch if 1st inst
+ .cause_filter_i (cause_filter),
+ .upper_cause_i (upper_cause),
+ .lower_cause_i (lower_cause),
+ .match_cause_i (match_cause),
+ .cause_mode_i (cause_mode),
+ .cause_i (cause_i),
+ .tvec_filter_i (tvec_filter),
+ .upper_tvec_i (upper_tvec),
+ .lower_tvec_i (lower_tvec),
+ .match_tvec_i (match_tvec),
+ .tvec_mode_i (tvec_mode),
+ .tvec_i (tvec_i),
+ .tval_filter_i (tval_filter),
+ .upper_tval_i (upper_tval),
+ .lower_tval_i (lower_tval),
+ .match_tval_i (match_tval),
+ .tval_mode_i (tval_mode),
+ .tval_i (tval_i),
+ .priv_lvl_filter_i(priv_lvl_filter),
+ .upper_priv_i (upper_priv),
+ .lower_priv_i (lower_priv),
+ .match_priv_i (match_priv),
+ .priv_lvl_mode_i (priv_lvl_mode),
+ .priv_i (priv_i),
+ .iaddr_filter_i (iaddr_filter),
+ .upper_iaddr_i (upper_iaddr),
+ .lower_iaddr_i (lower_iaddr),
+ .match_iaddr_i (match_iaddr),
+ .iaddr_mode_i (iaddr_mode),
+ .iaddr_i (iaddr_i[i]),
+ .nc_qualified_o (qualified[i])
+ );
+ end
+ end
+ endgenerate
+
+ /* PRIORITY, PACKET EMITTER*/
+ // case dependant
+ generate
+ // 1 instance for N == 1 || (N > 1 && ONLY_BRANCHES)
+ if (N == 1 || (N > 1 && ONLY_BRANCHES)) begin
+ /* PRIORITY */
+ te_priority i_te_priority(
+ .clk_i (clk_gated),
+ .rst_ni (rst_ni),
+ .valid_i (valid0_q[0] || (enc_activated_q || enc_deactivated_q)), // necessary to generate F3SF3 packet
+ .lc_exception_i (lc_exception || lc_interrupt),
+ .lc_updiscon_i (lc_updiscon),
+ .tc_qualified_i (tc_qualified[0]),
+ .tc_exception_i (tc_exception|| tc_interrupt),
+ .tc_retired_i (tc_iretired[0]),
+ .tc_first_qualified_i (tc_first_qualified),
+ .tc_privchange_i (privchange_q),
+ //.tc_context_change_i(), // non mandatory
+ //.tc_precise_context_report_i(), // requires ctype signal CPU side
+ //.tc_context_report_as_disc_i(), // ibidem
+ //.tc_imprecise_context_report_i(), // ibidem
+ .tc_gt_max_resync_i (gt_max_resync_q),
+ .tc_et_max_resync_i (et_max_resync_q),
+ .tc_branch_map_empty_i (tc_branch_map_empty),
+ .tc_branch_map_full_i (branch_map_full_d),
+ //.tc_branch_misprediction_i(), // non mandatory
+ //.tc_pbc_i(), // non mandatory
+ .tc_enc_enabled_i (enc_activated_q),
+ .tc_enc_disabled_i (enc_deactivated_q),
+ .tc_opmode_change_i (enc_config_change_q),
+ .tc_final_qualified_i (tc_final_qualified),
+ .tc_packets_lost_i (~encapsulator_ready_i), // non mandatory
+ .nc_exception_i (nc_exception || nc_interrupt),
+ .nc_privchange_i (privchange_d),
+ //.nc_context_change_i(),
+ //.nc_precise_context_report_i(), // requires ctype signal CPU side
+ //.nc_context_report_as_disc_i(), // ibidem
+ .nc_branch_map_empty_i (nc_branch_map_empty),
+ .nc_qualified_i (nc_qualified[0]),
+ .nc_retired_i (nc_iretired[0]),
+ //.halted_i(), // non mandatory side band signal
+ //.reset_i(), // ibidem
+ //.implicit_return_i(), // non mandatory
+ //.tc_trigger_req_i(), // non mandatory
+ //.notify_o(), // non mandatory, depends on trigger request
+ .addr_to_compress_i (addr_to_compress[0]),
+ .valid_o (packet_valid[0]),
+ .packet_format_o (packet_format[0]),
+ .packet_f_sync_subformat_o(packet_f_sync_subformat[0]),
+ //.packet_f_opt_ext_subformat_o(packet_f_opt_ext_subformat), // non mandatory
+ .thaddr_o (thaddr[0]),
+ .lc_tc_mux_o (lc_tc_mux[0]),
+ .resync_timer_rst_o (resync_rst),
+ .qual_status_o (qual_status[0]),
+ .tc_resync_o (tc_resync[0]),
+ .nc_exc_only_o (nc_exc_only[0]),
+ .nc_ppccd_br_o (nc_ppccd_br[0]),
+ .keep_bits_o (keep_bits[0])
+ );
+
+ /* PACKET EMITTER */
+ te_packet_emitter i_te_packet_emitter(
+ .clk_i (clk_gated),
+ .rst_ni (rst_ni),
+ .valid_i (packet_valid[0]),
+ .packet_format_i (packet_format[0]),
+ .packet_f_sync_subformat_i(packet_f_sync_subformat[0]),
+ //.packet_f_opt_ext_subformat_i(packet_f_opt_ext_subformat), // non mandatory
+ .lc_cause_i (lc_cause),
+ .lc_tval_i (lc_tval),
+ .lc_interrupt_i (lc_interrupt),
+ .tc_cause_i (tc_cause),
+ .tc_tval_i (tc_tval),
+ .tc_interrupt_i (tc_interrupt),
+ .tc_resync_i (tc_resync[0]),
+ .nc_exc_only_i (nc_exc_only[0]),
+ .nc_ppccd_br_i (nc_ppccd_br[0]),
+ .nocontext_i (nocontext),
+ .notime_i (notime),
+ .tc_branch_i (branch_q),
+ .tc_branch_taken_i (branch_taken_q),
+ .tc_priv_i (tc_priv),
+ .tc_time_i (tc_time), // non mandatory
+ //.context_i(), // non mandatory
+ .tc_address_i (tc_address[0]),
+ .lc_tc_mux_i (lc_tc_mux[0]),
+ .thaddr_i (thaddr[0]),
+ .tc_tvec_i (tc_tvec),
+ .lc_epc_i (lc_epc),
+ .tc_ienable_i (trace_enable),
+ .encoder_mode_i (encoder_mode),
+ .qual_status_i (qual_status[0]),
+ .ioptions_i (enc_config_q),
+ //.denable_i(), // stand-by
+ //.dloss_i(), //stand-by
+ //.notify_i(), // non mandatory
+ .lc_updiscon_i (lc_updiscon[0]),
+ //.irreport_i(), // non mandatory
+ //.irdepth_i(), // non mandatory
+ .branches_i (branch_count),
+ .branch_map_i (branch_map),
+ .keep_bits_i (keep_bits[0]),
+ .shallow_trace_i (shallow_trace),
+ .packet_valid_o (packet_emitted[0]),
+ .packet_type_o (packet_type_o[0]),
+ .packet_payload_o (packet_payload_o[0]),
+ .payload_length_o (packet_length_o[0]),
+ .branch_map_flush_o (nc_branch_map_flush),
+ .addr_to_compress_o (addr_to_compress[0])
+ );
+
+ end else if (N > 1 && !ONLY_BRANCHES) begin
+ // N instances for N > 1 && !ONLY_BRANCHES
+ for (genvar i = 0; i < N; i++) begin
+ if (i == 0) begin
+ /* PRIORITY */
+ te_priority i_te_priority(
+ .clk_i (clk_gated),
+ .rst_ni (rst_ni),
+ .valid_i (|valid0_q || (enc_activated_q || enc_deactivated_q)),
+ .lc_exception_i (lc_exception || lc_interrupt),
+ .lc_updiscon_i (lc_updiscon[i]),
+ .tc_qualified_i (tc_qualified[i]),
+ .tc_exception_i (tc_exception|| tc_interrupt),
+ .tc_retired_i (tc_iretired[i]),
+ .tc_first_qualified_i (tc_first_qualified),
+ .tc_privchange_i (privchange_q),
+ //.tc_context_change_i(), // non mandatory
+ //.tc_precise_context_report_i(), // requires ctype signal CPU side
+ //.tc_context_report_as_disc_i(), // ibidem
+ //.tc_imprecise_context_report_i(), // ibidem
+ .tc_gt_max_resync_i (gt_max_resync_q), // connected only to the first port
+ .tc_et_max_resync_i (et_max_resync_q), // connected only to the first port
+ .tc_branch_map_empty_i (tc_branch_map_empty),
+ .tc_branch_map_full_i (branch_map_full_q), // connected only to the first port
+ //.tc_branch_misprediction_i(), // non mandatory
+ //.tc_pbc_i(), // non mandatory
+ .tc_enc_enabled_i (enc_activated_q),
+ .tc_enc_disabled_i (enc_deactivated_q),
+ .tc_opmode_change_i (enc_config_change_q),
+ .tc_final_qualified_i (tc_final_qualified),
+ .tc_packets_lost_i (~encapsulator_ready_i), // non mandatory
+ .nc_exception_i (nc_exception || nc_interrupt),
+ .nc_privchange_i (privchange_d),
+ //.nc_context_change_i(),
+ //.nc_precise_context_report_i(), // requires ctype signal CPU side
+ //.nc_context_report_as_disc_i(), // ibidem
+ .nc_branch_map_empty_i (nc_branch_map_empty),
+ .nc_qualified_i (nc_qualified[i]),
+ .nc_retired_i (nc_iretired[i]),
+ //.halted_i(), // non mandatory side band signal
+ //.reset_i(), // ibidem
+ //.implicit_return_i(), // non mandatory
+ //.tc_trigger_req_i(), // non mandatory
+ //.notify_o(), // non mandatory, depends on trigger request
+ .addr_to_compress_i (addr_to_compress[i]),
+ .valid_o (packet_valid[i]),
+ .packet_format_o (packet_format[i]),
+ .packet_f_sync_subformat_o(packet_f_sync_subformat[i]),
+ //.packet_f_opt_ext_subformat_o(packet_f_opt_ext_subformat), // non mandatory
+ .thaddr_o (thaddr[i]),
+ .lc_tc_mux_o (lc_tc_mux[i]),
+ .resync_timer_rst_o (resync_rst),
+ .qual_status_o (qual_status[i]),
+ .tc_resync_o (tc_resync[i]),
+ .nc_exc_only_o (nc_exc_only[i]),
+ .nc_ppccd_br_o (nc_ppccd_br[i]),
+ .keep_bits_o (keep_bits[i])
+ );
+
+ /* PACKET EMITTER */
+ te_packet_emitter i_te_packet_emitter(
+ .clk_i (clk_gated),
+ .rst_ni (rst_ni),
+ .valid_i (packet_valid[i]),
+ .packet_format_i (packet_format[i]),
+ .packet_f_sync_subformat_i(packet_f_sync_subformat[i]),
+ //.packet_f_opt_ext_subformat_i(packet_f_opt_ext_subformat), // non mandatory
+ .lc_cause_i (lc_cause),
+ .lc_tval_i (lc_tval),
+ .lc_interrupt_i (lc_interrupt),
+ .tc_cause_i (tc_cause),
+ .tc_tval_i (tc_tval),
+ .tc_interrupt_i (tc_interrupt),
+ .tc_resync_i (tc_resync[i]),
+ .nc_exc_only_i (nc_exc_only[i]),
+ .nc_ppccd_br_i (nc_ppccd_br[i]),
+ .nocontext_i (nocontext),
+ .notime_i (notime),
+ .tc_branch_i (branch_q),
+ .tc_branch_taken_i (branch_taken_q),
+ .tc_priv_i (tc_priv),
+ .tc_time_i (tc_time), // non mandatory
+ //.context_i(), // non mandatory
+ .tc_address_i (tc_address[i]),
+ .lc_tc_mux_i (lc_tc_mux[i]),
+ .thaddr_i (thaddr[i]),
+ .tc_tvec_i (tc_tvec),
+ .lc_epc_i (lc_epc),
+ .tc_ienable_i (trace_enable),
+ .encoder_mode_i (encoder_mode),
+ .qual_status_i (qual_status[i]),
+ .ioptions_i (enc_config_q),
+ //.denable_i(), // stand-by
+ //.dloss_i(), //stand-by
+ //.notify_i(), // non mandatory
+ .lc_updiscon_i (lc_updiscon[i]),
+ //.irreport_i(), // non mandatory
+ //.irdepth_i(), // non mandatory
+ .branches_i (branch_count),
+ .branch_map_i (branch_map),
+ .keep_bits_i (keep_bits[i]),
+ .shallow_trace_i (shallow_trace),
+ .packet_valid_o (packet_emitted[i]),
+ .packet_type_o (packet_type_o[i]),
+ .packet_payload_o (packet_payload_o[i]),
+ .payload_length_o (packet_length_o[i]),
+ .branch_map_flush_o (nc_branch_map_flush),
+ .addr_to_compress_o (addr_to_compress[i])
+ );
+ end else begin
+ /* PRIORITY */
+ te_priority i_te_priority(
+ .clk_i (clk_gated),
+ .rst_ni (rst_ni),
+ .valid_i (|valid0_q || (enc_activated_q || enc_deactivated_q)),
+ .lc_exception_i (lc_exception || lc_interrupt),
+ .lc_updiscon_i (lc_updiscon[i]),
+ .tc_qualified_i (tc_qualified[i]),
+ .tc_exception_i (tc_exception || tc_interrupt),
+ .tc_retired_i (tc_iretired[i]),
+ .tc_first_qualified_i (tc_first_qualified),
+ .tc_privchange_i (privchange_q),
+ //.tc_context_change_i(), // non mandatory
+ //.tc_precise_context_report_i(), // requires ctype signal CPU side
+ //.tc_context_report_as_disc_i(), // ibidem
+ //.tc_imprecise_context_report_i(), // ibidem
+ .tc_gt_max_resync_i (), // connected only to the first port
+ .tc_et_max_resync_i (), // connected only to the first port
+ .tc_branch_map_empty_i (tc_branch_map_empty),
+ .tc_branch_map_full_i (), // connected only to the first port
+ //.tc_branch_misprediction_i(), // non mandatory
+ //.tc_pbc_i(), // non mandatory
+ .tc_enc_enabled_i (enc_activated_q),
+ .tc_enc_disabled_i (enc_deactivated_q),
+ .tc_opmode_change_i (enc_config_change_q),
+ .tc_final_qualified_i (tc_final_qualified),
+ .tc_packets_lost_i (~encapsulator_ready_i), // non mandatory
+ .nc_exception_i (nc_exception || nc_interrupt),
+ .nc_privchange_i (privchange_d),
+ //.nc_context_change_i(),
+ //.nc_precise_context_report_i(), // requires ctype signal CPU side
+ //.nc_context_report_as_disc_i(), // ibidem
+ .nc_branch_map_empty_i (nc_branch_map_empty),
+ .nc_qualified_i (nc_qualified[i]),
+ .nc_retired_i (nc_iretired[i]),
+ //.halted_i(), // non mandatory side band signal
+ //.reset_i(), // ibidem
+ //.implicit_return_i(), // non mandatory
+ //.tc_trigger_req_i(), // non mandatory
+ //.notify_o(), // non mandatory, depends on trigger request
+ .addr_to_compress_i (addr_to_compress[i]),
+ .valid_o (packet_valid[i]),
+ .packet_format_o (packet_format[i]),
+ .packet_f_sync_subformat_o(packet_f_sync_subformat[i]),
+ //.packet_f_opt_ext_subformat_o(packet_f_opt_ext_subformat), // non mandatory
+ .thaddr_o (thaddr[i]),
+ .lc_tc_mux_o (lc_tc_mux[i]),
+ .resync_timer_rst_o (), // connected only to the first port
+ .qual_status_o (qual_status[i]),
+ .tc_resync_o (tc_resync[i]),
+ .nc_exc_only_o (nc_exc_only[i]),
+ .nc_ppccd_br_o (nc_ppccd_br[i]),
+ .keep_bits_o (keep_bits[i])
+ );
+
+ /* PACKET EMITTER */
+ te_packet_emitter i_te_packet_emitter(
+ .clk_i (clk_gated),
+ .rst_ni (rst_ni),
+ .valid_i (packet_valid[i]),
+ .packet_format_i (packet_format[i]),
+ .packet_f_sync_subformat_i(packet_f_sync_subformat[i]),
+ //.packet_f_opt_ext_subformat_i(packet_f_opt_ext_subformat), // non mandatory
+ .lc_cause_i (lc_cause),
+ .lc_tval_i (lc_tval),
+ .lc_interrupt_i (lc_interrupt),
+ .tc_cause_i (tc_cause),
+ .tc_tval_i (tc_tval),
+ .tc_interrupt_i (tc_interrupt),
+ .tc_resync_i (tc_resync[i]),
+ .nc_exc_only_i (nc_exc_only[i]),
+ .nc_ppccd_br_i (nc_ppccd_br[i]),
+ .nocontext_i (nocontext),
+ .notime_i (notime),
+ .tc_branch_i (branch_q),
+ .tc_branch_taken_i (branch_taken_q),
+ .tc_priv_i (tc_priv),
+ .tc_time_i (tc_time), // non mandatory
+ //.context_i(), // non mandatory
+ .tc_address_i (tc_address[i]),
+ .lc_tc_mux_i (lc_tc_mux[i]),
+ .thaddr_i (thaddr[i]),
+ .tc_tvec_i (tc_tvec),
+ .lc_epc_i (lc_epc),
+ .tc_ienable_i (trace_enable),
+ .encoder_mode_i (encoder_mode),
+ .qual_status_i (qual_status[i]),
+ .ioptions_i (enc_config_q),
+ //.denable_i(), // stand-by
+ //.dloss_i(), //stand-by
+ //.notify_i(), // non mandatory
+ .lc_updiscon_i (lc_updiscon[i]),
+ //.irreport_i(), // non mandatory
+ //.irdepth_i(), // non mandatory
+ .branches_i (branch_count),
+ .branch_map_i (branch_map),
+ .keep_bits_i (keep_bits[i]),
+ .shallow_trace_i (shallow_trace),
+ .packet_valid_o (packet_emitted[i]),
+ .packet_type_o (packet_type_o[i]),
+ .packet_payload_o (packet_payload_o[i]),
+ .payload_length_o (packet_length_o[i]),
+ .branch_map_flush_o (), // connected only to the first port
+ .addr_to_compress_o (addr_to_compress[i])
+ );
+ end
+ end
+ end
+ endgenerate
+
+ /* REGISTERS MANAGEMENT */
+ always_ff @( posedge clk_i, negedge rst_ni ) begin : registers
+ if(~rst_ni) begin
+ valid0_q <= '0;
+ privchange_q <= '0;
+ // context_change_q <= '0;
+ //precise_context_report_q <= '0; // requires ctype signal CPU side
+ //context_report_as_disc_q <= '0; //ibidem
+ //no_context_report_q <= '0; // ibidem
+ //imprecise_context_report_q <= '0; // ibidem
+ gt_max_resync_q <= '0;
+ et_max_resync_q <= '0;
+ branch_map_full_q <= '0;
+ //branch_misprediction_q <= '0; // non mandatory
+ trace_activated_q <= '0;
+ enc_activated_q <= '0;
+ enc_deactivated_q <= '0;
+ //packets_lost_q <= '0; // non mandatory
+ enc_config_q <= te_pkg::DELTA_ADDRESS; // 3'b0
+ enc_config_change_q <= '0;
+ branch_taken_q <= '0;
+ branch_q <= '0;
+ turn_on_tracer_q <= '0;
+ end else begin
+ privchange_q <= privchange_d;
+ // context_change_q <= context_change_d;
+ //precise_context_report_q <= precise_context_report_d; // requires ctype signal CPU side
+ //context_report_as_disc_q <= context_report_as_disc_d; //ibidem
+ //no_context_report_q <= no_context_report_d; // ibidem
+ //imprecise_context_report_q <= imprecise_context_report_d; // ibidem
+ branch_q <= branch_d;
+ valid0_q <= valid0_d;
+ gt_max_resync_q <= gt_max_resync_d;
+ et_max_resync_q <= et_max_resync_d;
+ branch_map_full_q <= branch_map_full_d;
+ //branch_misprediction_q <= branch_misprediction_d; // non mandatory
+ trace_activated_q <= trace_activated_d;
+ enc_activated_q <= enc_activated_d;
+ enc_deactivated_q <= enc_deactivated_d;
+ //packets_lost_q <= packets_lost_d; // non mandatory
+ enc_config_q <= enc_config_d;
+ enc_config_change_q <= enc_config_change_d;
+ branch_taken_q <= branch_taken_d;
+ turn_on_tracer_q <= turn_on_tracer_d;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv
new file mode 100644
index 0000000000..c1e2f0fc8b
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv
@@ -0,0 +1,85 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/* BRANCH MAP */
+/*
+It keeps track of taken and non taken branches.
+
+Whenever a branch happens it updates the branch map
+and the number of branches stored.
+
+When flush_i signal is asserted, the branch map is
+cleaned.
+*/
+
+module te_branch_map #(
+ parameter N = 1 // max number of committed branches in one cycle
+)
+(
+ input logic clk_i,
+ input logic rst_ni,
+
+ input logic [N-1:0] valid_i,
+ input logic [N-1:0] branch_taken_i,
+ input logic flush_i,
+
+ output logic [te_pkg::BRANCH_MAP_LEN-1:0] map_o,
+ output logic [te_pkg::BRANCH_COUNT_LEN-1:0] branches_o,
+ output logic is_full_o,
+ output logic is_empty_o
+);
+
+
+ logic [te_pkg::BRANCH_MAP_LEN-1:0] map_d, map_q;
+ logic [te_pkg::BRANCH_COUNT_LEN-1:0] branch_cnt_d, branch_cnt_q;
+
+ always_comb begin
+ map_d = map_q;
+ branch_cnt_d = branch_cnt_q;
+
+ if (flush_i) begin
+ map_d = '0;
+ branch_cnt_d = '0;
+ end
+
+ if (valid_i) begin
+ if(flush_i) begin
+ map_d[0] = ~branch_taken_i;
+ branch_cnt_d = 5'b1;
+ end else begin
+ map_d[branch_cnt_q] = ~branch_taken_i ;
+ branch_cnt_d = branch_cnt_q +1;
+ end
+ end
+ end
+
+ assign map_o = map_d;
+ assign branches_o = branch_cnt_d;
+ assign is_full_o = (branch_cnt_d == 31);
+ assign is_empty_o = (branch_cnt_d == 0);
+
+
+ always_ff @(posedge clk_i, negedge rst_ni) begin
+ if(~rst_ni) begin
+ map_q <= '0;
+ branch_cnt_q <= '0;
+
+ end else begin
+ map_q <= map_d;
+ branch_cnt_q <= branch_cnt_d;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv
new file mode 100644
index 0000000000..6d33b7ebc5
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv
@@ -0,0 +1,142 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/* FILTER MODULE */
+/*
+it declares instructions qualified or not
+*/
+
+module te_filter
+(
+ // if trace isn't enabled it doesn't make sense to filter
+ input logic trace_enable_i,
+
+ /*
+ The idea is to have all inputs to be filtered in range or match.
+ To achieve this, the filter requires for each parameter:
+ - enable
+ - upper and lower values
+ - to be matched value
+ - select between in range or match
+ - qualified for each mode
+
+ The trace to be qualified according to the filters set it requires
+ an AND between the qualified of the parameters to filter.
+ */
+
+ // parameters to filter
+ // cause
+ input logic cause_filter_i,
+ input logic [te_pkg::XLEN-1:0] upper_cause_i,
+ input logic [te_pkg::XLEN-1:0] lower_cause_i,
+ input logic [te_pkg::XLEN-1:0] match_cause_i,
+ input logic cause_mode_i,
+ input logic [te_pkg::XLEN-1:0] cause_i,
+ // tvec
+ input logic tvec_filter_i,
+ input logic [te_pkg::XLEN-1:0] upper_tvec_i,
+ input logic [te_pkg::XLEN-1:0] lower_tvec_i,
+ input logic [te_pkg::XLEN-1:0] match_tvec_i,
+ input logic tvec_mode_i,
+ input logic [te_pkg::XLEN-1:0] tvec_i,
+ // tval
+ input logic tval_filter_i,
+ input logic [te_pkg::XLEN-1:0] upper_tval_i,
+ input logic [te_pkg::XLEN-1:0] lower_tval_i,
+ input logic [te_pkg::XLEN-1:0] match_tval_i,
+ input logic tval_mode_i,
+ input logic [te_pkg::XLEN-1:0] tval_i,
+ // priv_lvl
+ input logic priv_lvl_filter_i,
+ input logic [te_pkg::PRIV_LEN-1:0] upper_priv_i,
+ input logic [te_pkg::PRIV_LEN-1:0] lower_priv_i,
+ input logic [te_pkg::PRIV_LEN-1:0] match_priv_i,
+ input logic priv_lvl_mode_i,
+ input logic [te_pkg::PRIV_LEN-1:0] priv_i,
+ // iaddr (pc)
+ input logic iaddr_filter_i,
+ input logic [te_pkg::XLEN-1:0] upper_iaddr_i,
+ input logic [te_pkg::XLEN-1:0] lower_iaddr_i,
+ input logic [te_pkg::XLEN-1:0] match_iaddr_i,
+ input logic iaddr_mode_i,
+ input logic [te_pkg::XLEN-1:0] iaddr_i,
+
+ output logic nc_qualified_o
+);
+
+ // output signals for comparators
+ // cause
+ logic cause_in_range;
+ logic cause_equals;
+ // tvec
+ logic tvec_in_range;
+ logic tvec_equals;
+ // tval
+ logic tval_in_range;
+ logic tval_equals;
+ // priv_lvl
+ logic priv_lvl_in_range;
+ logic priv_lvl_equals;
+ // iaddr (pc)
+ logic iaddr_in_range;
+ logic iaddr_equals;
+
+ // assignments
+ // cause
+ assign cause_in_range = cause_mode_i == te_pkg::RANGE_MODE &&
+ cause_i <= upper_cause_i &&
+ cause_i >= lower_cause_i;
+ assign cause_equals = cause_mode_i == te_pkg::EQUAL_MODE &&
+ cause_i == match_cause_i;
+ // tvec
+ assign tvec_in_range = tvec_mode_i == te_pkg::RANGE_MODE &&
+ tvec_i <= upper_tvec_i &&
+ tvec_i >= lower_tvec_i;
+ assign tvec_equals = tvec_mode_i == te_pkg::EQUAL_MODE &&
+ tvec_i == match_tvec_i;
+ // tval
+ assign tval_in_range = tval_mode_i == te_pkg::RANGE_MODE &&
+ tval_i <= upper_tval_i &&
+ tval_i >= lower_tval_i;
+ assign tval_equals = tval_mode_i == te_pkg::EQUAL_MODE &&
+ tval_i == match_tval_i;
+ // priv_lvl
+ assign priv_lvl_in_range = priv_lvl_mode_i == te_pkg::RANGE_MODE &&
+ priv_i <= upper_priv_i &&
+ priv_i >= lower_priv_i;
+ assign priv_lvl_equals = priv_lvl_mode_i == te_pkg::EQUAL_MODE &&
+ priv_i == match_priv_i;
+ // iaddr
+ assign iaddr_in_range = iaddr_mode_i == te_pkg::RANGE_MODE &&
+ iaddr_i <= upper_iaddr_i &&
+ iaddr_i >= lower_iaddr_i;
+ assign iaddr_equals = iaddr_mode_i == te_pkg::EQUAL_MODE &&
+ iaddr_i == match_iaddr_i;
+
+ // assigning output
+ // if no filter is enabled -> the instruction is qualified
+ assign nc_qualified_o = ((cause_filter_i && (cause_in_range || cause_equals)) ||
+ ~cause_filter_i) && // cause
+ ((tvec_filter_i && (tvec_in_range || tvec_equals)) ||
+ ~tvec_filter_i) && // tvec
+ ((tval_filter_i && (tval_in_range || tval_equals)) ||
+ ~tval_filter_i) && // tval
+ ((priv_lvl_filter_i && (priv_lvl_in_range || priv_lvl_equals)) ||
+ ~priv_lvl_filter_i) && // priv_lvl
+ ((iaddr_filter_i && (iaddr_in_range || iaddr_equals)) ||
+ ~iaddr_filter_i) && // iaddr
+ trace_enable_i;
+
+endmodule
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv
new file mode 100644
index 0000000000..447519f685
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv
@@ -0,0 +1,1096 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/* PACKET EMITTER */
+/*
+it produces the packets for the output interface
+*/
+
+module te_packet_emitter
+(
+ input logic clk_i,
+ input logic rst_ni,
+ input logic valid_i,
+
+ // necessary info to assemble packet
+ input te_pkg::format_e packet_format_i,
+ input te_pkg::f_sync_subformat_e packet_f_sync_subformat_i, // SF for F3
+ //input f_opt_ext_subformat_e packet_f_opt_ext_subformat_i, // non mandatory, SF for F0
+
+ // lc (last cycle) signals
+ input logic [te_pkg::XLEN-1:0] lc_cause_i,
+ input logic [te_pkg::XLEN-1:0] lc_tval_i,
+ input logic lc_interrupt_i,
+
+ // tc (this cycle) signals
+ input logic [te_pkg::XLEN-1:0] tc_cause_i,
+ input logic [te_pkg::XLEN-1:0] tc_tval_i,
+ input logic tc_interrupt_i,
+ input logic tc_resync_i,
+
+ input logic nc_exc_only_i,
+ input logic nc_ppccd_br_i,
+
+ // nc (next cycle) signals
+
+ /* the following signals used to determine
+ if the packet emitter has to put context
+ and/or time in the payload*/
+ input logic nocontext_i, // both read from registers
+ input logic notime_i,
+ // in this implementation both hardwired to 0
+
+ // format 3 subformat 0 specific signals
+ input logic tc_branch_i,
+ input logic tc_branch_taken_i,
+ input logic [te_pkg::PRIV_LEN-1:0] tc_priv_i,
+ input logic [te_pkg::TIME_LEN-1:0] tc_time_i, // optional
+ //input logic [:0] context_i, // optional
+ input logic [te_pkg::XLEN-1:0] tc_address_i,
+
+ // format 3 subformat 1 specific signals
+ input logic lc_tc_mux_i,
+ /* format 3 subformat 1 packets require sometimes lc_cause o tc_cause
+ To discriminate I use a mux to choose between lc or tc */
+
+ input logic thaddr_i,
+ input logic [te_pkg::XLEN-1:0] tc_tvec_i, // trap handler address
+ input logic [te_pkg::XLEN-1:0] lc_epc_i,
+
+ // format 3 subformat 3 specific signals
+ input logic tc_ienable_i, // trace encoder enabled
+ input logic encoder_mode_i, // only branch trace supported (value==0)
+ input te_pkg::qual_status_e qual_status_i,
+ input te_pkg::ioptions_s ioptions_i,
+ // about DATA trace, in stand-by at the moment
+ //input logic denable_i, // DATA trace enabled, if supported
+ //input logic dloss_i, // one or more DATA trace packets lost, if supported
+ //input logic [:0] doptions_i, // it's like ioptions, but for DATA trace
+
+
+ // format 2 specific signals
+ /* notify -> means the packet was requested by the cpu trigger unit*/
+ //input logic notify_i, // non mandatory
+
+ // most of the time these 2 values can be compressed
+ input logic lc_updiscon_i,
+
+ // necessary if implicit_return mode is enabled
+ //input logic irreport_i,
+
+ //input logic [2**te_pkg::CALL_COUNTER_SIZE-1:0] irdepth_i, // non mandatory, traces nested calls
+
+ // format 1 specific signals
+ /* this format exists in two modes:
+ - address, branch map
+ - NO address, branch maps
+
+ Their generation depends on the value of branches:
+ - 0: no need for address
+ - >0: address required
+ */
+ input logic [te_pkg::BRANCH_COUNT_LEN-1:0] branches_i,
+ input logic [te_pkg::BRANCH_MAP_LEN-1:0] branch_map_i, // can change size to improve efficiency
+
+ // format 0 specific signals
+ /* This format can have two possible subformats:
+ - subformat 0: number of correctly predicted branches
+ - subformat 1: jump target cache index
+
+ Non mandatory, required support by the encoder.
+ */
+ input logic [$clog2(te_pkg::XLEN):0] keep_bits_i, // required for address compression
+ input logic shallow_trace_i, // used to flush branch map at each packet
+
+ // outputs
+ output logic packet_valid_o, // asserted when a packet is generated
+ output te_pkg::it_packet_type_e packet_type_o,
+ output logic [te_pkg::PAYLOAD_LEN-1:0] packet_payload_o,
+ output logic [te_pkg::P_LEN-1:0] payload_length_o, // in bytes
+ output logic branch_map_flush_o, // flushing done after each request
+ // to send back to priority module in order to compress them
+ output logic [te_pkg::XLEN-1:0] addr_to_compress_o
+);
+
+ // internal signals
+ logic branch;
+ logic interrupt;
+ logic [te_pkg::XLEN-1:0] address;
+ logic [te_pkg::XLEN-1:0] ecause;
+ logic [te_pkg::XLEN-1:0] diff_addr;
+ logic [te_pkg::XLEN-1:0] latest_addr_d, latest_addr_q; // address of the latest packet emitted
+ logic [te_pkg::XLEN-1:0] tval;
+ logic [1:0] time_and_context; // if payload requires time/context
+ logic notify;
+ logic updiscon;
+ logic irreport;
+ logic [2**te_pkg::CALL_COUNTER_SIZE-1:0] irdepth;
+ logic [4:0] branch_map_off;
+ logic [3:0] address_off;
+ logic [8:0] used_bits; // counts the bits used inside each payload
+ logic flush_d, flush_q;
+ logic update_latest_addr;
+ logic resync_d, resync_q;
+ logic [te_pkg::XLEN-1:0] resync_addr_d, resync_addr_q;
+
+ // assigning values
+ assign branch = ~(tc_branch_i && tc_branch_taken_i);
+ assign address = thaddr_i ? tc_tvec_i : lc_epc_i;
+ assign ecause = lc_tc_mux_i ? tc_cause_i : lc_cause_i;
+ assign tval = lc_tc_mux_i ? tc_tval_i : lc_tval_i;
+ assign interrupt = lc_tc_mux_i ? tc_interrupt_i : lc_interrupt_i;
+ assign time_and_context = {~notime_i, ~nocontext_i};
+ assign branch_map_flush_o = flush_q;
+ assign payload_length_o = (used_bits + 7) >> 3;
+
+ always_comb begin
+ // init
+ resync_d = resync_q;
+ resync_addr_d = resync_addr_q;
+
+ // updates resync signal
+ if (tc_resync_i) begin
+ resync_d = '1;
+ resync_addr_d = tc_address_i;
+ end
+
+ // synchronous reset of resync signal
+ if (packet_type_o == te_pkg::F3SF0 && resync_q) begin
+ resync_d = '0;
+ end
+ end
+
+
+ // register to store the last address emitted in a packet
+ always_ff @(posedge clk_i, negedge rst_ni) begin
+ if(~rst_ni) begin
+ latest_addr_q <= '0;
+ flush_q <= '0;
+ resync_q <= '0;
+ resync_addr_q <= '0;
+ end else begin
+ latest_addr_q <= latest_addr_d;
+ resync_q <= resync_d;
+ resync_addr_q <= resync_addr_d;
+ flush_q <= flush_d;
+ end
+ end
+
+ // combinatorial network to compute the offset to compress the branch_map
+ always_comb begin : branch_map_offset
+ if(branches_i == 1) begin
+ branch_map_off = 1;
+ end else if(branches_i <= 3) begin
+ branch_map_off = 3;
+ end else if(branches_i <= 7) begin
+ branch_map_off = 7;
+ end else if(branches_i <= 15) begin
+ branch_map_off = 15;
+ end else if (branches_i < 31) begin
+ branch_map_off = 31;
+ end else begin
+ branch_map_off = '0;
+ end
+
+ end
+
+ /*
+ the address compression works in byte chunks: based on the value of
+ keep_bits_i, the number of least significant bytes to keep is determined.
+
+ example:
+ keep_bits_i == 7 -> 1 lsB kept 0111
+ keep_bits_i == 10 -> 2 lsB kept 1010
+ keep_bits_i == 25 -> 4 lsB kept 11001
+ */
+ // 33 = 100001 + 7 = 101000 >>3 = 0101 = 5
+
+ // find the number of least significant bytes to keep in the compressed address
+ assign address_off = (keep_bits_i + 7)>>3;
+
+ // combinatorial network to output packets
+ always_comb begin
+ // init values
+ packet_payload_o = '0;
+ packet_valid_o = '0;
+ flush_d = '0;
+ used_bits = '0;
+ packet_type_o = te_pkg::F0SF0;
+ update_latest_addr = '0;
+
+ if(valid_i) begin
+ /* branch_map_flush_o
+ the signal is output in this cycle, but the branch map does
+ the flush in the next cycle to leave time to the packet
+ emitter to read values and put them in the payload
+ */
+ // flushes at each packet emitted to get a less precise tracing
+ flush_d = shallow_trace_i;
+
+ // setting the packet to emit as valid
+ packet_valid_o = '1;
+
+ /* packet payload creation:
+ at the beginning it's put in the payload the common part (i.e. the packet format)
+ then, for each format and subformat it's put the rest of the payload
+ */
+
+ // setting the packet format - common for all payloads
+ packet_payload_o[1:0] = packet_format_i;
+
+ // format bits
+ used_bits += 2;
+
+ case(packet_format_i)
+ te_pkg::F_SYNC: begin // format 3
+ // setting packet subformat - common for all type 3 payloads
+ packet_payload_o[3:2] = packet_f_sync_subformat_i;
+
+ used_bits += 2; // subformat bits
+
+ // setting the rest of payload for each type
+ case(packet_f_sync_subformat_i)
+ te_pkg::SF_START: begin // subformat 0
+ // updating packet type
+ packet_type_o = te_pkg::F3SF0;
+ update_latest_addr = '1;
+
+ case(time_and_context)
+ 2'b00: begin
+ used_bits += 1 + (address_off * 8) + te_pkg::PRIV_LEN;
+
+ packet_payload_o[4+:1+te_pkg::PRIV_LEN] = {
+ tc_priv_i,
+ branch
+ };
+ // address compression
+ case (address_off)
+ 1: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+:8] = {
+ addr_to_compress_o[7:0]
+ };
+ end
+ 2: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+:16] = {
+ addr_to_compress_o[15:0]
+ };
+ end
+ 3: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+:24] = {
+ addr_to_compress_o[23:0]
+ };
+ end
+ 4: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+:32] = {
+ addr_to_compress_o[31:0]
+ };
+ end
+ `ifdef TE_ARCH64 // 64bits case
+ 5: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+:40] = {
+ addr_to_compress_o[39:0]
+ };
+ end
+ 6: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+:48] = {
+ addr_to_compress_o[47:0]
+ };
+ end
+ 7: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+:56] = {
+ addr_to_compress_o[55:0]
+ };
+ end
+ 8: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+:64] = {
+ addr_to_compress_o
+ };
+ end
+ `endif
+ endcase
+ end
+
+ 2'b10: begin
+ used_bits += 1 + te_pkg::PRIV_LEN + te_pkg::TIME_LEN + (address_off * 8);
+
+ packet_payload_o[4+:1+te_pkg::PRIV_LEN+te_pkg::TIME_LEN] = {
+ tc_time_i,
+ tc_priv_i,
+ branch
+ };
+ // address compression
+ // FIXME(MAX): simplify case with:
+ // for (int unsigned i = 1; i <= 8; i++) begin
+ // if (i == address_off) begin
+ // packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:i*8] = {
+ // addr_to_compress_o[i*8-1:0]
+ // };
+ // end
+ // end
+ case (address_off)
+ 1: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:8] = {
+ addr_to_compress_o[7:0]
+ };
+ end
+ 2: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:16] = {
+ addr_to_compress_o[15:0]
+ };
+ end
+ 3: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:24] = {
+ addr_to_compress_o[23:0]
+ };
+ end
+ 4: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:32] = {
+ addr_to_compress_o[31:0]
+ };
+ end
+ `ifdef TE_ARCH64 // 64bits case
+ 5: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:40] = {
+ addr_to_compress_o[39:0]
+ };
+ end
+ 6: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:48] = {
+ addr_to_compress_o[47:0]
+ };
+ end
+ 7: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:56] = {
+ addr_to_compress_o[55:0]
+ };
+ end
+ 8: begin
+ packet_payload_o[5+te_pkg::PRIV_LEN+te_pkg::TIME_LEN+:64] = {
+ addr_to_compress_o
+ };
+ end
+ `endif
+ endcase
+ end
+ /*TODO: other cases*/
+ endcase
+ end
+ te_pkg::SF_TRAP: begin // subformat 1
+ // updating packet type
+ packet_type_o = te_pkg::F3SF1;
+ update_latest_addr = '1;
+
+ case(time_and_context)
+ 2'b00: begin
+ used_bits += 1 + te_pkg::PRIV_LEN + te_pkg::XLEN + 2 + (address_off * 8) + te_pkg::XLEN; // last XLEN is for tval
+
+ packet_payload_o[4+:1+te_pkg::PRIV_LEN+te_pkg::XLEN+2] = {
+ thaddr_i,
+ interrupt,
+ ecause,
+ tc_priv_i,
+ branch
+ };
+ // address compression //FIXME Why tval is with addr_to_compress ? and not before ???
+ case (address_off)
+ 1: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:8+te_pkg::XLEN] = {
+ addr_to_compress_o[7:0],
+ tval
+
+ };
+ end
+ 2: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:16+te_pkg::XLEN] = {
+ addr_to_compress_o[15:0],
+ tval
+ };
+ end
+ 3: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:24+te_pkg::XLEN] = {
+ addr_to_compress_o[23:0],
+ tval
+ };
+ end
+ 4: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:32+te_pkg::XLEN] = {
+ addr_to_compress_o[31:0],
+ tval
+ };
+ end
+ `ifdef TE_ARCH64 // 64bits case
+ 5: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:40+te_pkg::XLEN] = {
+ addr_to_compress_o[39:0],
+ tval
+ };
+ end
+ 6: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:48+te_pkg::XLEN] = {
+ addr_to_compress_o[47:0],
+ tval
+ };
+ end
+ 7: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:56+te_pkg::XLEN] = {
+ addr_to_compress_o[55:0],
+ tval
+ };
+ end
+ 8: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+:64+te_pkg::XLEN] = {
+ addr_to_compress_o,
+ tval
+ };
+ end
+ `endif
+ endcase
+ end
+
+ 2'b10: begin
+ used_bits += 1 + te_pkg::PRIV_LEN + te_pkg::XLEN + 2 + (address_off * 8) + te_pkg::TIME_LEN + te_pkg::XLEN ; // why time_len *2 , time = 64 bits ?
+
+ packet_payload_o[4+:1+te_pkg::PRIV_LEN+te_pkg::XLEN+2+te_pkg::TIME_LEN] = {
+ thaddr_i,
+ interrupt,
+ ecause,
+ tc_time_i,
+ tc_priv_i,
+ branch
+ };
+ // address compression
+ case (address_off)
+ 1: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:8+te_pkg::XLEN] = { // FIXME Replace XLEN by TIME_LEN every time ?
+ addr_to_compress_o[7:0],
+ tval
+
+ };
+ end
+ 2: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:16+te_pkg::XLEN] = {
+ addr_to_compress_o[15:0],
+ tval
+ };
+ end
+ 3: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:24+te_pkg::XLEN] = {
+ addr_to_compress_o[23:0],
+ tval
+ };
+ end
+ 4: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:32+te_pkg::XLEN] = {
+ addr_to_compress_o[31:0],
+ tval
+ };
+ end
+ `ifdef TE_ARCH64 // 64bits case
+ 5: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:40+te_pkg::XLEN] = {
+ addr_to_compress_o[39:0],
+ tval
+ };
+ end
+ 6: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:48+te_pkg::XLEN] = {
+ addr_to_compress_o[47:0],
+ tval
+ };
+ end
+ 7: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:56+te_pkg::XLEN] = {
+ addr_to_compress_o[55:0],
+ tval
+ };
+ end
+ 8: begin
+ packet_payload_o[7+te_pkg::PRIV_LEN+te_pkg::XLEN+te_pkg::TIME_LEN+:64+te_pkg::XLEN] = {
+ addr_to_compress_o,
+ tval
+ };
+ end
+ `endif
+ endcase
+ end
+ /*TODO: other cases*/
+ endcase
+ end
+ te_pkg::SF_CONTEXT: begin // subformat 2
+ // updating packet type
+ packet_type_o = te_pkg::F3SF2;
+
+ case(time_and_context)
+ 2'b00: begin
+ used_bits += te_pkg::PRIV_LEN;
+
+ packet_payload_o[4+:te_pkg::PRIV_LEN] = {
+ tc_priv_i
+ };
+ end
+
+ 2'b10: begin
+ used_bits += te_pkg::PRIV_LEN + te_pkg::TIME_LEN;
+
+ packet_payload_o[4+:te_pkg::PRIV_LEN+te_pkg::TIME_LEN] = {
+ tc_time_i,
+ tc_priv_i
+ };
+ end
+ /*TODO: other cases*/
+ endcase
+ end
+ te_pkg::SF_SUPPORT: begin // subformat 3
+ // updating packet type
+ packet_type_o = te_pkg::F3SF3;
+
+ used_bits += 11;
+
+ packet_payload_o[4+:1+1+2+7] = {
+ /* info required for data tracing - in the future
+ doptions_i,
+ dloss_i,
+ denable_i, */
+ ioptions_i,
+ qual_status_i,
+ encoder_mode_i,
+ tc_ienable_i
+ };
+ end
+ endcase
+ end
+
+ te_pkg::F_ADDR_ONLY: begin // format 2
+ // updating packet type
+ packet_type_o = te_pkg::F2;
+ update_latest_addr = '1;
+
+ // requires trigger unit in CPU
+ /*
+ if(notify_i) begin // request from trigger unit
+ notify = !tc_address_i[XLEN-1];
+ updiscon = notify;
+ irreport = updsicon;
+ irdepth = irdepth_i;
+ end else begin*/
+
+ // case of an updiscon
+ if(lc_updiscon_i && (nc_exc_only_i || nc_ppccd_br_i)) begin //FIXME spec says lc_updiscon AND nc_execption/interrupt /priv change / resync <= need to add nc_resync
+ notify = tc_address_i[te_pkg::XLEN-1];
+ updiscon = !notify;
+ irreport = updiscon;
+ irdepth = {2**te_pkg::CALL_COUNTER_SIZE{updiscon}};
+ /* non mandatory
+ end else if(implicit_mode_i && irreport_i) begin // request for implicit return mode
+ notify = tc_address_i[XLEN-1];
+ updiscon = notify;
+ irreport = !updiscon;
+ irdepth = irdepth_i;
+ */
+ end else begin //other cases
+ notify = tc_address_i[te_pkg::XLEN-1];
+ updiscon = notify;
+ irreport = updiscon;
+ irdepth = {2**te_pkg::CALL_COUNTER_SIZE{updiscon}};
+ end
+
+ // checking if implicit return is supported
+ if (te_pkg::CALL_COUNTER_SIZE == 0 &&
+ te_pkg::RETURN_STACK_SIZE == 0) begin // not supported
+
+ // payload bits
+ used_bits += 3 + address_off*8 ;
+
+ // address compression
+ case (address_off)
+ 1: begin
+ packet_payload_o[2+:8+3] = {
+ addr_to_compress_o[7:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 2: begin
+ packet_payload_o[2+:16+3] = {
+ addr_to_compress_o[15:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 3: begin
+ packet_payload_o[2+:24+3] = {
+ addr_to_compress_o[23:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 4: begin
+ packet_payload_o[2+:32+3] = {
+ addr_to_compress_o[31:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ `ifdef TE_ARCH64 // 64bits case
+ 5: begin
+ packet_payload_o[2+:40+3] = {
+ addr_to_compress_o[39:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 6: begin
+ packet_payload_o[2+:48+3] = {
+ addr_to_compress_o[47:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 7: begin
+ packet_payload_o[2+:56+3] = {
+ addr_to_compress_o[55:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 8: begin
+ packet_payload_o[2+:64+3] = {
+ addr_to_compress_o,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ `endif
+ endcase
+
+ end else begin // supported
+ // payload bits
+ used_bits += 3 + 2**te_pkg::CALL_COUNTER_SIZE + address_off*8 ;
+
+ // address compression
+ case (address_off)
+ 1: begin
+ packet_payload_o[2+:8+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[7:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 2: begin
+ packet_payload_o[2+:16+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[15:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 3: begin
+ packet_payload_o[2+:24+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[23:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 4: begin
+ packet_payload_o[2+:32+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[31:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ `ifdef TE_ARCH64 // 64bits case
+ 5: begin
+ packet_payload_o[2+:40+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[39:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 6: begin
+ packet_payload_o[2+:48+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[47:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 7: begin
+ packet_payload_o[2+:56+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[55:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 8: begin
+ packet_payload_o[2+:64+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o,
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ `endif
+ endcase
+ end
+ end
+
+ te_pkg::F_DIFF_DELTA: begin // format 1
+ /* There can be two type of payloads for this format:
+ 1. address, branch map
+ 2. no address, branch map
+
+ Type 1 payload is used when there has been at least
+ one branch from last packet. This can be determined
+ by the number of branches in the branch map.
+
+ Type 2 payload is used when the address is not needed,
+ for examples if the branch map is full.
+ */
+ // flushing the branch_map
+ flush_d = '1;
+ // updating packet type
+ packet_type_o = te_pkg::F1;
+
+ // requires trigger unit in CPU
+ /*
+ if(notify_i) begin // request from trigger unit
+ notify = !tc_address_i[XLEN-1];
+ updiscon = notify;
+ irreport = updsicon;
+ irdepth = irdepth_i;
+ end else begin*/
+
+ // case of an updiscon
+ if(lc_updiscon_i && (nc_exc_only_i || nc_ppccd_br_i)) begin //FIXME spec says lc_updiscon AND nc_execption/interrupt /priv change / resync <= need to add nc_resync
+ notify = tc_address_i[te_pkg::XLEN-1];
+ updiscon = !notify;
+ irreport = updiscon;
+ irdepth = {2**te_pkg::CALL_COUNTER_SIZE{updiscon}};
+ /* non mandatory
+ end else if(implicit_return_i && irreport_i) begin // request for implicit return mode
+ notify = tc_address_i[XLEN-1];
+ updiscon = notify;
+ irreport = !updiscon;
+ irdepth = irdepth_i;
+ */
+ end else begin // other cases
+ notify = tc_address_i[te_pkg::XLEN-1];
+ updiscon = notify;
+ irreport = updiscon;
+ irdepth = {2**te_pkg::CALL_COUNTER_SIZE{updiscon}};
+ end
+
+ // branches and branch_map bits
+ used_bits += (branch_map_off==0)? te_pkg::BRANCH_COUNT_LEN + 32 : te_pkg::BRANCH_COUNT_LEN + branch_map_off;
+
+ // adding branch count and branch map
+ if (branch_map_off == 1) begin
+ packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+1] = {
+ branch_map_i[0],
+ branches_i
+ };
+ end else if (branch_map_off == 3) begin
+ packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+3] = {
+ branch_map_i[2:0],
+ branches_i
+ };
+ end else if (branch_map_off == 7) begin
+ packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+7] = {
+ branch_map_i[6:0],
+ branches_i
+ };
+ end else if (branch_map_off == 15) begin
+ packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+15] = {
+ branch_map_i[14:0],
+ branches_i
+ };
+ end else if (branch_map_off == 31) begin
+ packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+31] = {
+ branch_map_i[30:0],
+ branches_i
+ };
+ end else begin //FIXME if we have discontinuity branches =31 not 0
+ packet_payload_o[2+:te_pkg::BRANCH_COUNT_LEN+31] = {
+ branch_map_i[30:0],
+ 5'b00000
+ };
+ end
+
+ // attaching the rest of the payload
+ if(branches_i < 31) begin // branch map not full - address
+ update_latest_addr = '1;
+ // checking if implicit return is supported
+ if (te_pkg::CALL_COUNTER_SIZE == 0 &&
+ te_pkg::RETURN_STACK_SIZE == 0) begin // not supported
+ // rest of the payload bits
+ used_bits += 3 + address_off*8 ;
+
+ // address compression
+ case (address_off)
+ 1: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:8+3] = {
+ addr_to_compress_o[7:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 2: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:16+3] = {
+ addr_to_compress_o[15:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 3: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:24+3] = {
+ addr_to_compress_o[23:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 4: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:32+3] = {
+ addr_to_compress_o[31:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ `ifdef TE_ARCH64 // 64bits case
+ 5: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:40+3] = {
+ addr_to_compress_o[39:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 6: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:48+3] = {
+ addr_to_compress_o[47:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 7: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:56+3] = {
+ addr_to_compress_o[55:0],
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 8: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:64+3] = {
+ addr_to_compress_o,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ `endif
+ endcase
+
+ end else begin // supported -> uses irdepth and irreport
+ // rest of the payload bits
+ used_bits += 3 + 2**te_pkg::CALL_COUNTER_SIZE + address_off*8 ;
+
+ // address compression
+ case (address_off)
+ 1: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:8+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[7:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 2: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:16+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[15:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 3: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:24+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[23:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 4: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:32+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[31:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ `ifdef TE_ARCH64 // 64bits case
+ 5: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:40+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[39:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 6: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:48+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[47:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 7: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:56+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o[55:0],
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ 8: begin
+ packet_payload_o[2+te_pkg::BRANCH_COUNT_LEN+branch_map_off+:64+3+2**te_pkg::CALL_COUNTER_SIZE] = {
+ addr_to_compress_o,
+ irdepth,
+ irreport,
+ updiscon,
+ notify
+ };
+ end
+ `endif
+ endcase
+ end
+ end
+ end
+
+ //F_OPT_EXT: begin // format 0 // TODO
+ // requires trigger unit in CPU
+ /*
+ if(notify_i) begin // request from trigger unit
+ notify = !tc_address_i[XLEN-1];
+ updiscon = notify;
+ irreport = updsicon;
+ irdepth = irdepth_i;
+ end else begin
+ notify = tc_address_i[XLEN-1];
+ updiscon = notify;
+ irreport = updiscon;
+ irdepth = {2**CALL_COUNTER_SIZE{updiscon}};
+ end */
+
+ /* requires non mandatory support for jtc and branch prediction
+ case(packet_f_opt_ext_subformat_i)
+ SF_PBC: begin // subformat 0
+ /* There can be two type of payloads for this subformat:
+ 1. no address, branch count
+ 2. address, branch count
+ * /
+
+ // only for F0SF0 payload w/address
+ // updating latest address sent in a packet
+
+ packet_payload_o = {F_OPT_EXT, SF_PBC, etc..};
+ packet_valid_o = '1;
+ end
+
+ SF_JTC: begin // subformat 1
+ packet_payload_o = {F_OPT_EXT, SF_JTC, etc..};
+ packet_valid_o = '1;
+ end
+ endcase
+ */
+ //end
+ endcase
+ end
+ end
+
+ always_comb begin : address_to_compress
+ diff_addr = '0;
+ addr_to_compress_o = '0;
+ latest_addr_d = latest_addr_q;
+
+ // determines differential address for F1, F2
+ if (packet_valid_o && (packet_format_i == te_pkg::F_DIFF_DELTA ||
+ packet_format_i == te_pkg::F_ADDR_ONLY)) begin
+ if (ioptions_i.delta_address_en) begin
+ diff_addr = latest_addr_q - tc_address_i; // mostly >0 exept for jump , remove signed
+ addr_to_compress_o = diff_addr;
+ end else if (ioptions_i.full_address_en) begin
+ addr_to_compress_o = tc_address_i;
+ end
+ end
+
+ // determines latest address
+ if (packet_valid_o && update_latest_addr) begin
+ if (packet_type_o == te_pkg::F1 ||
+ packet_type_o == te_pkg::F2) begin // F1, F2
+ latest_addr_d = tc_address_i;
+ addr_to_compress_o = tc_address_i;
+ end
+ if (packet_type_o == te_pkg::F3SF0) begin // F3SF0
+ if (resync_q) begin //FIXME WHY ?
+ latest_addr_d = tc_address_i;
+ addr_to_compress_o = tc_address_i;
+ end else begin
+ latest_addr_d = tc_address_i;
+ addr_to_compress_o = tc_address_i;
+ end
+ end
+ if (packet_type_o == te_pkg::F3SF1) begin // F3SF1
+ latest_addr_d = address;
+ addr_to_compress_o = address;
+ end
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv
new file mode 100644
index 0000000000..9fd6db48af
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv
@@ -0,0 +1,405 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/*PRIORITY*/
+/*
+change this module name to a more appropriate one
+for example "packet identifier" or something similar
+*/
+/*
+it orders packet generation - refer to page 53 of the spec
+*/
+
+module te_priority (
+
+ input logic clk_i,
+ input logic rst_ni,
+
+ input logic valid_i,
+
+ /* signals for the jump target cache mode - non mandatory */
+ //input logic jtc_enabled_i,
+ //input logic address_in_cache_i, // communicates if the address is present in cache
+
+ // lc (last cycle) signals
+ input logic lc_exception_i,
+ input logic lc_updiscon_i, // updsicon == uninferable PC discontinuity
+
+ // tc (this cycle) signals
+ input logic tc_qualified_i,
+ input logic tc_exception_i,
+ input logic [te_pkg::IRETIRE_LEN-1:0] tc_retired_i,
+ input logic tc_first_qualified_i,
+ input logic tc_privchange_i,
+ //input logic tc_context_change_i, // non mandatory
+ //input logic tc_precise_context_report_i, // requires ctype signal CPU side
+ //input logic tc_context_report_as_disc_i, // ibidem
+ //input logic tc_imprecise_context_report_i, // ibidem
+ input logic tc_gt_max_resync_i, // greater than timeout
+ input logic tc_et_max_resync_i, // one step to timeout
+ input logic tc_branch_map_empty_i,
+ input logic tc_branch_map_full_i,
+ //input logic tc_branch_misprediction_i, // non mandatory
+ //input logic tc_pbc_i, // correctly predicted branch count, non mandatory
+
+ // format 3 subformat 3 - NOT shown in graph
+ input logic tc_enc_enabled_i,
+ input logic tc_enc_disabled_i,
+ input logic tc_opmode_change_i,
+ input logic tc_final_qualified_i,
+ input logic tc_packets_lost_i, // non mandatory
+
+ // nc (next cycle) signals
+ input logic nc_exception_i,
+ input logic nc_privchange_i,
+ //input logic nc_context_change_i, // non mandatory
+ //input logic nc_precise_context_report_i, // requires ctype signal CPU side
+ //input logic nc_context_report_as_disc_i, // ibidem
+ input logic nc_branch_map_empty_i,
+ input logic nc_qualified_i,
+ input logic [te_pkg::IRETIRE_LEN-1:0] nc_retired_i, // used w/nc_exception for signal nc_exc_only
+
+ // non mandatory sideband signals
+ // refer to page 52 of the spec
+ //input logic halted_i,
+ //input logic reset_i,
+
+ // inputs for irreport and irdepth, non mandatory
+ //input logic implicit_return_i, // tells if the mode is enabled
+ //input logic [:0] call_counter_size_i, // size of nested calls counter, 2^value
+ //input logic [:0] return_stack_size_i, // size of nested calls stack, 2^value
+
+ // trigger unit request ports, must be supported by the CPU
+ //input logic tc_trigger_req_i,
+ //output logic notify_o,
+ // communicates the packet emitter that format 2 packet was requested by trigger unit
+
+ // input to compress
+ input logic [te_pkg::XLEN-1:0] addr_to_compress_i,
+
+ // outputs for packet_emitter
+ output logic valid_o,
+ output te_pkg::format_e packet_format_o,
+ output te_pkg::f_sync_subformat_e packet_f_sync_subformat_o,
+ //output te_pkg::f_opt_ext_subformat_e packet_f_opt_ext_subformat_o, // non mandatory, used for jtc and branch prediction
+ output logic thaddr_o, // required for f3 sf1 packet payload
+ output logic lc_tc_mux_o, // operates the MUX to choose between lc or tc cause, tval, interrupt: 0 -> lc, 1
+ output logic resync_timer_rst_o, // resets counter
+ output te_pkg::qual_status_e qual_status_o,
+ //output logic irreport_o, // non mandatory, required implicit return mode
+ output logic tc_resync_o,
+ output logic nc_exc_only_o,
+ output logic nc_ppccd_br_o,
+ // output for compression
+ output logic [$clog2(te_pkg::XLEN):0] keep_bits_o
+ );
+
+
+ /* internal signals required for packet determination */
+ // last cycle
+ logic lc_ended_ntr_d, lc_ended_ntr_q;
+ logic lc_ended_rep_d, lc_ended_rep_q;
+ // this cycle
+ logic tc_exc_only; // for a precise definition: page 51 of the spec
+ logic tc_ppccd; // ibidem
+ logic tc_resync_br; // ibidem
+ logic tc_er_n; // ibidem
+ logic tc_rpt_br; // ibidem
+ //logic tc_cci; // ibidem
+ logic tc_reported_d, tc_reported_q; // ibidem
+ logic reported_status;
+ logic reported_update; // determines when reported_q updates
+ // reported is updated when the lc_exception was updated or not
+ logic tc_f3_sf3;
+ // next cycle
+
+ // signals for compression
+ logic [$clog2(te_pkg::XLEN)-1:0] addr_zeros, addr_ones;
+ logic [$clog2(te_pkg::XLEN)-1:0] sign_extendable;
+ logic empty_zeros;
+ logic empty_ones;
+
+ // signals to store
+ logic tc_resync_br_d, tc_resync_br_q;
+
+ // value assignment
+ assign tc_exc_only = tc_exception_i && tc_retired_i == 0;
+ assign tc_ppccd = tc_privchange_i /*|| (tc_context_change_i &&
+ (tc_precise_context_report_i ||
+ tc_context_report_as_disc_i))*/;
+ assign tc_resync_br = tc_et_max_resync_i && ~tc_branch_map_empty_i;
+ assign tc_er_n = (tc_exception_i && tc_retired_i != 0) /*|| tc_trigger_req_i*/;
+ assign tc_rpt_br = tc_branch_map_full_i && !nc_branch_map_empty_i/* || tc_branch_misprediction_i*/;
+ //assign tc_cci = tc_context_change_i && tc_imprecise_context_report_i;
+ assign nc_exc_only_o = nc_exception_i && nc_retired_i == 0;
+ assign nc_ppccd_br_o = (nc_privchange_i /*|| (nc_context_change_i &&
+ (nc_precise_context_report_i || nc_context_report_as_disc_i))*/) &&
+ ~nc_branch_map_empty_i;
+ assign tc_f3_sf3 = tc_enc_enabled_i || tc_enc_disabled_i || tc_opmode_change_i ||
+ tc_final_qualified_i || tc_packets_lost_i;
+ assign reported_update = ( packet_format_o == te_pkg::F_SYNC &&
+ packet_f_sync_subformat_o == te_pkg::SF_TRAP &&
+ ~thaddr_o) ||
+ ( packet_format_o == te_pkg::F_SYNC &&
+ packet_f_sync_subformat_o == te_pkg::SF_START &&
+ ~tc_exc_only);
+ assign tc_resync_o = valid_i && tc_resync_br_q;
+
+ always_comb begin
+ // init
+ tc_resync_br_d = tc_resync_br_q;
+
+ if (reported_update) begin
+ tc_reported_d = reported_status;
+ end
+
+ if (tc_resync_br) begin
+ tc_resync_br_d = '1;
+ end
+
+ if (valid_o &&
+ (packet_format_o == te_pkg::F_DIFF_DELTA ||
+ packet_format_o == te_pkg::F_ADDR_ONLY)) begin
+ tc_resync_br_d = '0;
+ end
+ end
+
+ /*
+ The reset value is 0, the spec doesn't say how to behave.
+ The 0 value specifies an exception w/out retired instr
+ in this cycle and an exception in the previous cycle.
+ */
+ always_ff @( posedge clk_i, negedge rst_ni ) begin
+ if(~rst_ni) begin
+ tc_reported_q <= '0;
+ lc_ended_ntr_q <= '0;
+ lc_ended_rep_q <= '0;
+ tc_resync_br_q <= '0;
+ end else begin
+ tc_reported_q <= tc_reported_d;
+ tc_resync_br_q <= tc_resync_br_d;
+ lc_ended_ntr_q <= lc_ended_ntr_d;
+ lc_ended_rep_q <= lc_ended_rep_d;
+ end
+ end
+
+ /*TODO: add condition to determine if F2, F1, F0SF0 are requested by the trigger unit*/
+
+ /* combinatorial network to determine packet format */
+ // refer to flowchart at page 53 of the spec
+ always_comb begin : select_packet_format
+ // default init values
+ valid_o = '0;
+ packet_format_o = te_pkg::F_OPT_EXT;
+ packet_f_sync_subformat_o = te_pkg::SF_START;
+ //packet_f_opt_ext_subformat_o = SF_PBC;
+ //notify_o = '0;
+ thaddr_o = '0;
+ lc_tc_mux_o = '0;
+ resync_timer_rst_o = '0;
+ reported_status = '0;
+ qual_status_o = te_pkg::NO_CHANGE;
+ lc_ended_ntr_d = '0;
+ lc_ended_rep_d = '0;
+
+ if(valid_i) begin
+ // format 3 subformat 3 packet generation
+ /* this if is not in the flowchart, but it's only described.
+ To me it made more sense to have it as the first if. */
+ if(tc_f3_sf3) begin
+ packet_format_o = te_pkg::F_SYNC;
+ packet_f_sync_subformat_o = te_pkg::SF_SUPPORT;
+ // if-then-else to determine qual_status value for payload
+ if(lc_ended_ntr_q == '1) begin
+ qual_status_o = te_pkg::ENDED_NTR;
+ end else if(lc_ended_rep_q == '1) begin
+ qual_status_o = te_pkg::ENDED_REP;
+ end else if(tc_packets_lost_i == '1) begin
+ qual_status_o = te_pkg::TRACE_LOST;
+ end
+ valid_o = '1;
+ /* TODO: if for halted and reset sideband signals,
+ if at least one asserted -> considers unqualified*/
+ end else if(tc_qualified_i) begin
+ if(lc_exception_i) begin
+ if(tc_exc_only) begin
+ packet_format_o = te_pkg::F_SYNC;
+ packet_f_sync_subformat_o = te_pkg::SF_TRAP;
+ resync_timer_rst_o = '1;
+ lc_tc_mux_o = 0;
+ reported_status = '1;
+ thaddr_o = '0;
+ /* thaddr_d = 0; resync_cnt = 0
+ cause = lc_cause_i; tval = lc_tval*/
+ valid_o = '1;
+ end else if(tc_reported_q) begin
+ packet_format_o = te_pkg::F_SYNC;
+ packet_f_sync_subformat_o = te_pkg::SF_START;
+ resync_timer_rst_o = '1;
+ //reported_d = '0; // not necessary
+ // resync_cnt = 0
+ valid_o = '1;
+ end else begin // not reported
+ packet_format_o = te_pkg::F_SYNC;
+ packet_f_sync_subformat_o = te_pkg::SF_TRAP;
+ resync_timer_rst_o = '1;
+ lc_tc_mux_o = '0;
+ thaddr_o = '1;
+ /*thaddr_d = 1; resync_cnt = 0
+ cause = lc_cause_i; tval = lc_tval */
+ valid_o = '1;
+ end
+ end else if(tc_first_qualified_i || tc_ppccd || (tc_gt_max_resync_i && !tc_resync_br_q)) begin
+ packet_format_o = te_pkg::F_SYNC;
+ packet_f_sync_subformat_o = te_pkg::SF_START;
+ resync_timer_rst_o = '1;
+ //resync_cnt = 0
+ valid_o = '1;
+ end else if(lc_updiscon_i) begin
+ // packet generated due to updiscon
+ lc_ended_ntr_d = '1;
+ if(tc_exc_only) begin
+ packet_format_o = te_pkg::F_SYNC;
+ packet_f_sync_subformat_o = te_pkg::SF_TRAP;
+ thaddr_o = '0;
+ resync_timer_rst_o = '1;
+ lc_tc_mux_o = '1;
+ /* thaddr = 0; resync_cnt = 0
+ cause = tc_cause_i; tval = tc_tval */
+ valid_o = '1;
+ end else begin
+ /* choosing between format 0/1/2 */
+ /*if(tc_pbc_i >= 31) begin // format 0 subformat 0
+ packet_format_o = F_OPT_EXT;
+ packet_f_opt_ext_subformat_o = SF_JTC;
+ // value for payload TBD
+ end else if(jtc_enabled_i && address_in_cache_i) begin // format 0 subformat 1
+ packet_format_o = F_OPT_EXT;
+ packet_f_opt_ext_subformat_o = SF_JTC;
+ // value for payload TBD
+ end else*/ if(!tc_branch_map_empty_i) begin
+ packet_format_o = te_pkg::F_DIFF_DELTA;
+ end else begin // branch count == 0
+ packet_format_o = te_pkg::F_ADDR_ONLY;
+ end
+ valid_o = '1;
+ end
+ end else if(tc_resync_br_q || tc_er_n) begin
+ // non mandatory
+ /* if(tc_er_n && tc_trigger_req_i) begin // requested from trigger unit
+ notify_o = '1;
+ end */
+
+ /* choosing between format 0/1/2 */
+ /*if(tc_pbc_i >= 31) begin
+ packet_format_o = F_OPT_EXT;
+ packet_f_opt_ext_subformat_o = SF_JTC;
+ // value for payload TBD
+ end else if(jtc_enabled_i && address_in_cache_i) begin
+ packet_format_o = F_OPT_EXT;
+ packet_f_opt_ext_subformat_o = SF_JTC;
+ // value for payload TBD
+ end else*/ if(!tc_branch_map_empty_i) begin
+ packet_format_o = te_pkg::F_DIFF_DELTA;
+ end else begin // branch count == 0
+ packet_format_o = te_pkg::F_ADDR_ONLY;
+ end
+ valid_o = '1;
+ end else if(nc_exc_only_o || nc_ppccd_br_o || !nc_qualified_i) begin
+ if(!nc_qualified_i) begin
+ // the packet is sent because it's the last instr qualified
+ lc_ended_rep_d = '1;
+ end
+ /* choosing between format 0/1/2 */
+ /*if(tc_pbc_i >= 31) begin
+ packet_format_o = F_OPT_EXT;
+ packet_f_opt_ext_subformat_o = SF_JTC;
+ // value for payload TBD
+ end else if(jtc_enabled_i && address_in_cache_i) begin
+ packet_format_o = F_OPT_EXT;
+ packet_f_opt_ext_subformat_o = SF_JTC;
+ // value for payload TBD
+ end else*/ if(!tc_branch_map_empty_i) begin
+ packet_format_o = te_pkg::F_DIFF_DELTA;
+ end else begin // branch count == 0
+ packet_format_o = te_pkg::F_ADDR_ONLY;
+ end
+ valid_o = '1;
+ end else if(tc_rpt_br) begin
+ /* // non mandatory, requires support for jtc and branch prediction
+ if(tc_pbc_i >= 31) begin
+ packet_format_o = F_OPT_EXT;
+ packet_f_opt_ext_subformat_o = SF_PBC;
+ valid_o = '1;
+ end else begin*/
+ packet_format_o = te_pkg::F_DIFF_DELTA;
+ valid_o = '1;
+ //end
+ end /*else if(tc_cci) begin // non mandatory, requires support for context
+ packet_format_o = F_SYNC;
+ packet_f_sync_subformat_o = SF_CONTEXT;
+ valid_o = '1;
+ end*/
+ end
+ end
+ end
+
+ /* compression logic */
+ /* short explanation on how it works:
+ by using the lzc we determine how many bits we can discard starting from the MSB,
+ this process is done with the normal address (we count 0s) and bitwise not of the
+ signal (we count 1s).
+ Then we decide in which way we can compress more and output the keep_bits signal.
+
+ On the encoder side, it's possible to reconstruct the address: because we don't
+ remove all 0s (or 1s) from the MSB, but we keep one. This way it's possible to
+ sign extend the compressed address and get back the original address.
+
+ Example 1:
+ address to compress: 0000001100010
+ bits kept: -----01100010
+
+ Example 2:
+ address to compress: 1111011110110
+ bits kept: ---1011110110
+
+ */
+ // choosing between removing 1s or 0s
+ assign sign_extendable = addr_zeros > addr_ones ? addr_zeros : addr_ones;
+ // outputting the least sign bits we want to keep
+ // empty signals are used to cover 32'b0 and 32'b1 corner cases
+ assign keep_bits_o = (empty_zeros || empty_ones) ? 1 : te_pkg::XLEN - sign_extendable + 1;
+
+ // leading zero counters
+ // from common_cells
+ lzc #(
+ .WIDTH(te_pkg::XLEN),
+ .MODE(1)
+ )i_lzc_zeros(
+ .in_i (addr_to_compress_i),
+ .cnt_o (addr_zeros),
+ .empty_o(empty_zeros)
+ );
+
+ lzc #(
+ .WIDTH(te_pkg::XLEN),
+ .MODE(1)
+ )i_lzc_ones(
+ .in_i (~addr_to_compress_i),
+ .cnt_o (addr_ones),
+ .empty_o(empty_ones)
+ );
+
+endmodule
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv
new file mode 100644
index 0000000000..0b7a086a51
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv
@@ -0,0 +1,792 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/*REG*/
+/*
+it stores values for the encoder in memory mapped registers
+*/
+
+// uncomment to enable 64bits arch support
+//`define TE_ARCH64
+
+module te_reg #(
+ parameter APB_ADDR_WIDTH = 32 // it is the max allowed, maybe change to a smaller value
+)
+(
+ input logic clk_i,
+ input logic rst_ni,
+
+ // tracing management
+ input logic trace_req_off_i, // from filter
+ input logic trace_req_on_i, // directly from trigger unit
+ input logic encapsulator_ready_i,
+
+ // filter settings
+ output logic cause_filter_o,
+ output logic [te_pkg::XLEN-1:0] upper_cause_o,
+ output logic [te_pkg::XLEN-1:0] lower_cause_o,
+ output logic [te_pkg::XLEN-1:0] match_cause_o,
+ output logic cause_mode_o,
+ output logic tvec_filter_o,
+ output logic [te_pkg::XLEN-1:0] upper_tvec_o,
+ output logic [te_pkg::XLEN-1:0] lower_tvec_o,
+ output logic [te_pkg::XLEN-1:0] match_tvec_o,
+ output logic tvec_mode_o,
+ output logic tval_filter_o,
+ output logic [te_pkg::XLEN-1:0] upper_tval_o,
+ output logic [te_pkg::XLEN-1:0] lower_tval_o,
+ output logic [te_pkg::XLEN-1:0] match_tval_o,
+ output logic tval_mode_o,
+ output logic priv_lvl_filter_o,
+ output logic [te_pkg::PRIV_LEN-1:0] upper_priv_o,
+ output logic [te_pkg::PRIV_LEN-1:0] lower_priv_o,
+ output logic [te_pkg::PRIV_LEN-1:0] match_priv_o,
+ output logic priv_lvl_mode_o,
+ output logic iaddr_filter_o,
+ output logic [te_pkg::XLEN-1:0] upper_iaddr_o,
+ output logic [te_pkg::XLEN-1:0] lower_iaddr_o,
+ output logic [te_pkg::XLEN-1:0] match_iaddr_o,
+ output logic iaddr_mode_o,
+
+ output logic trace_enable_o, // turned off by filter
+ output logic trace_activated_o, // managed by user
+ // packet_emitter settings and control
+ output logic nocontext_o,
+ output logic notime_o,
+ output logic encoder_mode_o, // hardwired to 0 - can only be 0 according to spec
+ output te_pkg::ioptions_s configuration_o,
+ output logic lossless_trace_o,
+ output logic shallow_trace_o,
+
+ output logic clk_gated_o,
+
+ // APB I/O interface
+ input logic [APB_ADDR_WIDTH-1:0] paddr_i,
+ input logic pwrite_i,
+ input logic psel_i,
+ input logic penable_i,
+ input logic [31:0] pwdata_i,
+ output logic pready_o,
+ output logic [31:0] prdata_o
+);
+
+ // FFs I/Os
+ logic trace_enable_d, trace_enable_q;
+ // trace enabling
+ logic trace_req_off, trace_req_on;
+ logic turn_on, turn_off;
+ logic clk_gated;
+ logic test_enabled;
+
+ // registers I/O
+ logic cause_filter_d, cause_filter_q;
+ logic [te_pkg::XLEN-1:0] upper_cause_d, upper_cause_q;
+ logic [te_pkg::XLEN-1:0] lower_cause_d, lower_cause_q;
+ logic [te_pkg::XLEN-1:0] match_cause_d, match_cause_q;
+ logic cause_mode_d, cause_mode_q;
+ logic tvec_filter_d, tvec_filter_q;
+ logic [te_pkg::XLEN-1:0] upper_tvec_d, upper_tvec_q;
+ logic [te_pkg::XLEN-1:0] lower_tvec_d, lower_tvec_q;
+ logic [te_pkg::XLEN-1:0] match_tvec_d, match_tvec_q;
+ logic tvec_mode_d, tvec_mode_q;
+ logic tval_filter_d, tval_filter_q;
+ logic [te_pkg::XLEN-1:0] upper_tval_d, upper_tval_q;
+ logic [te_pkg::XLEN-1:0] lower_tval_d, lower_tval_q;
+ logic [te_pkg::XLEN-1:0] match_tval_d, match_tval_q;
+ logic tval_mode_d, tval_mode_q;
+ logic priv_lvl_filter_d, priv_lvl_filter_q;
+ logic [te_pkg::PRIV_LEN-1:0] upper_priv_d, upper_priv_q;
+ logic [te_pkg::PRIV_LEN-1:0] lower_priv_d, lower_priv_q;
+ logic [te_pkg::PRIV_LEN-1:0] match_priv_d, match_priv_q;
+ logic priv_lvl_mode_d, priv_lvl_mode_q;
+ logic iaddr_filter_d, iaddr_filter_q;
+ logic [te_pkg::XLEN-1:0] upper_iaddr_d, upper_iaddr_q;
+ logic [te_pkg::XLEN-1:0] lower_iaddr_d, lower_iaddr_q;
+ logic [te_pkg::XLEN-1:0] match_iaddr_d, match_iaddr_q;
+ logic iaddr_mode_d, iaddr_mode_q;
+ logic trace_activated_d, trace_activated_q;
+ logic nocontext_d, nocontext_q;
+ logic notime_d, notime_q;
+ te_pkg::ioptions_s configuration_d, configuration_q;
+ logic lossless_trace_d, lossless_trace_q;
+ logic shallow_trace_d, shallow_trace_q;
+
+ // APB transaction
+ logic read_access;
+ logic write_access;
+ logic setup_d, setup_q;
+
+ // assignments
+ // filter
+ assign cause_filter_o = cause_filter_q;
+ assign upper_cause_o = upper_cause_q;
+ assign lower_cause_o = lower_cause_q;
+ assign match_cause_o = match_cause_q;
+ assign cause_mode_o = cause_mode_q;
+ assign tvec_filter_o = tvec_filter_q;
+ assign upper_tvec_o = upper_tvec_q;
+ assign lower_tvec_o = lower_tvec_q;
+ assign match_tvec_o = match_tvec_q;
+ assign tvec_mode_o = tvec_mode_q;
+ assign tval_filter_o = tval_filter_q;
+ assign upper_tval_o = upper_tval_q;
+ assign lower_tval_o = lower_tval_q;
+ assign match_tval_o = match_tval_q;
+ assign tval_mode_o = tval_mode_q;
+ assign priv_lvl_filter_o = priv_lvl_filter_q;
+ assign upper_priv_o = upper_priv_q;
+ assign lower_priv_o = lower_priv_q;
+ assign match_priv_o = match_priv_q;
+ assign priv_lvl_mode_o = priv_lvl_mode_q;
+ assign iaddr_filter_o = iaddr_filter_q;
+ assign upper_iaddr_o = upper_iaddr_q;
+ assign lower_iaddr_o = lower_iaddr_q;
+ assign match_iaddr_o = match_iaddr_q;
+ assign iaddr_mode_o = iaddr_mode_q;
+ // packet emitter
+ assign configuration_o = configuration_q;
+ assign lossless_trace_o = lossless_trace_q; // if == 1 stalls the core when the encapsulator buffer is full
+ assign shallow_trace_o = shallow_trace_q; // if == 1 flushes the branch map at each packet emitted
+ assign nocontext_o = nocontext_q;
+ assign notime_o = notime_q;
+ assign encoder_mode_o = '0; // hardwired
+ assign trace_activated_o = trace_activated_q;
+
+ // tracing is switched on only when it's not enabled anc a request of turning on is received
+ assign turn_on = (trace_enable_q == 0) && (trace_req_on /*|| encapsulator_ready_i*/); // encapsulator signal is temporarely disabled
+ // tracing is switched off only when it's not enabled anc a request of turning off is received
+ assign turn_off = (trace_enable_q == 1) && (trace_req_off /*|| ~encapsulator_ready_i*/);
+ // the toggle of trace_enable value happens only when turn off or turn off is asserted
+ assign trace_enable_d = (turn_off || turn_on) ? ~trace_enable_q : trace_enable_q;
+ assign trace_enable_o = trace_enable_d;
+
+ assign clk_gated_o = clk_gated;
+ assign test_enabled = '0;
+
+ assign setup_d = psel_i && ~penable_i;
+ assign pready_o = setup_q && psel_i && penable_i;
+ assign read_access = pready_o && !pwrite_i;
+ assign write_access = pready_o && pwrite_i;
+
+ /* APB read and write */
+ always_comb begin
+ // initialization
+ // set _d as _q, because we don't to erase them all
+ cause_filter_d = cause_filter_q;
+ cause_mode_d = cause_mode_q;
+ tvec_filter_d = tvec_filter_q;
+ tvec_mode_d = tvec_mode_q;
+ tval_filter_d = tval_filter_q;
+ tval_mode_d = tval_mode_q;
+ priv_lvl_filter_d = priv_lvl_filter_q;
+ priv_lvl_mode_d = priv_lvl_mode_q;
+ iaddr_filter_d = iaddr_filter_q;
+ iaddr_mode_d = iaddr_mode_q;
+ lower_priv_d = lower_priv_q;
+ upper_priv_d = upper_priv_q;
+ match_priv_d = match_priv_q;
+ trace_activated_d = trace_activated_q;
+ lossless_trace_d = lossless_trace_q;
+ shallow_trace_d = shallow_trace_q;
+ notime_d = notime_q;
+ nocontext_d = nocontext_q;
+ configuration_d = configuration_q;
+ upper_cause_d = upper_cause_q;
+ lower_cause_d = lower_cause_q;
+ match_cause_d = match_cause_q;
+ upper_tvec_d = upper_tvec_q;
+ lower_tvec_d = lower_tvec_q;
+ match_tvec_d = match_tvec_q;
+ upper_tval_d = upper_tval_q;
+ lower_tval_d = lower_tval_q;
+ match_tval_d = match_tval_q;
+ upper_iaddr_d = upper_iaddr_q;
+ lower_iaddr_d = lower_iaddr_q;
+ match_iaddr_d = match_iaddr_q;
+ prdata_o = '0; // clean output
+
+ if (read_access) begin
+ case (paddr_i[7:0])
+ // XLEN agnostic (or always <= than 32)
+ // FILTER
+ // enable and mode
+ te_pkg::CAUSE_ENABLE_MODE: begin
+ prdata_o[0] = cause_filter_q;
+ prdata_o[1] = cause_mode_q;
+ end
+
+ te_pkg::TVEC_ENABLE_MODE: begin
+ prdata_o[0] = tvec_filter_q;
+ prdata_o[1] = tvec_mode_q;
+ end
+
+ te_pkg::TVAL_ENABLE_MODE: begin
+ prdata_o[0] = tval_filter_q;
+ prdata_o[1] = tval_mode_q;
+ end
+
+ te_pkg::PRIV_ENABLE_MODE: begin
+ prdata_o[0] = priv_lvl_filter_q;
+ prdata_o[1] = priv_lvl_mode_q;
+ end
+
+ te_pkg::IADDR_ENABLE_MODE: begin
+ prdata_o[0] = iaddr_filter_q;
+ prdata_o[1] = iaddr_mode_q;
+ end
+
+ // priv
+ te_pkg::PRIV_RANGE: begin
+ prdata_o[te_pkg::PRIV_LEN-1:0] = lower_priv_q;
+ prdata_o[te_pkg::PRIV_LEN*2-1:te_pkg::PRIV_LEN] = upper_priv_q;
+ end
+
+ te_pkg::PRIV_MATCH: begin
+ prdata_o[te_pkg::PRIV_LEN-1:0] = match_priv_q;
+ end
+
+ // TRACE MANAGEMENT
+ te_pkg::TRACE_STATE: begin
+ prdata_o[0] = trace_activated_q;
+ end
+
+ te_pkg::LOSSLESS_TRACE: begin
+ prdata_o[0] = lossless_trace_q;
+ end
+
+ te_pkg::SHALLOW_TRACE: begin
+ prdata_o[0] = shallow_trace_q;
+ end
+
+ // PACKET EMITTER
+ te_pkg::NO_TIME: begin
+ prdata_o[0] = notime_q;
+ end
+
+ te_pkg::NO_CONTEXT: begin
+ prdata_o[0] = nocontext_q;
+ end
+
+ te_pkg::DELTA_ADDRESS: begin
+ prdata_o[0] = configuration_q.delta_address_en;
+ end
+ te_pkg::FULL_ADDRESS: begin
+ prdata_o[0] = configuration_q.full_address_en;
+ end
+ te_pkg::IMPLICIT_EXCEPTION: begin
+ prdata_o[0] = configuration_q.implicit_exception_en;
+ end
+ te_pkg::SIJUMP: begin
+ prdata_o[0] = configuration_q.sijump_en;
+ end
+ te_pkg::IMPLICIT_RETURN: begin
+ prdata_o[0] = configuration_q.implicit_return_en;
+ end
+ te_pkg::BRANCH_PREDICTION: begin
+ prdata_o[0] = configuration_q.branch_prediction_en;
+ end
+ te_pkg::JUMP_TARGET_CACHE: begin
+ prdata_o[0] = configuration_q.jump_target_cache_en;
+ end
+
+ `ifdef TE_ARCH64 // 64bits case
+ // FILTER
+ // cause
+ te_pkg::CAUSE_UPPER: begin
+ prdata_o[te_pkg::XLEN-1:0] = upper_cause_q;
+ end
+
+ te_pkg::CAUSE_LOWER: begin
+ prdata_o[te_pkg::XLEN-1:0] = lower_cause_q;
+ end
+
+ te_pkg::CAUSE_MATCH: begin
+ prdata_o[te_pkg::XLEN-1:0] = match_cause_q;
+ end
+
+ // tvec
+ te_pkg::TVEC_UPPER_L: begin // least significant bits
+ prdata_o = upper_tvec_q[31:0];
+ end
+
+ te_pkg::TVEC_UPPER_M: begin // most significant bits
+ prdata_o = upper_tvec_q[63:32];
+ end
+
+ te_pkg::TVEC_LOWER_L: begin // least significant bits
+ prdata_o = lower_tvec_q[31:0];
+ end
+
+ te_pkg::TVEC_LOWER_M: begin // most significant bits
+ prdata_o = lower_tvec_q[63:32];
+ end
+
+ te_pkg::TVEC_MATCH_L: begin // least significant bits
+ prdata_o = match_tvec_q[31:0];
+ end
+
+ te_pkg::TVEC_MATCH_M: begin // most significant bits
+ prdata_o = match_tvec_q[63:32];
+ end
+
+ // tval
+ te_pkg::TVAL_UPPER_L: begin // least significant bits
+ prdata_o = upper_tval_q[31:0];
+ end
+
+ te_pkg::TVAL_UPPER_M: begin // most significant bits
+ prdata_o = upper_tval_q[63:32];
+ end
+
+ te_pkg::TVAL_LOWER_L: begin // least significant bits
+ prdata_o = lower_tval_q[31:0];
+ end
+
+ te_pkg::TVAL_LOWER_M: begin // most significant bits
+ prdata_o = lower_tval_q[63:32];
+ end
+
+ te_pkg::TVAL_MATCH_L: begin // least significant bits
+ prdata_o = match_tval_q[31:0];
+ end
+
+ te_pkg::TVAL_MATCH_M: begin // most significant bits
+ prdata_o = match_tval_q[63:32];
+ end
+
+ // iaddr
+ te_pkg::IADDR_UPPER_L: begin // least significant bits
+ prdata_o = upper_iaddr_q[31:0];
+ end
+
+ te_pkg::IADDR_UPPER_M: begin // most significant bits
+ prdata_o = upper_iaddr_q[63:32];
+ end
+
+ te_pkg::IADDR_LOWER_L: begin // least significant bits
+ prdata_o = lower_iaddr_q[31:0];
+ end
+
+ te_pkg::IADDR_LOWER_M: begin // most significant bits
+ prdata_o = lower_iaddr_q[63:32];
+ end
+
+ te_pkg::IADDR_MATCH_L: begin // least significant bits
+ prdata_o = match_iaddr_q[31:0];
+ end
+
+ te_pkg::IADDR_MATCH_M: begin // most significant bits
+ prdata_o = match_iaddr_q[63:32];
+ end
+
+ `else // 32bits case
+ // FILTER
+ // cause
+ te_pkg::CAUSE_UPPER: begin
+ prdata_o[te_pkg::XLEN-1:0] = upper_cause_q;
+ end
+
+ te_pkg::CAUSE_LOWER: begin
+ prdata_o[te_pkg::XLEN-1:0] = lower_cause_q;
+ end
+
+ te_pkg::CAUSE_MATCH: begin
+ prdata_o[te_pkg::XLEN-1:0] = match_cause_d;
+ end
+
+ // tvec
+ te_pkg::TVEC_UPPER: begin
+ prdata_o = upper_tvec_q;
+ end
+
+ te_pkg::TVEC_LOWER: begin
+ prdata_o = lower_tvec_q;
+ end
+
+ te_pkg::TVEC_MATCH: begin
+ prdata_o = match_tvec_q;
+ end
+
+ // tval
+ te_pkg::TVAL_UPPER: begin
+ prdata_o = upper_tval_q;
+ end
+
+ te_pkg::TVAL_LOWER: begin
+ prdata_o = lower_tval_q;
+ end
+
+ te_pkg::TVAL_MATCH: begin
+ prdata_o = match_tval_q;
+ end
+
+ // iaddr
+ te_pkg::IADDR_UPPER: begin
+ prdata_o = upper_iaddr_q;
+ end
+
+ te_pkg::IADDR_LOWER: begin
+ prdata_o = lower_iaddr_q;
+ end
+
+ te_pkg::IADDR_MATCH: begin
+ prdata_o = match_iaddr_q;
+ end
+ `endif
+ endcase
+ end else if (write_access) begin
+
+
+ case (paddr_i[7:0])
+ // common cases
+ te_pkg::CAUSE_ENABLE_MODE: begin
+ cause_filter_d = pwdata_i[0];
+ cause_mode_d = pwdata_i[1];
+ end
+
+ te_pkg::TVEC_ENABLE_MODE: begin
+ tvec_filter_d = pwdata_i[0];
+ tvec_mode_d = pwdata_i[1];
+ end
+
+ te_pkg::TVAL_ENABLE_MODE: begin
+ tval_filter_d = pwdata_i[0];
+ tval_mode_d = pwdata_i[1];
+ end
+
+ te_pkg::PRIV_ENABLE_MODE: begin
+ priv_lvl_filter_d = pwdata_i[0];
+ priv_lvl_mode_d = pwdata_i[1];
+ end
+
+ te_pkg::IADDR_ENABLE_MODE: begin
+ iaddr_filter_d = pwdata_i[0];
+ iaddr_mode_d = pwdata_i[1];
+ end
+
+ // priv
+ te_pkg::PRIV_RANGE: begin
+ lower_priv_d = pwdata_i[te_pkg::PRIV_LEN-1:0];
+ upper_priv_d = pwdata_i[te_pkg::PRIV_LEN*2-1:te_pkg::PRIV_LEN];
+ end
+
+ te_pkg::PRIV_MATCH: begin
+ match_priv_d = pwdata_i[te_pkg::PRIV_LEN-1:0];
+ end
+
+ // TRACE MANAGEMENT
+ te_pkg::TRACE_STATE: begin
+ trace_activated_d = pwdata_i[0];
+ end
+
+ te_pkg::LOSSLESS_TRACE: begin
+ lossless_trace_d = pwdata_i[0];
+ end
+
+ te_pkg::SHALLOW_TRACE: begin
+ shallow_trace_d = pwdata_i[0];
+ end
+
+ // PACKET EMITTER
+ te_pkg::NO_TIME: begin
+ notime_d = pwdata_i[0];
+ end
+
+ te_pkg::NO_CONTEXT: begin
+ nocontext_d = pwdata_i[0];
+ end
+
+ te_pkg::DELTA_ADDRESS: begin
+ configuration_d.delta_address_en = pwdata_i[0];
+ end
+
+ te_pkg::FULL_ADDRESS: begin
+ configuration_d.full_address_en = pwdata_i[0];
+ end
+
+ te_pkg::IMPLICIT_EXCEPTION: begin
+ configuration_d.implicit_exception_en = pwdata_i[0];
+ end
+
+ te_pkg::SIJUMP: begin
+ configuration_d.sijump_en = pwdata_i[0];
+ end
+
+ te_pkg::IMPLICIT_RETURN: begin
+ configuration_d.implicit_return_en = pwdata_i[0];
+ end
+
+ te_pkg::BRANCH_PREDICTION: begin
+ configuration_d.branch_prediction_en = pwdata_i[0];
+ end
+
+ te_pkg::JUMP_TARGET_CACHE: begin
+ configuration_d.jump_target_cache_en = pwdata_i[0];
+ end
+
+ `ifdef TE_ARCH64
+ // cause
+ te_pkg::CAUSE_UPPER: begin
+ upper_cause_d = pwdata_i[te_pkg::XLEN-1:0];
+ end
+
+ te_pkg::CAUSE_LOWER: begin
+ lower_cause_d = pwdata_i[te_pkg::XLEN-1:0];
+ end
+
+ te_pkg::CAUSE_MATCH: begin
+ match_cause_d = pwdata_i[te_pkg::XLEN-1:0];
+ end
+
+ // tvec
+ te_pkg::TVEC_UPPER_L: begin // least significant bits
+ upper_tvec_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::TVEC_UPPER_M: begin // most significant bits
+ upper_tvec_d[63:32] = pwdata_i;
+ end
+
+ te_pkg::TVEC_LOWER_L: begin // least significant bits
+ lower_tvec_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::TVEC_LOWER_M: begin // most significant bits
+ lower_tvec_d[63:32] = pwdata_i;
+ end
+
+ te_pkg::TVEC_MATCH_L: begin // least significant bits
+ match_tvec_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::TVEC_MATCH_M: begin // most significant bits
+ match_tvec_d[63:32] = pwdata_i;
+ end
+
+ // tval
+ te_pkg::TVAL_UPPER_L: begin // least significant bits
+ upper_tval_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::TVAL_UPPER_M: begin // most significant bits
+ upper_tval_d[63:32] = pwdata_i;
+ end
+
+ te_pkg::TVAL_LOWER_L: begin // least significant bits
+ lower_tval_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::TVAL_LOWER_M: begin // most significant bits
+ lower_tval_d[63:32] = pwdata_i;
+ end
+
+ te_pkg::TVAL_MATCH_L: begin // least significant bits
+ match_tval_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::TVAL_MATCH_M: begin // most significant bits
+ match_tval_d[63:32] = pwdata_i;
+ end
+
+ // iaddr
+ te_pkg::IADDR_UPPER_L: begin // least significant bits
+ upper_iaddr_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::IADDR_UPPER_M: begin // most significant bits
+ upper_iaddr_d[63:32] = pwdata_i;
+ end
+
+ te_pkg::IADDR_LOWER_L: begin // least significant bits
+ lower_iaddr_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::IADDR_LOWER_M: begin // most significant bits
+ lower_iaddr_d[63:32] = pwdata_i;
+ end
+
+ te_pkg::IADDR_MATCH_L: begin // least significant bits
+ match_iaddr_d[31:0] = pwdata_i;
+ end
+
+ te_pkg::IADDR_MATCH_M: begin // most significant bits
+ match_iaddr_d[63:32] = pwdata_i;
+ end
+ `else // 32 bits case
+ // cause
+ te_pkg::CAUSE_UPPER: begin
+ upper_cause_d = pwdata_i[te_pkg::XLEN-1:0];
+ end
+
+ te_pkg::CAUSE_LOWER: begin
+ lower_cause_d = pwdata_i[te_pkg::XLEN-1:0];
+ end
+
+ te_pkg::CAUSE_MATCH: begin
+ match_cause_d = pwdata_i[te_pkg::XLEN-1:0];
+ end
+
+ // tvec
+ te_pkg::TVEC_UPPER: begin
+ upper_tvec_d = pwdata_i;
+ end
+
+ te_pkg::TVEC_LOWER: begin
+ lower_tvec_d = pwdata_i;
+ end
+
+ te_pkg::TVEC_MATCH: begin
+ match_tvec_d = pwdata_i;
+ end
+
+ // tval
+ te_pkg::TVAL_UPPER: begin
+ upper_tval_d = pwdata_i;
+ end
+
+ te_pkg::TVAL_LOWER: begin
+ lower_tval_d = pwdata_i;
+ end
+
+ te_pkg::TVAL_MATCH: begin
+ match_tval_d = pwdata_i;
+ end
+
+ // iaddr
+ te_pkg::IADDR_UPPER: begin
+ upper_iaddr_d = pwdata_i;
+ end
+
+ te_pkg::IADDR_LOWER: begin
+ lower_iaddr_d = pwdata_i;
+ end
+
+ te_pkg::IADDR_MATCH: begin
+ match_iaddr_d = pwdata_i;
+ end
+ `endif
+ endcase
+ end
+ end
+
+ // clock gating module
+ pulp_clock_gating i_clock_gating(
+ .clk_i (clk_i),
+ .en_i (trace_activated_o),
+ .test_en_i(test_enabled),
+ .clk_o (clk_gated)
+ );
+
+ // edge detector for trace_req_on_i
+ // turns on and off the tracing
+ edge_detect i_edge_detect_on(
+ .clk_i(clk_gated),
+ .rst_ni(rst_ni),
+ .d_i(trace_req_on_i),
+ .re_o(trace_req_on),
+ .fe_o()
+ );
+
+ // edge detector for trace_req_off_i
+ // turns on and off the tracing
+ edge_detect i_edge_detect_off(
+ .clk_i(clk_gated),
+ .rst_ni(rst_ni),
+ .d_i(trace_req_off_i),
+ .re_o(trace_req_off),
+ .fe_o()
+ );
+
+ always_ff @(posedge clk_i, negedge rst_ni) begin
+ if(~rst_ni) begin
+ trace_enable_q <= '1;
+ // storing config parameters
+ cause_filter_q <= '0;
+ upper_cause_q <= '0;
+ lower_cause_q <= '0;
+ match_cause_q <= '0;
+ cause_mode_q <= '0;
+ tvec_filter_q <= '0;
+ upper_tvec_q <= '0;
+ lower_tvec_q <= '0;
+ match_tvec_q <= '0;
+ tvec_mode_q <= '0;
+ tval_filter_q <= '0;
+ upper_tval_q <= '0;
+ lower_tval_q <= '0;
+ match_tval_q <= '0;
+ tval_mode_q <= '0;
+ priv_lvl_filter_q <= '0;
+ upper_priv_q <= '0;
+ lower_priv_q <= '0;
+ match_priv_q <= '0;
+ priv_lvl_mode_q <= '0;
+ iaddr_filter_q <= '0;
+ upper_iaddr_q <= '0;
+ lower_iaddr_q <= '0;
+ match_iaddr_q <= '0;
+ iaddr_mode_q <= '0;
+ configuration_q.delta_address_en <= '0; // delta address only one mandatory //FIXME changing this for debug
+ configuration_q.full_address_en <= '1;
+ configuration_q.implicit_exception_en <= '0;
+ configuration_q.sijump_en <= '0;
+ configuration_q.implicit_return_en <= '0;
+ configuration_q.branch_prediction_en <= '0;
+ configuration_q.jump_target_cache_en <= '0;
+ lossless_trace_q <= '0;
+ shallow_trace_q <= '0;
+ nocontext_q <= '1;
+ notime_q <= '0;
+ trace_activated_q <= '1;
+ setup_q <= '0;
+ end else begin
+ trace_enable_q <= trace_enable_d;
+ // storing config parameters
+ cause_filter_q <= cause_filter_d;
+ upper_cause_q <= upper_cause_d;
+ lower_cause_q <= lower_cause_d;
+ match_cause_q <= match_cause_d;
+ cause_mode_q <= cause_mode_d;
+ tvec_filter_q <= tvec_filter_d;
+ upper_tvec_q <= upper_tvec_d;
+ lower_tvec_q <= lower_tvec_d;
+ match_tvec_q <= match_tvec_d;
+ tvec_mode_q <= tvec_mode_d;
+ tval_filter_q <= tval_filter_d;
+ upper_tval_q <= upper_tval_d;
+ lower_tval_q <= lower_tval_d;
+ match_tval_q <= match_tval_d;
+ tval_mode_q <= tval_mode_d;
+ priv_lvl_filter_q <= priv_lvl_filter_d;
+ upper_priv_q <= upper_priv_d;
+ lower_priv_q <= lower_priv_d;
+ match_priv_q <= match_priv_d;
+ priv_lvl_mode_q <= priv_lvl_mode_d;
+ iaddr_filter_q <= iaddr_filter_d;
+ upper_iaddr_q <= upper_iaddr_d;
+ lower_iaddr_q <= lower_iaddr_d;
+ match_iaddr_q <= match_iaddr_d;
+ iaddr_mode_q <= iaddr_mode_d;
+ configuration_q <= configuration_d;
+ lossless_trace_q <= lossless_trace_d;
+ shallow_trace_q <= shallow_trace_d;
+ nocontext_q <= nocontext_d;
+ notime_q <= notime_d;
+ trace_activated_q <= trace_activated_d;
+ setup_q <= setup_d;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv
new file mode 100644
index 0000000000..d8c6f9a8aa
--- /dev/null
+++ b/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv
@@ -0,0 +1,106 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License. You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+// SPDX-License-Identifier: SHL-0.51
+
+// Author: Umberto Laghi
+// Contact: umberto.laghi2@unibo.it
+// Github: @ubolakes
+
+/* RESYNC COUNTER */
+/*
+It keeps track of the emitted packets or cycles elapsed,
+operational mode and threshold are set by the user.
+
+It produces a signal when the counter reaches the specified
+threshold and it remains to 1 until it receives a reset signal.
+
+In packed mode: the packets that exceeds the defined threshold
+are discarded, because they belong to a pre-resync period.
+Packets received while the counter is requesting a resync are
+ignored.
+*/
+
+module te_resync_counter #(
+ parameter N = 1,
+ parameter MODE = te_pkg::CYCLE_MODE, // counts cycles as default
+ parameter MAX_VALUE = 16'hFFFF // default max value, can be personalized
+ )
+ (
+ input logic clk_i,
+ input logic rst_ni,
+
+ input logic trace_enabled_i, // it comes from filter
+ input logic [N-1:0] packet_emitted_i,
+ input logic resync_rst_i,
+
+ output logic gt_resync_max_o, // greater than the max value, in reality MAX_VALUE
+ output logic et_resync_max_o // equals to the max value, in reality MAX_VALUE-1
+ );
+
+ /*
+ The packets that exceeds the defined threshold are discarded,
+ because they belong to a pre-resync period.
+ Packets received while the counter is requesting a resync are
+ ignored.
+ */
+
+ // signals declaration
+ logic [$clog2(MAX_VALUE):0] counter_d, counter_q;
+ logic [$clog2(N):0] n_packets;
+ logic overflow;
+
+ // assignments
+ // both for packet and cycle mode
+ assign et_resync_max_o = counter_d == MAX_VALUE;
+ assign gt_resync_max_o = counter_d > MAX_VALUE && ~resync_rst_i;
+
+ always_comb begin
+ // init
+ counter_d = counter_q;
+ n_packets = '0;
+
+ // packet mode
+ if (MODE == te_pkg::PACKET_MODE && trace_enabled_i) begin
+ // counting the packets received
+ for (int i = 0; i < N; i++) begin
+ if (packet_emitted_i[i]) begin
+ n_packets += 1;
+ end
+ end
+
+ // summing the packets counted
+ for (int i = 0; i < n_packets; i++) begin
+ if (counter_d <= MAX_VALUE) begin
+ counter_d += 1;
+ end
+ end
+ end
+
+ // cycle mode
+ if (MODE == te_pkg::CYCLE_MODE && trace_enabled_i && counter_d <= MAX_VALUE) begin
+ counter_d += 1;
+ end
+
+ // synchronous reset
+ if (resync_rst_i) begin
+ counter_d = '0;
+ end
+ end
+
+
+ always_ff @(posedge clk_i, negedge rst_ni) begin
+ if (~rst_ni) begin
+ counter_q <= '0;
+ end else begin
+ counter_q <= counter_d;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/corev_apu/openpiton/ariane_verilog_wrap.sv b/corev_apu/openpiton/ariane_verilog_wrap.sv
index 5b8e574421..15933b858b 100644
--- a/corev_apu/openpiton/ariane_verilog_wrap.sv
+++ b/corev_apu/openpiton/ariane_verilog_wrap.sv
@@ -21,7 +21,7 @@ module ariane_verilog_wrap
parameter int unsigned BHTEntries = 128,
// debug module base address
parameter logic [63:0] DmBaseAddress = 64'h0,
- // swap endianess in l15 adapter
+ // swap endianness in l15 adapter
parameter bit SwapEndianess = 1,
// PMA configuration
// idempotent region
diff --git a/corev_apu/openpiton/bootrom/linux/src/spi.c b/corev_apu/openpiton/bootrom/linux/src/spi.c
index c574f59cf6..fa5b53f416 100644
--- a/corev_apu/openpiton/bootrom/linux/src/spi.c
+++ b/corev_apu/openpiton/bootrom/linux/src/spi.c
@@ -115,7 +115,7 @@ int spi_write_bytes(uint8_t *bytes, uint32_t len, uint8_t *ret)
for (int i = 0; i < len;)
{
status = read_reg(SPI_STATUS_REG);
- if ((status & 0x1) != 0x1) // recieve fifo not empty
+ if ((status & 0x1) != 0x1) // receive fifo not empty
{
ret[i++] = read_reg(SPI_RECEIVE_REG);
}
diff --git a/corev_apu/src/ariane.sv b/corev_apu/src/ariane.sv
index fec7854b31..24432248f4 100644
--- a/corev_apu/src/ariane.sv
+++ b/corev_apu/src/ariane.sv
@@ -13,19 +13,38 @@
// Description: Ariane Top-level module
`include "cvxif_types.svh"
-`include "axi_types.svh"
module ariane import ariane_pkg::*; #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
- parameter type rvfi_probes_t = logic,
+ parameter type rvfi_probes_instr_t = logic,
+ parameter type rvfi_probes_csr_t = logic,
+ parameter type rvfi_probes_t = struct packed {
+ logic csr;
+ logic instr;
+ },
+ // CVXIF Types
+ localparam type readregflags_t = `READREGFLAGS_T(CVA6Cfg),
+ localparam type writeregflags_t = `WRITEREGFLAGS_T(CVA6Cfg),
+ localparam type id_t = `ID_T(CVA6Cfg),
+ localparam type hartid_t = `HARTID_T(CVA6Cfg),
+ localparam type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t),
+ localparam type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg),
+ localparam type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartid_t, id_t),
+ localparam type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t),
+ localparam type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t),
+ localparam type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t),
+ localparam type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t),
+ localparam type cvxif_req_t = `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_t, x_commit_t),
+ localparam type cvxif_resp_t = `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t),
// AXI Types
- localparam type axi_ar_chan_t = `AXI_AR_CHAN_T(CVA6Cfg),
- localparam type axi_aw_chan_t = `AXI_AW_CHAN_T(CVA6Cfg),
- localparam type axi_w_chan_t = `AXI_W_CHAN_T(CVA6Cfg),
- localparam type axi_b_chan_t = `AXI_B_CHAN_T(CVA6Cfg),
- localparam type axi_r_chan_t = `AXI_R_CHAN_T(CVA6Cfg),
- localparam type noc_req_t = `AXI_REQ_T(CVA6Cfg),
- localparam type noc_resp_t = `AXI_RSP_T(CVA6Cfg)
+ parameter int unsigned AxiAddrWidth = ariane_axi::AddrWidth,
+ parameter int unsigned AxiDataWidth = ariane_axi::DataWidth,
+ parameter int unsigned AxiIdWidth = ariane_axi::IdWidth,
+ parameter type axi_ar_chan_t = ariane_axi::ar_chan_t,
+ parameter type axi_aw_chan_t = ariane_axi::aw_chan_t,
+ parameter type axi_w_chan_t = ariane_axi::w_chan_t,
+ parameter type noc_req_t = ariane_axi::req_t,
+ parameter type noc_resp_t = ariane_axi::resp_t
) (
input logic clk_i,
input logic rst_ni,
@@ -47,29 +66,32 @@ module ariane import ariane_pkg::*; #(
input noc_resp_t noc_resp_i
);
- // CVXIF Types
- localparam type readregflags_t = `READREGFLAGS_T(CVA6Cfg);
- localparam type writeregflags_t = `WRITEREGFLAGS_T(CVA6Cfg);
- localparam type id_t = `ID_T(CVA6Cfg);
- localparam type hartid_t = `HARTID_T(CVA6Cfg);
- localparam type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t);
- localparam type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg);
- localparam type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartit_t, id_t);
- localparam type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t);
- localparam type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t);
- localparam type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t);
- localparam type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t);
- localparam type cvxif_req_t = `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t);
- localparam type cvxif_resp_t = `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t);
-
cvxif_req_t cvxif_req;
cvxif_resp_t cvxif_resp;
cva6 #(
- .CVA6Cfg ( CVA6Cfg ),
- .rvfi_probes_t ( rvfi_probes_t ),
- .noc_req_t ( noc_req_t ),
- .noc_resp_t ( noc_resp_t )
+ .CVA6Cfg ( CVA6Cfg ),
+ //.rvfi_probes_instr_t ( rvfi_probes_instr_t ),
+ //.rvfi_probes_csr_t ( rvfi_probes_csr_t ),
+ .rvfi_probes_t ( rvfi_probes_t ),
+ //.axi_ar_chan_t (axi_ar_chan_t),
+ //.axi_aw_chan_t (axi_aw_chan_t),
+ //.axi_w_chan_t (axi_w_chan_t),
+ .noc_req_t (noc_req_t),
+ .noc_resp_t (noc_resp_t)
+ //.readregflags_t (readregflags_t),
+ //.writeregflags_t (writeregflags_t),
+ //.id_t (id_t),
+ //.hartid_t (hartid_t),
+ //.x_compressed_req_t (x_compressed_req_t),
+ //.x_compressed_resp_t (x_compressed_resp_t),
+ //.x_issue_req_t (x_issue_req_t),
+ //.x_issue_resp_t (x_issue_resp_t),
+ //.x_register_t (x_register_t),
+ //.x_commit_t (x_commit_t),
+ //.x_result_t (x_result_t),
+ //.cvxif_req_t (cvxif_req_t),
+ //.cvxif_resp_t (cvxif_resp_t)
) i_cva6 (
.clk_i ( clk_i ),
.rst_ni ( rst_ni ),
@@ -86,6 +108,8 @@ module ariane import ariane_pkg::*; #(
.noc_resp_i ( noc_resp_i )
);
+
+
if (CVA6Cfg.CvxifEn) begin: gen_cvxif
if (CVA6Cfg.CoproType == config_pkg::COPRO_EXAMPLE) begin: gen_COPRO_EXAMPLE
cvxif_example_coprocessor #(
diff --git a/corev_apu/tb/ariane_gate_tb.sv b/corev_apu/tb/ariane_gate_tb.sv
index 958a56fc14..d077443296 100644
--- a/corev_apu/tb/ariane_gate_tb.sv
+++ b/corev_apu/tb/ariane_gate_tb.sv
@@ -24,10 +24,13 @@ import uvm_pkg::*;
`timescale 1ns/1ns
+`ifndef READ_ELF_T
+`define READ_ELF_T
import "DPI-C" function void read_elf(input string filename);
import "DPI-C" function byte get_section(output longint address, output longint len);
import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]);
import "DPI-C" function string getenv(input string env_name);
+`endif
module ariane_gate_tb;
diff --git a/corev_apu/tb/ariane_soc_pkg.sv b/corev_apu/tb/ariane_soc_pkg.sv
index d20b6a6b8b..7785485310 100644
--- a/corev_apu/tb/ariane_soc_pkg.sv
+++ b/corev_apu/tb/ariane_soc_pkg.sv
@@ -29,12 +29,12 @@ package ariane_soc;
PLIC = 6,
CLINT = 7,
ROM = 8,
- Debug = 9
+ Debug = 9,
+ HPS = 10
} axi_slaves_t;
localparam NB_PERIPHERALS = Debug + 1;
-
localparam logic[63:0] DebugLength = 64'h1000;
localparam logic[63:0] ROMLength = 64'h10000;
localparam logic[63:0] CLINTLength = 64'hC0000;
@@ -44,6 +44,7 @@ package ariane_soc;
localparam logic[63:0] SPILength = 64'h800000;
localparam logic[63:0] EthernetLength = 64'h10000;
localparam logic[63:0] GPIOLength = 64'h1000;
+ localparam logic[63:0] HPSLength = 64'h800000;
`ifdef NEXYS_VIDEO
localparam logic[63:0] DRAMLength = 64'h20000000; // 512MByte of DDR on Nexys video board
`else
@@ -63,7 +64,8 @@ package ariane_soc;
SPIBase = 64'h2000_0000,
EthernetBase = 64'h3000_0000,
GPIOBase = 64'h4000_0000,
- DRAMBase = 64'h8000_0000
+ DRAMBase = 64'h8000_0000,
+ HPSBase = 64'hFF80_0000
} soc_bus_start_t;
localparam NrRegion = 1;
diff --git a/corev_apu/tb/ariane_tb.cpp b/corev_apu/tb/ariane_tb.cpp
index 8de0c5b20f..3653eaa516 100644
--- a/corev_apu/tb/ariane_tb.cpp
+++ b/corev_apu/tb/ariane_tb.cpp
@@ -120,7 +120,7 @@ class preload_aware_dtm_t : public dtm_t {
preload_aware_dtm_t(int argc, char **argv) : dtm_t(argc, argv) {}
bool is_address_preloaded(addr_t taddr, size_t len) override { return true; }
// We do not want to reset the hart here as the reset function in `dtm_t` seems to disregard
- // the privilege level and in general does not perform propper reset (despite the name).
+ // the privilege level and in general does not perform proper reset (despite the name).
// As all our binaries in preloading will always start at the base of DRAM this should not
// be such a big problem.
void reset() {}
@@ -351,7 +351,7 @@ int main(int argc, char **argv) {
try {
read_section_void(addr, (void *) MEM_USER , mem_size);
} catch (...){
- std::cerr << "No user memory instanciated ...\n";
+ std::cerr << "No user memory instantiated ...\n";
}
}
diff --git a/corev_apu/tb/ariane_testharness.sv b/corev_apu/tb/ariane_testharness.sv
index 04530ff45f..e4e3236392 100644
--- a/corev_apu/tb/ariane_testharness.sv
+++ b/corev_apu/tb/ariane_testharness.sv
@@ -15,6 +15,7 @@
`include "axi/assign.svh"
`include "rvfi_types.svh"
+`include "iti_types.svh"
`ifdef VERILATOR
`include "custom_uvm_macros.svh"
@@ -46,6 +47,8 @@ module ariane_testharness #(
localparam type rvfi_instr_t = `RVFI_INSTR_T(CVA6Cfg);
localparam type rvfi_csr_elmt_t = `RVFI_CSR_ELMT_T(CVA6Cfg);
localparam type rvfi_csr_t = `RVFI_CSR_T(CVA6Cfg, rvfi_csr_elmt_t);
+ localparam type rvfi_to_iti_t = `RVFI_TO_ITI_T(CVA6Cfg);
+ localparam type iti_to_encoder_t = `ITI_TO_ENCODER_T(CVA6Cfg);
// RVFI PROBES
localparam type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg);
@@ -625,10 +628,16 @@ module ariane_testharness #(
rvfi_probes_t rvfi_probes;
rvfi_csr_t rvfi_csr;
rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr;
+ rvfi_to_iti_t rvfi_to_iti;
+ iti_to_encoder_t iti_to_encoder;
ariane #(
.CVA6Cfg ( CVA6Cfg ),
- .rvfi_probes_t ( rvfi_probes_t )
+ .rvfi_probes_instr_t ( rvfi_probes_instr_t ),
+ .rvfi_probes_csr_t ( rvfi_probes_csr_t ),
+ .rvfi_probes_t ( rvfi_probes_t ),
+ .noc_req_t ( ariane_axi::req_t ),
+ .noc_resp_t ( ariane_axi::resp_t )
) i_ariane (
.clk_i ( clk_i ),
.rst_ni ( ndmreset_n ),
@@ -668,19 +677,133 @@ module ariane_testharness #(
end
end
+ cva6_iti #(
+ .CVA6Cfg (CVA6Cfg),
+ .CAUSE_LEN (iti_pkg::CAUSE_LEN),
+ .ITYPE_LEN (iti_pkg::ITYPE_LEN),
+ .IRETIRE_LEN (iti_pkg::IRETIRE_LEN),
+ .block_mode(0),
+ .rvfi_to_iti_t(rvfi_to_iti_t),
+ .iti_to_encoder_t(iti_to_encoder_t)
+ ) i_cva6_iti (
+ .clk_i (clk_i),
+ .rst_ni (ndmreset_n),
+ // inputs from rvfi
+ .valid_i(rvfi_to_iti.valid),
+ .rvfi_to_iti_i(rvfi_to_iti),
+ .valid_o(),
+ .iti_to_encoder_o(iti_to_encoder)
+ );
+
+ logic packet_valid;
+ te_pkg::it_packet_type_e [0:0] packet_type;
+ logic [te_pkg::P_LEN-1:0] packet_length;
+ logic [te_pkg::PAYLOAD_LEN-1:0] packet_payload;
+
+ rv_tracer #(
+ .N(1),
+ .ONLY_BRANCHES(1)
+ ) i_encoder(
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .valid_i (iti_to_encoder.valid),
+ .itype_i (iti_to_encoder.itype),
+ .cause_i (iti_to_encoder.cause),
+ .tval_i (iti_to_encoder.tval),
+ .priv_i (iti_to_encoder.priv),
+ .iaddr_i (iti_to_encoder.iaddr),
+ .iretire_i (iti_to_encoder.iretire),
+ .ilastsize_i (iti_to_encoder.ilastsize),
+ .time_i (iti_to_encoder.cycles),
+ .tvec_i ('0),
+ .epc_i ('0),
+ .encapsulator_ready_i('1),
+ .paddr_i ('0),
+ .pwrite_i ('0),
+ .psel_i ('0),
+ .penable_i ('0),
+ .pwdata_i ('0),
+ .packet_valid_o (packet_valid),
+ .packet_type_o (packet_type),
+ .packet_length_o (packet_length),
+ .packet_payload_o (packet_payload),
+ .stall_o (),
+ .pready_o (),
+ .prdata_o ()
+ );
+ logic encap_valid;
+ encap_pkg::encap_fifo_entry_s encap_fifo_entry_i;
+ encap_pkg::encap_fifo_entry_s encap_fifo_entry_o;
+ logic encap_fifo_full;
+ logic encap_fifo_empty;
+ logic encap_fifo_pop;
+
+ encapsulator i_encapsulator (
+ .clk_i (clk_i),
+ .valid_i (packet_valid),
+ .packet_length_i (packet_length),
+ .flow_i ('0),
+ .timestamp_present_i('1),
+ //.srcid_i(),
+ .timestamp_i (rvfi_to_iti.cycles),
+ //.type_i(),
+ .trace_payload_i (packet_payload),
+ .valid_o (encap_valid),
+ .encap_fifo_entry_o (encap_fifo_entry_i)
+ );
+
+ fifo_v3 # (
+ .DEPTH(16),
+ .dtype(encap_pkg::encap_fifo_entry_s)
+ ) i_fifo_encap (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .flush_i ('0),
+ .testmode_i('0),
+ .full_o (encap_fifo_full),
+ .empty_o (encap_fifo_empty),
+ .usage_o (),
+ .data_i (encap_fifo_entry_i),
+ .push_i (encap_valid),
+ .data_o (encap_fifo_entry_o),
+ .pop_i (encap_fifo_pop)
+ );
+ localparam DATA_LEN = 8;
+
+ logic slicer_valid;
+ logic [DATA_LEN-1:0] slice;
+ logic [$clog2(DATA_LEN)-4:0] valid_bytes;
+
+ slicer_DPTI #(
+ .SLICE_LEN(DATA_LEN),
+ .NO_TIME ('0)
+ ) i_slicer (
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
+ .valid_i (!encap_fifo_empty),
+ .encap_fifo_entry_i(encap_fifo_entry_o),
+ .fifo_full_i ('0), // usrFull DPTI in ariane_xilinx
+ .valid_o (slicer_valid),
+ .slice_o (slice),
+ .done_o (encap_fifo_pop)
+ );
cva6_rvfi #(
.CVA6Cfg (CVA6Cfg),
.rvfi_instr_t(rvfi_instr_t),
.rvfi_csr_t(rvfi_csr_t),
- .rvfi_probes_t(rvfi_probes_t)
+ .rvfi_probes_instr_t(rvfi_probes_instr_t),
+ .rvfi_probes_csr_t(rvfi_probes_csr_t),
+ .rvfi_probes_t(rvfi_probes_t),
+ .rvfi_to_iti_t(rvfi_to_iti_t)
) i_cva6_rvfi (
- .clk_i (clk_i),
- .rst_ni (rst_ni),
+ .clk_i (clk_i),
+ .rst_ni (rst_ni),
.rvfi_probes_i(rvfi_probes),
- .rvfi_instr_o(rvfi_instr),
- .rvfi_csr_o(rvfi_csr)
+ .rvfi_instr_o (rvfi_instr),
+ .rvfi_to_iti_o (rvfi_to_iti),
+ .rvfi_csr_o (rvfi_csr)
);
rvfi_tracer #(
diff --git a/corev_apu/tb/common/mock_uart.sv b/corev_apu/tb/common/mock_uart.sv
index 0124ea714e..839b41f0e1 100644
--- a/corev_apu/tb/common/mock_uart.sv
+++ b/corev_apu/tb/common/mock_uart.sv
@@ -10,7 +10,7 @@
//
// Author: Florian Zaruba, ETH Zurich
// Date: 28/09/2018
-// Description: Mock replacement for UART in testbench (not synthesiesable!)
+// Description: Mock replacement for UART in testbench (not synthesizable!)
module mock_uart (
input logic clk_i,
diff --git a/corev_apu/tb/common/tb_amoport.sv b/corev_apu/tb/common/tb_amoport.sv
index 18a59636ff..604f211fc9 100644
--- a/corev_apu/tb/common/tb_amoport.sv
+++ b/corev_apu/tb/common/tb_amoport.sv
@@ -88,7 +88,7 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #(
else
size = 'h2;
- // For LRs/SCs, choose from only 4 adresses,
+ // For LRs/SCs, choose from only 4 addresses,
// so that valid LR/SC combinations become more likely.
// Note: AMOs to address 0 are not supported in axi_riscv_atomics module
// so we start at 8 (for alignment purposes)
@@ -97,7 +97,7 @@ program tb_amoport import ariane_pkg::*; import tb_pkg::*; #(
else
void'(randomize(paddr) with {paddr >= 8; paddr < (MemWords<<$clog2(CVA6Cfg.XLEN/8));});
- // Align adress
+ // Align address
if (size == 2)
paddr[1:0] = '0;
else
diff --git a/corev_apu/tb/common/tb_dcache_pkg.sv b/corev_apu/tb/common/tb_dcache_pkg.sv
index 7584d81a86..0597824453 100644
--- a/corev_apu/tb/common/tb_dcache_pkg.sv
+++ b/corev_apu/tb/common/tb_dcache_pkg.sv
@@ -31,7 +31,7 @@ package tb_pkg;
time CLK_LO = 5ns; // set clock low time
time CLK_PERIOD = CLK_HI+CLK_LO;
time APPL_DEL = 2ns; // set stimuli application delay
- time ACQ_DEL = 8ns; // set response aquisition delay
+ time ACQ_DEL = 8ns; // set response acquisition delay
parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation...
diff --git a/corev_apu/tb/common/tb_writeport.sv b/corev_apu/tb/common/tb_writeport.sv
index 46cb362875..82cc10bbee 100644
--- a/corev_apu/tb/common/tb_writeport.sv
+++ b/corev_apu/tb/common/tb_writeport.sv
@@ -152,7 +152,7 @@ program tb_writeport import tb_pkg::*; import ariane_pkg::*; #(
dut_req_port_o.data_wdata = 'x;
endtask : genSeqWrite
- // Repeadedly write to the same address
+ // Repeatedly write to the same address
task automatic genConstWrite();
automatic logic [CVA6Cfg.XLEN-1:0] val;
paddr = CachedAddrBeg;
diff --git a/corev_apu/tb/dpi/elfloader.cc b/corev_apu/tb/dpi/elfloader.cc
index f137015a5e..8cdf6a4cbc 100644
--- a/corev_apu/tb/dpi/elfloader.cc
+++ b/corev_apu/tb/dpi/elfloader.cc
@@ -50,7 +50,7 @@ extern "C" char get_section (long long* address, long long* len) {
}
extern "C" void read_section (long long address, const svOpenArrayHandle buffer) {
- // get actual poitner
+ // get actual pointer
void* buf = svGetArrayPtr(buffer);
// check that the address points to a section
assert(mems.count(address) > 0);
diff --git a/corev_apu/tb/rvfi_tracer.sv b/corev_apu/tb/rvfi_tracer.sv
index 13d7183fa6..c680f8cd50 100644
--- a/corev_apu/tb/rvfi_tracer.sv
+++ b/corev_apu/tb/rvfi_tracer.sv
@@ -69,6 +69,39 @@ module rvfi_tracer #(
logic[31:0] end_of_test_q;
logic[31:0] end_of_test_d;
+ function automatic logic fp_instr_writes_gpr(logic [31:0] insn);
+ logic [6:0] opcode;
+ logic [4:0] funct5;
+ logic [2:0] rm;
+
+ opcode = insn[6:0];
+ funct5 = insn[31:27];
+ rm = insn[14:12];
+
+ if (opcode != riscv::OpcodeOpFp) begin
+ return 1'b0;
+ end
+
+ if (funct5 == 5'b11000) begin
+ return 1'b1;
+ end
+
+ if (funct5 == 5'b10100) begin
+ return 1'b1;
+ end
+
+ if (funct5 == 5'b11100) begin
+ if ((rm == 3'b000) || (rm == 3'b001)) begin
+ return 1'b1;
+ end
+ if (CVA6Cfg.XF16ALT && ((rm == 3'b100) || (rm == 3'b101))) begin
+ return 1'b1;
+ end
+ end
+
+ return 1'b0;
+ endfunction
+
assign end_of_test_o = end_of_test_d;
always_ff @(posedge clk_i) begin
@@ -77,6 +110,7 @@ module rvfi_tracer #(
pc64 = {{CVA6Cfg.XLEN-CVA6Cfg.VLEN{rvfi_i[i].pc_rdata[CVA6Cfg.VLEN-1]}}, rvfi_i[i].pc_rdata};
// print the instruction information if the instruction is valid or a trap is taken
if (rvfi_i[i].valid) begin
+ logic dest_is_fp;
// Instruction information
if (rvfi_i[i].intr[2]) begin
$fwrite(f, "core INTERRUPT 0: 0x%h (0x%h) DASM(%h)\n",
@@ -96,6 +130,7 @@ module rvfi_tracer #(
end
// Decode instruction to know if destination register is FP register.
// Handle both uncompressed and compressed instructions.
+ dest_is_fp = 1'b0;
if ( rvfi_i[i].insn[6:0] == 7'b1001111 ||
rvfi_i[i].insn[6:0] == 7'b1001011 ||
rvfi_i[i].insn[6:0] == 7'b1000111 ||
@@ -106,21 +141,29 @@ module rvfi_tracer #(
&& rvfi_i[i].insn[31:26] != 6'b110000) ||
(rvfi_i[i].insn[0] == 1'b0 && ((rvfi_i[i].insn[15:13] == 3'b001 && CVA6Cfg.XLEN == 64) ||
(rvfi_i[i].insn[15:13] == 3'b011 && CVA6Cfg.XLEN == 32) ))) begin
+ if (fp_instr_writes_gpr(rvfi_i[i].insn)) begin
+ dest_is_fp = 1'b0;
+ end else begin
+ dest_is_fp = 1'b1;
+ end
+ end
+
+ if (dest_is_fp) begin
$fwrite(f, " f%d 0x%h", rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata);
end else if (rvfi_i[i].rd_addr != 0) begin
$fwrite(f, " x%d 0x%h", rvfi_i[i].rd_addr, rvfi_i[i].rd_wdata);
if (rvfi_i[i].mem_rmask != 0) begin
$fwrite(f, " mem 0x%h", rvfi_i[i].mem_addr);
end
- end else begin
- if (rvfi_i[i].mem_wmask != 0) begin
- $fwrite(f, " mem 0x%h 0x%h", rvfi_i[i].mem_addr, rvfi_i[i].mem_wdata);
- if (TOHOST_ADDR != '0 &&
- rvfi_i[i].mem_paddr == TOHOST_ADDR &&
- rvfi_i[i].mem_wdata[0] == 1'b1) begin
- end_of_test_q <= rvfi_i[i].mem_wdata[31:0];
- $display("*** [rvfi_tracer] INFO: Simulation terminated after %d cycles!\n", cycles);
- end
+ end
+ // Handle memory writes (including for AMO instructions which have both rd and mem_wmask)
+ if (rvfi_i[i].mem_wmask != 0) begin
+ $fwrite(f, " mem 0x%h 0x%h", rvfi_i[i].mem_addr, rvfi_i[i].mem_wdata);
+ if (TOHOST_ADDR != '0 &&
+ rvfi_i[i].mem_paddr == TOHOST_ADDR &&
+ rvfi_i[i].mem_wdata[0] == 1'b1) begin
+ end_of_test_q <= rvfi_i[i].mem_wdata[31:0];
+ $display("*** [rvfi_tracer] INFO: Simulation terminated after %d cycles!\n", cycles);
end
end
$fwrite(f, "\n");
diff --git a/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv b/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv
index 994190e314..300c8d1f8e 100644
--- a/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv
+++ b/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv
@@ -151,7 +151,7 @@ module mem_emul import ariane_pkg::*; import wt_cache_pkg::*; #(
infifo_data.rtype = ICACHE_INV_REQ;
// since we do not keep a mirror tag table here,
- // we allways invalidate all ways of the aliased index.
+ // we always invalidate all ways of the aliased index.
// this is not entirely correct and will produce
// too many invalidations
infifo_data.inv.idx = rand_addr_q[CVA6Cfg.ICACHE_INDEX_WIDTH-1:0];
diff --git a/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv b/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv
index ae461862ab..488d4713a9 100644
--- a/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv
+++ b/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv
@@ -30,7 +30,7 @@ package tb_pkg;
time CLK_HI = 5ns; // set clock high time
time CLK_LO = 5ns; // set clock low time
time APPL_DEL = 2ns; // set stimuli application delay
- time ACQ_DEL = 8ns; // set response aquisition delay
+ time ACQ_DEL = 8ns; // set response acquisition delay
parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation...
diff --git a/corev_apu/tb/tb_serdiv/hdl/tb.sv b/corev_apu/tb/tb_serdiv/hdl/tb.sv
index a01a1bfe3b..7590353946 100644
--- a/corev_apu/tb/tb_serdiv/hdl/tb.sv
+++ b/corev_apu/tb/tb_serdiv/hdl/tb.sv
@@ -188,7 +188,7 @@ module tb;
$display("TB> response acquisition started");
///////////////////////////////////////////////
- // acquisiton and verification
+ // acquisition and verification
///////////////////////////////////////////////
repeat(4) begin
diff --git a/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv b/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv
index 9767d472e2..15ff02e819 100644
--- a/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv
+++ b/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv
@@ -33,7 +33,7 @@ package tb_pkg;
time CLK_LO = 5ns; // set clock low time
time CLK_PERIOD = CLK_HI+CLK_LO;
time APPL_DEL = 2ns; // set stimuli application delay
- time ACQ_DEL = 8ns; // set response aquisition delay
+ time ACQ_DEL = 8ns; // set response acquisition delay
parameter ERROR_CNT_STOP_LEVEL = 1; // use 1 for debugging. 0 runs the complete simulation...
diff --git a/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv b/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv
index c6c7b9a2d9..1b1aafcfaf 100644
--- a/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv
+++ b/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv
@@ -44,6 +44,8 @@ package cva6_config_pkg;
localparam CVA6ConfigDcacheLineWidth = 128;
localparam CVA6ConfigDcacheIdWidth = 1;
+ localparam CVA6ConfigMemTidWidth = 2;
+
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
@@ -87,6 +89,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
+ MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
RVF: bit'(CVA6ConfigRVF),
RVD: bit'(CVA6ConfigRVF),
@@ -139,10 +142,10 @@ package cva6_config_pkg;
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
- DataUserEn: bit'(CVA6ConfigDataUserEn),
+ DataUserEn: unsigned'(CVA6ConfigDataUserEn),
WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
- FetchUserEn: bit'(CVA6ConfigFetchUserEn),
+ FetchUserEn: unsigned'(CVA6ConfigFetchUserEn),
InstrTlbEntries: int'(2),
DataTlbEntries: int'(2),
UseSharedTlb: bit'(1),
diff --git a/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv b/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv
index e855c21010..7ccfbfac87 100644
--- a/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv
+++ b/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv
@@ -44,6 +44,8 @@ package cva6_config_pkg;
localparam CVA6ConfigDcacheLineWidth = 128;
localparam CVA6ConfigDcacheIdWidth = 1;
+ localparam CVA6ConfigMemTidWidth = 2;
+
localparam CVA6ConfigWtDcacheWbufDepth = 8;
localparam CVA6ConfigSuperscalarEn = 0;
@@ -87,6 +89,7 @@ package cva6_config_pkg;
AxiDataWidth: unsigned'(CVA6ConfigAxiDataWidth),
AxiIdWidth: unsigned'(CVA6ConfigAxiIdWidth),
AxiUserWidth: unsigned'(CVA6ConfigDataUserWidth),
+ MemTidWidth: unsigned'(CVA6ConfigMemTidWidth),
NrLoadBufEntries: unsigned'(CVA6ConfigNrLoadBufEntries),
RVF: bit'(CVA6ConfigRVF),
RVD: bit'(CVA6ConfigRVF),
@@ -139,10 +142,10 @@ package cva6_config_pkg;
DcacheByteSize: unsigned'(CVA6ConfigDcacheByteSize),
DcacheSetAssoc: unsigned'(CVA6ConfigDcacheSetAssoc),
DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
- DataUserEn: bit'(CVA6ConfigDataUserEn),
+ DataUserEn: unsigned'(CVA6ConfigDataUserEn),
WtDcacheWbufDepth: int'(CVA6ConfigWtDcacheWbufDepth),
FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
- FetchUserEn: bit'(CVA6ConfigFetchUserEn),
+ FetchUserEn: unsigned'(CVA6ConfigFetchUserEn),
InstrTlbEntries: int'(16),
DataTlbEntries: int'(16),
UseSharedTlb: bit'(0),
diff --git a/corev_apu/tb/tb_wb_dcache/hdl/tb.sv b/corev_apu/tb/tb_wb_dcache/hdl/tb.sv
index 37e992c220..9cba78c7db 100644
--- a/corev_apu/tb/tb_wb_dcache/hdl/tb.sv
+++ b/corev_apu/tb/tb_wb_dcache/hdl/tb.sv
@@ -318,7 +318,7 @@ module tb import ariane_pkg::*; import std_cache_pkg::*; import tb_pkg::*; #(
amo_op_a_u = $unsigned(amo_shadow[31:0]);
amo_op_b_u = $unsigned(amo_req_i.operand_b[31:0]);
- // The result that is expected to be returned by AMO and evantually to be stored in rd.
+ // The result that is expected to be returned by AMO and eventually to be stored in rd.
// For most AMOs, this is the previous memory content.
// RISC-V spec requires: "For RV64, 32-bit AMOs always sign-extend the value placed in rd."
amo_exp_result = amo_op_a;
diff --git a/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv b/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv
index f3279f3439..f47b77fa4e 100644
--- a/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv
+++ b/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv
@@ -279,7 +279,7 @@ module tb import ariane_pkg::*; import wt_cache_pkg::*; import tb_pkg::*; #()();
amo_op_a_u = $unsigned(amo_shadow[31:0]);
amo_op_b_u = $unsigned(amo_req_i.operand_b[31:0]);
- // The result that is expected to be returned by AMO and evantually to be stored in rd.
+ // The result that is expected to be returned by AMO and eventually to be stored in rd.
// For most AMOs, this is the previous memory content.
// RISC-V spec requires: "For RV64, 32-bit AMOs always sign-extend the value placed in rd."
amo_exp_result = amo_op_a;
diff --git a/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv b/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv
index f7094bcc7c..92f4c7cc60 100644
--- a/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv
+++ b/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv
@@ -159,7 +159,7 @@ module tb_mem import tb_pkg::*; import ariane_pkg::*; import wt_cache_pkg::*;#(
rand_addr_q <= lval<<3;
// with the current TB setup, we cannot invalidate a memory location if a write response to the same address is
- // in flight, since this could lead to an incosistent state between the real memory and the shadow memory view.
+ // in flight, since this could lead to an inconsistent state between the real memory and the shadow memory view.
// the workaround is not to overwrite shadow memory regions that are still pending in the write buffer
// this can be improved.
for(int k=0; k<8; k++) begin
@@ -205,7 +205,7 @@ module tb_mem import tb_pkg::*; import ariane_pkg::*; import wt_cache_pkg::*;#(
infifo_data.rtype = DCACHE_INV_REQ;
// since we do not keep a mirror tag table here,
- // we allways invalidate all ways of the aliased index.
+ // we always invalidate all ways of the aliased index.
// this is not entirely correct and will produce
// too many invalidations
infifo_data.inv.idx = rand_addr_q[CVA6Cfg.DCACHE_INDEX_WIDTH-1:0];
diff --git a/notes_mk b/notes_mk
new file mode 100644
index 0000000000..2ba8798f30
--- /dev/null
+++ b/notes_mk
@@ -0,0 +1,23 @@
+OBI_COMMITS :
+ - core/frontend/frontend.sv
+ - core/load_unit.sv
+ - core/store_buffer.sv
+ - core/cvxif_example/*
+ - verif/env/uvme/cvxif_vseq/*
+ - core/csr_regfile.sv
+ - core/cva6_fifo_v3.sv
+ - core/cvxif_example/compressed_instr_decoder.sv
+ - core/frontend/instr_queue.sv
+ - core/include/config_pkg.sv
+ - core/include/utils_macros.svh
+ - core/issue_read_operands.sv
+ - core/scoreboard.sv
+ - core/cva6_pipeline.sv
+ - core/include/build_config_pkg.sv
+ - core/commit_stage.sv
+ - core/controller.sv_lib
+ - core/decoder.sv
+
+ notes to angela :
+ id_type in cva6.sv : 35?
+ Probably there is something wrong with ID's.
diff --git a/verif/core-v-verif b/verif/core-v-verif
index b7a496781c..c81d54fdbf 160000
--- a/verif/core-v-verif
+++ b/verif/core-v-verif
@@ -1 +1 @@
-Subproject commit b7a496781c6906a0cd8996ad426d7c36010840cb
+Subproject commit c81d54fdbf891cac75c3ebf8b6f081894b63ad3f
diff --git a/verif/env/corev-dv/simulator.yaml b/verif/env/corev-dv/simulator.yaml
index 6aafabf62c..bd120533d3 100644
--- a/verif/env/corev-dv/simulator.yaml
+++ b/verif/env/corev-dv/simulator.yaml
@@ -61,3 +61,27 @@
cov_opts: >
-cm_dir /test.vdb -cm_log /dev/null -cm_name test__
+- tool: questa
+ compile:
+ cmd:
+ - "vlog -64
+ +incdir+$QUESTASIM_HOME/verilog_src/uvm-1.2/src
+ +incdir+
+ +incdir+
+ +acc
+ $QUESTASIM_HOME/verilog_src/uvm-1.2/src/uvm_pkg.sv
+ -f /../env/corev-dv/cva6-files.f
+ -sv
+ -mfcu -cuname design_cuname
+ +define+UVM_REGEX_NO_DPI
+ -writetoplevels /top.list
+ -l /compile.log "
+ - "vopt -64 -debug
+ +designfile -f /top.list
+ -l /optimize.log
+ -o design_opt"
+ sim:
+ cmd: >
+ vsim -64 -c -do /dv/questa_sim.tcl design_opt -sv_seed -sv_lib $QUESTASIM_HOME/uvm-1.2/linux_x86_64/uvm_dpi
+ cov_opts: >
+ -do "coverage save -onexit /cov.ucdb;"
diff --git a/verif/env/uvme/cov/uvme_exception_covg.sv b/verif/env/uvme/cov/uvme_exception_covg.sv
index a91e730ef6..a2466b69ba 100644
--- a/verif/env/uvme/cov/uvme_exception_covg.sv
+++ b/verif/env/uvme/cov/uvme_exception_covg.sv
@@ -34,7 +34,6 @@ covergroup cg_exception(
option.per_instance = 1;
option.name = name;
-`ifndef QUESTA
cp_exception: coverpoint instr.cause {
bins BREAKPOINT = {3} iff (instr.trap);
@@ -155,7 +154,6 @@ covergroup cg_exception(
ignore_bins IGN_EXC = !binsof(cp_exception) intersect{6};
ignore_bins IGN_ADD = binsof(cp_add_mem) intersect{0};
}
-`endif
endgroup : cg_exception
diff --git a/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv b/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv
index d9dfabe362..731190b743 100644
--- a/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv
+++ b/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv
@@ -21,7 +21,14 @@ covergroup cg_interrupt(
option.name = name;
cp_interrupt_req : coverpoint req_item.interrupt_vector {
- bins INTERRUPTS[] = {[0:$]} with (item inside {[0:(2**(num_irq_supported))-1]});
+ // FIXME: Tanuj Khandelwal
+ // Questa is crashing on this CG
+ // Hence it has been changed a little to make it pass
+ `ifndef QUESTA
+ bins INTERRUPTS[] = {[0:$]} with (item inside {[0:((2**(num_irq_supported))-1)]});
+ `else
+ bins INTERRUPTS[] = {[0:((2**(num_irq_supported))-1)]};
+ `endif
}
endgroup: cg_interrupt
diff --git a/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv b/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv
index 6663accf23..252925ca5d 100644
--- a/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv
+++ b/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv
@@ -64,7 +64,7 @@ class uvma_interrupt_mon_c extends uvm_monitor;
endclass : uvma_interrupt_mon_c
-function uvma_interrupt_mon_c::new(string name = "uvma_interrupt_mon", uvm_component parent);
+function uvma_interrupt_mon_c::new(string name = "uvma_interrupt_mon", uvm_component parent = null);
super.new(name, parent);
endfunction
diff --git a/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv b/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv
index 0a08d68af4..1f3cad0e0b 100644
--- a/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv
+++ b/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv
@@ -16,7 +16,7 @@
`include "uvm_macros.svh"
`include "uvml_hrtbt_macros.sv"
`include "uvma_interrupt_macros.sv"
-
+`include "uvma_axi_macros.sv"
/**
* Encapsulates all the types needed for an UVM agent capable of driving and/or
* monitoring Clock & Reset.
diff --git a/verif/env/uvme/uvme_cva6_cfg.sv b/verif/env/uvme/uvme_cva6_cfg.sv
index c8b9f99175..9d63c1c345 100644
--- a/verif/env/uvme/uvme_cva6_cfg.sv
+++ b/verif/env/uvme/uvme_cva6_cfg.sv
@@ -49,7 +49,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
rand uvma_obi_memory_cfg_c obi_memory_amo_cfg;
rand uvma_obi_memory_cfg_c obi_memory_load_cfg;
rand uvma_obi_memory_cfg_c obi_memory_zcmt_cfg;
- //rand uvma_obi_memory_cfg_c obi_memory_mmu_ptw_cfg;
+ rand uvma_obi_memory_cfg_c obi_memory_mmu_ptw_cfg;
rand uvma_rvfi_cfg_c#(ILEN,XLEN) rvfi_cfg;
rand uvma_isacov_cfg_c isacov_cfg;
@@ -104,7 +104,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
`uvm_field_object(obi_memory_amo_cfg, UVM_DEFAULT)
`uvm_field_object(obi_memory_load_cfg, UVM_DEFAULT)
`uvm_field_object(obi_memory_zcmt_cfg, UVM_DEFAULT)
- //`uvm_field_object(obi_memory_mmu_ptw_cfg, UVM_DEFAULT)
+ `uvm_field_object(obi_memory_mmu_ptw_cfg, UVM_DEFAULT)
// TODO:`uvm_field_object(obi_memory_data_cfg, UVM_DEFAULT)
@@ -222,8 +222,8 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
obi_memory_zcmt_cfg.drv_slv_gnt_mode == UVMA_OBI_MEMORY_DRV_SLV_GNT_MODE_CONSTANT;
obi_memory_zcmt_cfg.drv_slv_rvalid_mode == UVMA_OBI_MEMORY_DRV_SLV_RVALID_MODE_CONSTANT;
- //obi_memory_mmu_ptw_cfg.drv_slv_gnt_mode == UVMA_OBI_MEMORY_DRV_SLV_GNT_MODE_CONSTANT;
- //obi_memory_mmu_ptw_cfg.drv_slv_rvalid_mode == UVMA_OBI_MEMORY_DRV_SLV_RVALID_MODE_CONSTANT;
+ obi_memory_mmu_ptw_cfg.drv_slv_gnt_mode == UVMA_OBI_MEMORY_DRV_SLV_GNT_MODE_CONSTANT;
+ obi_memory_mmu_ptw_cfg.drv_slv_rvalid_mode == UVMA_OBI_MEMORY_DRV_SLV_RVALID_MODE_CONSTANT;
}
else {
obi_memory_instr_cfg.drv_slv_gnt_mode != UVMA_OBI_MEMORY_DRV_SLV_GNT_MODE_CONSTANT;
@@ -241,8 +241,8 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
obi_memory_zcmt_cfg.drv_slv_gnt_mode != UVMA_OBI_MEMORY_DRV_SLV_GNT_MODE_CONSTANT;
obi_memory_zcmt_cfg.drv_slv_rvalid_mode != UVMA_OBI_MEMORY_DRV_SLV_RVALID_MODE_CONSTANT;
- //obi_memory_mmu_ptw_cfg.drv_slv_gnt_mode != UVMA_OBI_MEMORY_DRV_SLV_GNT_MODE_CONSTANT;
- //obi_memory_mmu_ptw_cfg.drv_slv_rvalid_mode != UVMA_OBI_MEMORY_DRV_SLV_RVALID_MODE_CONSTANT;
+ obi_memory_mmu_ptw_cfg.drv_slv_gnt_mode != UVMA_OBI_MEMORY_DRV_SLV_GNT_MODE_CONSTANT;
+ obi_memory_mmu_ptw_cfg.drv_slv_rvalid_mode != UVMA_OBI_MEMORY_DRV_SLV_RVALID_MODE_CONSTANT;
}
}
@@ -321,16 +321,16 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
obi_memory_load_cfg.achk_width == RTLCVA6Cfg.ObiLoadbusCfg.OptionalCfg.AChkWidth ;
obi_memory_load_cfg.rchk_width == RTLCVA6Cfg.ObiLoadbusCfg.OptionalCfg.RChkWidth ;
- //obi_memory_mmu_ptw_cfg.drv_mode == UVMA_OBI_MEMORY_MODE_SLV;
- //obi_memory_mmu_ptw_cfg.version == UVMA_OBI_MEMORY_VERSION_1P2;
- //obi_memory_mmu_ptw_cfg.auser_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.AUserWidth;
- //obi_memory_mmu_ptw_cfg.wuser_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.WUserWidth;
- //obi_memory_mmu_ptw_cfg.ruser_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.RUserWidth;
- //obi_memory_mmu_ptw_cfg.addr_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.AddrWidth ;
- //obi_memory_mmu_ptw_cfg.data_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.DataWidth ;
- //obi_memory_mmu_ptw_cfg.id_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.IdWidth ;
- //obi_memory_mmu_ptw_cfg.achk_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.AChkWidth ;
- //obi_memory_mmu_ptw_cfg.rchk_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.RChkWidth ;
+ obi_memory_mmu_ptw_cfg.drv_mode == UVMA_OBI_MEMORY_MODE_SLV;
+ obi_memory_mmu_ptw_cfg.version == UVMA_OBI_MEMORY_VERSION_1P2;
+ obi_memory_mmu_ptw_cfg.auser_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.AUserWidth;
+ obi_memory_mmu_ptw_cfg.wuser_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.WUserWidth;
+ obi_memory_mmu_ptw_cfg.ruser_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.RUserWidth;
+ obi_memory_mmu_ptw_cfg.addr_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.AddrWidth ;
+ obi_memory_mmu_ptw_cfg.data_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.DataWidth ;
+ obi_memory_mmu_ptw_cfg.id_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.IdWidth ;
+ obi_memory_mmu_ptw_cfg.achk_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.AChkWidth ;
+ obi_memory_mmu_ptw_cfg.rchk_width == RTLCVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.RChkWidth ;
soft obi_memory_instr_cfg.drv_slv_gnt_random_latency_min == 2;
soft obi_memory_instr_cfg.drv_slv_gnt_random_latency_max == 5;
@@ -367,12 +367,12 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
soft obi_memory_zcmt_cfg.drv_slv_rvalid_random_latency_min == 2;
soft obi_memory_zcmt_cfg.drv_slv_rvalid_random_latency_max == 5;
soft obi_memory_zcmt_cfg.drv_slv_rvalid_fixed_latency <= 5;
- //soft obi_memory_mmu_ptw_cfg.drv_slv_gnt_random_latency_min <= 0;
- //soft obi_memory_mmu_ptw_cfg.drv_slv_gnt_random_latency_max <= 10;
- //soft obi_memory_mmu_ptw_cfg.drv_slv_gnt_fixed_latency <= 2;
- //soft obi_memory_mmu_ptw_cfg.drv_slv_rvalid_random_latency_min <= 0;
- //soft obi_memory_mmu_ptw_cfg.drv_slv_rvalid_random_latency_max <= 10;
- //soft obi_memory_mmu_ptw_cfg.drv_slv_rvalid_fixed_latency <= 3;
+ soft obi_memory_mmu_ptw_cfg.drv_slv_gnt_random_latency_min <= 0;
+ soft obi_memory_mmu_ptw_cfg.drv_slv_gnt_random_latency_max <= 10;
+ soft obi_memory_mmu_ptw_cfg.drv_slv_gnt_fixed_latency <= 2;
+ soft obi_memory_mmu_ptw_cfg.drv_slv_rvalid_random_latency_min <= 0;
+ soft obi_memory_mmu_ptw_cfg.drv_slv_rvalid_random_latency_max <= 10;
+ soft obi_memory_mmu_ptw_cfg.drv_slv_rvalid_fixed_latency <= 3;
if (is_active == UVM_ACTIVE) {
clknrst_cfg.is_active == UVM_ACTIVE;
@@ -386,14 +386,14 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
obi_memory_amo_cfg.is_active == UVM_ACTIVE;
obi_memory_load_cfg.is_active == UVM_ACTIVE;
obi_memory_zcmt_cfg.is_active == UVM_ACTIVE;
- //obi_memory_mmu_ptw_cfg.is_active == UVM_ACTIVE;
+ obi_memory_mmu_ptw_cfg.is_active == UVM_ACTIVE;
} else {
obi_memory_instr_cfg.is_active == UVM_PASSIVE;
obi_memory_store_cfg.is_active == UVM_PASSIVE;
obi_memory_amo_cfg.is_active == UVM_PASSIVE;
obi_memory_zcmt_cfg.is_active == UVM_PASSIVE;
obi_memory_load_cfg.is_active == UVM_PASSIVE;
- //obi_memory_mmu_ptw_cfg.is_active == UVM_PASSIVE;
+ obi_memory_mmu_ptw_cfg.is_active == UVM_PASSIVE;
}
}
@@ -405,8 +405,8 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
obi_memory_zcmt_cfg.trn_log_enabled == 1;
obi_memory_amo_cfg.trn_log_enabled == 1;
obi_memory_load_cfg.trn_log_enabled == 1;
- //obi_memory_mmu_ptw_cfg.trn_log_enabled == 1;
- //obi_memory_mmu_ptw_cfg.trn_log_enabled == 1;
+ obi_memory_mmu_ptw_cfg.trn_log_enabled == 1;
+ obi_memory_mmu_ptw_cfg.trn_log_enabled == 1;
rvfi_cfg.trn_log_enabled == 1;
isacov_cfg.trn_log_enabled == 1;
} else {
@@ -417,7 +417,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
obi_memory_amo_cfg.trn_log_enabled == 0;
obi_memory_zcmt_cfg.trn_log_enabled == 0;
obi_memory_load_cfg.trn_log_enabled == 0;
- //obi_memory_mmu_ptw_cfg.trn_log_enabled == 0;
+ obi_memory_mmu_ptw_cfg.trn_log_enabled == 0;
rvfi_cfg.trn_log_enabled == 0;
isacov_cfg.trn_log_enabled == 0;
}
@@ -438,7 +438,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
// obi_memory_zcmt_cfg.cov_model_enabled == 0;
// }
obi_memory_load_cfg.cov_model_enabled == 1;
- //obi_memory_mmu_ptw_cfg.cov_model_enabled == 1;
+ obi_memory_mmu_ptw_cfg.cov_model_enabled == 1;
interrupt_cfg.cov_model_enabled == 1;
} else {
isacov_cfg.cov_model_enabled == 0;
@@ -447,7 +447,7 @@ class uvme_cva6_cfg_c extends uvma_core_cntrl_cfg_c;
obi_memory_store_cfg.cov_model_enabled == 0;
obi_memory_amo_cfg.cov_model_enabled == 0;
obi_memory_load_cfg.cov_model_enabled == 0;
- //obi_memory_mmu_ptw_cfg.cov_model_enabled == 0;
+ obi_memory_mmu_ptw_cfg.cov_model_enabled == 0;
interrupt_cfg.cov_model_enabled == 0;
}
@@ -489,7 +489,7 @@ function uvme_cva6_cfg_c::new(string name="uvme_cva6_cfg");
obi_memory_amo_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_amo_cfg");
obi_memory_zcmt_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_zcmt_cfg");
obi_memory_load_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_load_cfg");
- //obi_memory_mmu_ptw_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_mmu_ptw_cfg");
+ obi_memory_mmu_ptw_cfg = uvma_obi_memory_cfg_c::type_id::create("obi_memory_mmu_ptw_cfg");
rvfi_cfg = uvma_rvfi_cfg_c#(ILEN,XLEN)::type_id::create("rvfi_cfg");
isacov_cfg = uvma_isacov_cfg_c::type_id::create("isacov_cfg");
interrupt_cfg = uvma_interrupt_cfg_c::type_id::create("interrupt_cfg");
diff --git a/verif/env/uvme/uvme_cva6_cntxt.sv b/verif/env/uvme/uvme_cva6_cntxt.sv
index 0f6e832ab6..6dd9d852a8 100644
--- a/verif/env/uvme/uvme_cva6_cntxt.sv
+++ b/verif/env/uvme/uvme_cva6_cntxt.sv
@@ -38,7 +38,7 @@ class uvme_cva6_cntxt_c extends uvm_object;
uvma_obi_memory_cntxt_c obi_memory_amo_cntxt;
uvma_obi_memory_cntxt_c obi_memory_zcmt_cntxt;
uvma_obi_memory_cntxt_c obi_memory_load_cntxt;
- //uvma_obi_memory_cntxt_c obi_memory_mmu_ptw_cntxt;
+ uvma_obi_memory_cntxt_c obi_memory_mmu_ptw_cntxt;
uvma_cva6_core_cntrl_cntxt_c core_cntrl_cntxt;
uvma_rvfi_cntxt_c rvfi_cntxt;
@@ -66,7 +66,7 @@ class uvme_cva6_cntxt_c extends uvm_object;
`uvm_field_object(obi_memory_amo_cntxt, UVM_DEFAULT)
`uvm_field_object(obi_memory_load_cntxt, UVM_DEFAULT)
`uvm_field_object(obi_memory_zcmt_cntxt, UVM_DEFAULT)
- //`uvm_field_object(obi_memory_mmu_ptw_cntxt, UVM_DEFAULT)
+ `uvm_field_object(obi_memory_mmu_ptw_cntxt, UVM_DEFAULT)
`uvm_field_object(core_cntrl_cntxt, UVM_DEFAULT)
`uvm_field_object(rvfi_cntxt, UVM_DEFAULT)
@@ -109,7 +109,9 @@ function uvme_cva6_cntxt_c::new(string name="uvme_cva6_cntxt");
if (RTLCVA6Cfg.RVZCMT) begin
obi_memory_zcmt_cntxt = uvma_obi_memory_cntxt_c::type_id::create("obi_memory_zcmt_cntxt");
end
- //obi_memory_mmu_ptw_cntxt = uvma_obi_memory_cntxt_c::type_id::create("obi_memory_mmu_ptw_cntxt");
+ if (RTLCVA6Cfg.MmuPresent) begin
+ obi_memory_mmu_ptw_cntxt = uvma_obi_memory_cntxt_c::type_id::create("obi_memory_mmu_ptw_cntxt");
+ end
end
mem = uvml_mem_cva6::type_id::create("mem");
diff --git a/verif/env/uvme/uvme_cva6_env.sv b/verif/env/uvme/uvme_cva6_env.sv
index 2b99bd8fd0..405d3e2cc1 100644
--- a/verif/env/uvme/uvme_cva6_env.sv
+++ b/verif/env/uvme/uvme_cva6_env.sv
@@ -49,7 +49,7 @@ class uvme_cva6_env_c extends uvm_env;
uvma_obi_memory_agent_c obi_memory_amo_agent;
uvma_obi_memory_agent_c obi_memory_load_agent;
uvma_obi_memory_agent_c obi_memory_zcmt_agent;
- //uvma_obi_memory_agent_c obi_memory_mmu_ptw_agent;
+ uvma_obi_memory_agent_c obi_memory_mmu_ptw_agent;
uvma_cva6_core_cntrl_agent_c core_cntrl_agent;
uvma_rvfi_agent_c#(ILEN,XLEN) rvfi_agent;
@@ -195,7 +195,9 @@ function void uvme_cva6_env_c::build_phase(uvm_phase phase);
if (RTLCVA6Cfg.RVZCMT) begin
cntxt.obi_memory_zcmt_cntxt.mem = cntxt.mem_obi;
end
- //cntxt.obi_memory_mmu_ptw_cntxt.mem = cntxt.mem_obi;
+ if (RTLCVA6Cfg.MmuPresent) begin
+ cntxt.obi_memory_mmu_ptw_cntxt.mem = cntxt.mem_obi;
+ end
cntxt.interrupt_cntxt.mem_obi = cntxt.mem_obi;
`uvm_info("UVMECVA6ENV", "OBI interface is active", UVM_NONE)
end
@@ -281,7 +283,9 @@ function void uvme_cva6_env_c::assign_cfg();
if (RTLCVA6Cfg.RVZCMT) begin
uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "obi_memory_zcmt_agent", "cfg", cfg.obi_memory_zcmt_cfg);
end
- //uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "obi_memory_mmu_ptw_agent", "cfg", cfg.obi_memory_mmu_ptw_cfg);
+ if (RTLCVA6Cfg.MmuPresent) begin
+ uvm_config_db#(uvma_obi_memory_cfg_c)::set(this, "obi_memory_mmu_ptw_agent", "cfg", cfg.obi_memory_mmu_ptw_cfg);
+ end
end
uvm_config_db#(uvma_core_cntrl_cfg_c)::set(this, "core_cntrl_agent", "cfg", cfg);
@@ -316,7 +320,9 @@ function void uvme_cva6_env_c::assign_cntxt();
if (RTLCVA6Cfg.RVZCMT) begin
uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "obi_memory_zcmt_agent", "cntxt", cntxt.obi_memory_zcmt_cntxt);
end
- //uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "obi_memory_mmu_ptw_agent", "cntxt", cntxt.obi_memory_mmu_ptw_cntxt);
+ if (RTLCVA6Cfg.MmuPresent) begin
+ uvm_config_db#(uvma_obi_memory_cntxt_c)::set(this, "obi_memory_mmu_ptw_agent", "cntxt", cntxt.obi_memory_mmu_ptw_cntxt);
+ end
end
uvm_config_db#(uvma_rvfi_cntxt_c)::set(this, "rvfi_agent", "cntxt", cntxt.rvfi_cntxt);
@@ -341,7 +347,9 @@ function void uvme_cva6_env_c::create_agents();
if (RTLCVA6Cfg.RVZCMT) begin
obi_memory_zcmt_agent = uvma_obi_memory_agent_c::type_id::create("obi_memory_zcmt_agent", this);
end
- //obi_memory_mmu_ptw_agent = uvma_obi_memory_agent_c::type_id::create("obi_memory_mmu_ptw_agent", this);
+ if (RTLCVA6Cfg.MmuPresent) begin
+ obi_memory_mmu_ptw_agent = uvma_obi_memory_agent_c::type_id::create("obi_memory_mmu_ptw_agent", this);
+ end
end
core_cntrl_agent = uvma_cva6_core_cntrl_agent_c::type_id::create("core_cntrl_agent", this);
@@ -449,7 +457,9 @@ function void uvme_cva6_env_c::assemble_vsequencer();
if (RTLCVA6Cfg.RVZCMT) begin
vsequencer.obi_memory_zcmt_sequencer = obi_memory_zcmt_agent.sequencer;
end
- //vsequencer.obi_memory_mmu_ptw_sequencer = obi_memory_mmu_ptw_agent.sequencer;
+ if (RTLCVA6Cfg.MmuPresent) begin
+ vsequencer.obi_memory_mmu_ptw_sequencer = obi_memory_mmu_ptw_agent.sequencer;
+ end
end
vsequencer.interrupt_sequencer = interrupt_agent.sequencer;
vsequencer.cvxif_vsequencer = cvxif_agent.vsequencer;
@@ -465,7 +475,7 @@ task uvme_cva6_env_c::run_phase(uvm_phase phase);
uvma_obi_memory_slv_seq_c amo_slv_seq;
uvma_obi_memory_slv_seq_c zcmt_slv_seq;
uvma_obi_memory_slv_seq_c load_slv_seq;
- //uvma_obi_memory_slv_seq_c mmu_ptw_slv_seq;
+ uvma_obi_memory_slv_seq_c mmu_ptw_slv_seq;
fork
@@ -548,15 +558,16 @@ task uvme_cva6_env_c::run_phase(uvm_phase phase);
load_slv_seq.start(obi_memory_load_agent.sequencer);
end
end
- //begin : obi_mmu_ptw_slv_thread
- // if(cfg.obi_memory_mmu_ptw_cfg.is_active == UVM_ACTIVE && !config_pkg::OBI_NOT_COMPLIANT) begin
- // mmu_ptw_slv_seq = uvma_obi_memory_slv_seq_c::type_id::create("mmu_ptw_slv_seq");
- // if (!mmu_ptw_slv_seq.randomize()) begin
- // `uvm_fatal("MMUPTWSLVSEQ", "Randomize failed");
- // end
- // mmu_ptw_slv_seq.start(obi_memory_mmu_ptw_agent.sequencer);
- // end
- //end
+ begin : obi_mmu_ptw_slv_thread
+ if(cfg.obi_memory_mmu_ptw_cfg.is_active == UVM_ACTIVE && !config_pkg::OBI_NOT_COMPLIANT && RTLCVA6Cfg.MmuPresent) begin
+ mmu_ptw_slv_seq = uvma_obi_memory_slv_seq_c::type_id::create("mmu_ptw_slv_seq");
+ if (!mmu_ptw_slv_seq.randomize()) begin
+ `uvm_fatal("MMUPTWSLVSEQ", "Randomize failed");
+ end
+ mmu_ptw_slv_seq.start(obi_memory_mmu_ptw_agent.sequencer);
+ `uvm_warning("MMUPTWSLVSEQ", "Sequence started \n");
+ end
+ end
join_none
endtask
diff --git a/verif/env/uvme/uvme_cva6_sb.sv b/verif/env/uvme/uvme_cva6_sb.sv
index cf15c8f53d..10d6cedb17 100644
--- a/verif/env/uvme/uvme_cva6_sb.sv
+++ b/verif/env/uvme/uvme_cva6_sb.sv
@@ -323,7 +323,7 @@ endfunction : check_mepc
function bit [XLEN:0] uvme_cva6_sb_c::check_mcycle_h(uvma_isacov_instr_c instr, uvma_isacov_instr_c instr_prev, int cycle_count);
// Check mcycle value after a CSR read
- if (instr_prev == null) return;
+ if (instr_prev == null) return {1'h0 , -2147483648};
write_in_mcycle = (instr_prev.is_csr_write() && instr_prev.csr_val == 12'hb00) ? 1 : 0;
if (cfg.xlen == 32) begin
diff --git a/verif/env/uvme/uvme_cva6_vsqr.sv b/verif/env/uvme/uvme_cva6_vsqr.sv
index e064484a98..ffe4f66ef8 100644
--- a/verif/env/uvme/uvme_cva6_vsqr.sv
+++ b/verif/env/uvme/uvme_cva6_vsqr.sv
@@ -44,7 +44,7 @@ class uvme_cva6_vsqr_c extends uvm_sequencer#(
uvma_obi_memory_sqr_c obi_memory_amo_sequencer;
uvma_obi_memory_sqr_c obi_memory_zcmt_sequencer;
uvma_obi_memory_sqr_c obi_memory_load_sequencer;
- //uvma_obi_memory_sqr_c obi_memory_mmu_ptw_sequencer;
+ uvma_obi_memory_sqr_c obi_memory_mmu_ptw_sequencer;
diff --git a/verif/regress/Instr_tracing_test.sh b/verif/regress/Instr_tracing_test.sh
new file mode 100755
index 0000000000..e4a0078b48
--- /dev/null
+++ b/verif/regress/Instr_tracing_test.sh
@@ -0,0 +1,127 @@
+#!/bin/bash
+
+# Copyright 2025 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Author: Maxime Colson - Thales
+
+# Usage ./compare_iti_trace.sh
+# Exit 0 if iti traces match, 1 otherwise.
+
+exit_error() {
+ echo "$1" >&2
+ exit ${2:-1}
+}
+
+clean_file_preserve_header() {
+ local input_f="$1"
+ local output_f="$2"
+ local start_skip="$3"
+ local end_skip="$4"
+
+ local total_lines lines_to_keep
+ total_lines=$(wc -l < "$input_f")
+ lines_to_keep=$((total_lines - start_skip - end_skip))
+
+ if [ "$lines_to_keep" -le 0 ]; then
+ exit_error "Error: not enought lines in $input_f"
+ fi
+
+ {
+ head -n1 "$input_f"
+ tail -n "+$((start_skip + 1))" "$input_f" | head -n "$lines_to_keep"
+ } | sed $'s/\r$//'> "$output_f"
+}
+
+if [ "$#" -ne 1 ]; then
+ exit_error "Usage: $0 " 2
+fi
+
+exe="$1"
+base=$(basename "$exe" .o)
+mkdir verif/sim/Instr_tracing_artifact
+workdir="$(realpath verif/sim/Instr_tracing_artifact)"
+
+
+if ! bash verif/regress/iti_test.sh "$exe"; then
+ exit_error "Error: iti_test.sh failed"
+fi
+
+if [ ! -f verif/sim/iti.traces ]; then
+ exit_error "Error: iti.traces does not exist"
+fi
+if [ ! -f verif/sim/encaps.traces ]; then
+ exit_error "Error: encaps.traces does not exist"
+fi
+
+cp verif/sim/iti.traces "$workdir/iti.trace"
+cp verif/sim/encaps.traces "$workdir/encaps.trace"
+
+rm verif/sim/iti.traces
+rm verif/sim/encaps.traces
+
+cd "$workdir"
+git clone https://github.com/riscv-non-isa/riscv-trace-spec.git
+cd riscv-trace-spec
+git checkout dca761264721068c4576eebd206e2c8b0b9d58b6
+cd referenceFlow
+bash scripts/build.sh
+
+tmp_riscv="$workdir/riscv-trace-spec/referenceFlow/tests/test_files/$base.riscv"
+cd ../../..
+cp "$exe" "$tmp_riscv"
+cd Instr_tracing_artifact/riscv-trace-spec/referenceFlow
+if ! ./scripts/run_regression.sh -t itype3_debug --annotate --debug $tmp_riscv; then
+ exit_error "Error: run_regression failed"
+fi
+
+reg_dir=$(ls -td ./regression_* 2>/dev/null | head -n1)
+if [ -z "$reg_dir" ]; then
+ exit_error "Error: Folder regression does not exist"
+fi
+
+iti_out="$reg_dir/itype3_debug/$base.encoder_input"
+if [ ! -f "$iti_out" ]; then
+ exit_error "Error: $iti_out does not exist"
+fi
+encod_out="$reg_dir/itype3_debug/$base.te_inst"
+if [ ! -f "$iti_out" ]; then
+ exit_error "Error: $encod_out does not exist"
+fi
+
+cp "$iti_out" "$workdir/iti_reg.trace"
+cp "$encod_out" "$workdir/encod_reg.trace"
+
+clean_file_preserve_header "$workdir/iti_reg.trace" "$workdir/iti_reg_cleaned.trace" 6 2
+clean_file_preserve_header "$workdir/iti.trace" "$workdir/iti_cleaned.trace" 7 0
+
+if diff -q "$workdir/iti_reg_cleaned.trace" "$workdir/iti_cleaned.trace" > /dev/null; then
+ echo "SUCESS: Same ITI Traces"
+else
+ diff -u "$workdir/iti_reg_cleaned.trace" "$workdir/iti_cleaned.trace"
+ exit_error "FAILED: ITI traces do not match"
+fi
+
+decapsuler_path="$workdir/../../../corev_apu/instr_tracing/Decapsuler"
+
+if ! make -C "$decapsuler_path"; then
+ exit_error "Error: Compilation of Decapsuler failed"
+fi
+
+if ! "$decapsuler_path/Decapsuler" "$workdir/encaps.trace"; then
+ exit_error "Error: Decapsulation failed"
+fi
+
+clean_file_preserve_header "$workdir/encod_reg.trace" "$workdir/encod_reg_cleaned.trace" 3 2
+clean_file_preserve_header "$workdir/encaps.csv" "$workdir/encaps_cleaned.trace" 3 0
+
+if diff -q "$workdir/encod_reg_cleaned.trace" "$workdir/encaps_cleaned.trace" > /dev/null; then
+ echo "SUCESS: Same Encoder Packets"
+else
+ python3 "$decapsuler_path/diff_color.py" "$workdir/encaps.csv" "$workdir/encod_reg.trace"
+ exit_error "FAILED: Encoder Packets do not match"
+fi
\ No newline at end of file
diff --git a/verif/regress/dv-riscv-mmu-sv32-test.sh b/verif/regress/dv-riscv-mmu-sv32-test.sh
index d9cbea492c..21c3d7114c 100644
--- a/verif/regress/dv-riscv-mmu-sv32-test.sh
+++ b/verif/regress/dv-riscv-mmu-sv32-test.sh
@@ -31,3 +31,15 @@ fi
cd verif/sim
python3 cva6.py --testlist=../tests/testlist_riscv-mmu-sv32-arch-test-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
cd -
+
+cd verif/sim
+python3 cva6.py --testlist=../tests/testlist_riscv-mmu-sv32-arch-test-$DV_TARGET.yaml --target cv32a6_imac_sv32_obi --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
+cd -
+
+cd verif/sim
+python3 cva6.py --testlist=../tests/testlist_riscv-mmu-sv32-arch-test-$DV_TARGET.yaml --target cv32a65x_sv32 --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
+cd -
+
+cd verif/sim
+python3 cva6.py --testlist=../tests/testlist_riscv-mmu-sv32-arch-test-$DV_TARGET.yaml --target cv32a65x_sv32_axi --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../tests/riscv-arch-test/riscv-target/spike/link.ld
+cd -
\ No newline at end of file
diff --git a/verif/regress/iti_test.sh b/verif/regress/iti_test.sh
new file mode 100644
index 0000000000..1b914d202a
--- /dev/null
+++ b/verif/regress/iti_test.sh
@@ -0,0 +1,56 @@
+# Copyright 2025 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Author: Maxime Colson - Thales
+
+if [ "$#" -eq 1 ]; then
+ ELF_ARG="$1"
+elif [ "$#" -gt 1 ]; then
+ echo "Usage: $0 "
+ exit 1
+else
+ ELF_ARG="../tests/custom/ITI/test_iti_asm.o"
+fi
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S ../tests/custom/ITI/iti_asm.S -I../tests/custom/env -I../tests/custom/common -lgcc"
+
+cd verif/sim/
+
+make -C ../.. clean
+make clean_all
+python3 cva6.py --elf_tests "$ELF_ARG" --target cv32a60x --iss_yaml cva6.yaml --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld $DV_OPTS
+#python3 cva6.py --c_tests ../tests/custom/ITI/test_iti_asm.c --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/pmp-tests-combined.sh b/verif/regress/pmp-tests-combined.sh
new file mode 100644
index 0000000000..f2062948f4
--- /dev/null
+++ b/verif/regress/pmp-tests-combined.sh
@@ -0,0 +1,41 @@
+#!/bin/bash
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Description: Combined smoke tests for all cv32a6x targets
+
+set -e
+
+SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+
+echo "=============================================="
+echo "Running combined pmp tests for all targets"
+echo "=============================================="
+
+echo ""
+echo "----------------------------------------------"
+echo "Running pmp_cv32a60x-tests.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/pmp_cv32a60x_tests.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running pmp_cv32a65x-tests.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/pmp_cv32a65x_tests.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running pmp_cv32a65x_sv32_tests.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/pmp_cv32a65x_sv32_tests.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running pmp_cv32a_imac_sv32_tests.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/pmp_cv32a_imac_sv32_tests.sh"
\ No newline at end of file
diff --git a/verif/regress/pmp_cv32a60x_tests.sh b/verif/regress/pmp_cv32a60x_tests.sh
new file mode 100644
index 0000000000..54b400dda6
--- /dev/null
+++ b/verif/regress/pmp_cv32a60x_tests.sh
@@ -0,0 +1,49 @@
+##-----------------------------------------------------------------------------
+## Copyright 2024 Robert Bosch GmbH
+##
+## SPDX-License-Identifier: SHL-0.51
+##
+## Original Author: Konstantinos Leventos - Robert Bosch France SAS
+##-----------------------------------------------------------------------------
+
+# Where the tools are
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+# Install the required tools
+source ./verif/regress/install-spike.sh
+
+# Setup sim env
+source ./verif/sim/setup-env.sh
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-uvm
+fi
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+export DV_TARGET=cv32a65x_axi
+
+make clean
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target cv32a60x_zcmt_pmp --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+
+make clean_all
+
+
+export DV_TARGET=cv32a65x
+
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target cv32a60x_zcmt_pmp_axi --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+
+make clean_all
+
+cd -
+make clean
diff --git a/verif/regress/pmp_cv32a65x_sv32_tests.sh b/verif/regress/pmp_cv32a65x_sv32_tests.sh
new file mode 100644
index 0000000000..8d4956741d
--- /dev/null
+++ b/verif/regress/pmp_cv32a65x_sv32_tests.sh
@@ -0,0 +1,53 @@
+##-----------------------------------------------------------------------------
+## Copyright 2024 Robert Bosch GmbH
+##
+## SPDX-License-Identifier: SHL-0.51
+##
+## Original Author: Konstantinos Leventos - Robert Bosch France SAS
+##-----------------------------------------------------------------------------
+
+# Where the tools are
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+# Install the required tools
+source ./verif/regress/install-spike.sh
+
+# Setup sim env
+source ./verif/sim/setup-env.sh
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-uvm
+fi
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+export DV_TARGET=cv32a65x_axi
+
+make clean
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target cv32a65x_sv32_axi --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+
+make clean_all
+
+
+export DV_TARGET=cv32a65x
+
+<<<<<<<< HEAD:verif/regress/pmp_cv32a65x_sv32_tests.sh
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+========
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target cv32a65x_sv32 --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+>>>>>>>> 27305f670 (create all configs and their smoke tests):verif/regress/pmp_cv32a65x_tests.sh
+
+make clean_all
+
+cd -
+make clean
diff --git a/verif/regress/pmp_cv32a65x_tests.sh b/verif/regress/pmp_cv32a65x_tests.sh
new file mode 100644
index 0000000000..e06740b557
--- /dev/null
+++ b/verif/regress/pmp_cv32a65x_tests.sh
@@ -0,0 +1,41 @@
+##-----------------------------------------------------------------------------
+## Copyright 2024 Robert Bosch GmbH
+##
+## SPDX-License-Identifier: SHL-0.51
+##
+## Original Author: Konstantinos Leventos - Robert Bosch France SAS
+##-----------------------------------------------------------------------------
+
+# Where the tools are
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+# Install the required tools
+source ./verif/regress/install-spike.sh
+
+# Setup sim env
+source ./verif/sim/setup-env.sh
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-uvm
+fi
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+export DV_TARGET=cv32a65x_axi
+
+make clean
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target $DV_TARGET --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+
+make clean_all
+cd -
+make clean
diff --git a/verif/regress/pmp_cv32a6_imac_sv32_tests.sh b/verif/regress/pmp_cv32a6_imac_sv32_tests.sh
new file mode 100644
index 0000000000..7b69bd0e4a
--- /dev/null
+++ b/verif/regress/pmp_cv32a6_imac_sv32_tests.sh
@@ -0,0 +1,49 @@
+##-----------------------------------------------------------------------------
+## Copyright 2024 Robert Bosch GmbH
+##
+## SPDX-License-Identifier: SHL-0.51
+##
+## Original Author: Konstantinos Leventos - Robert Bosch France SAS
+##-----------------------------------------------------------------------------
+
+# Where the tools are
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+# Install the required tools
+source ./verif/regress/install-spike.sh
+
+# Setup sim env
+source ./verif/sim/setup-env.sh
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-uvm
+fi
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+export DV_TARGET=cv32a65x_axi
+
+make clean
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target cv32a6_imac_sv32_obi --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+
+make clean_all
+
+
+export DV_TARGET=cv32a65x
+
+python3 cva6.py --testlist=../tests/testlist_pmp-$DV_TARGET.yaml --target cv32a6_imac_sv32 --iss_yaml=cva6.yaml --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/cv32a60x/linker/link.ld
+
+make clean_all
+
+cd -
+make clean
diff --git a/verif/regress/smoke-tests-combined.sh b/verif/regress/smoke-tests-combined.sh
new file mode 100644
index 0000000000..f6c08b598d
--- /dev/null
+++ b/verif/regress/smoke-tests-combined.sh
@@ -0,0 +1,106 @@
+#!/bin/bash
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Description: Combined smoke tests for all cv32a6x targets
+
+set -e
+
+SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+
+echo "=============================================="
+echo "Running combined smoke tests for all targets"
+echo "=============================================="
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a60x.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a60x.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a60x_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a60x_axi.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a65x.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a65x.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a65x_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a65x_axi.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a65x_noPMP.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a65x_noPMP.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a65x_noPMP_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a65x_noPMP_axi.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a65x_noPMP_noSuperScalar.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a65x_noPMP_noSuperScalar.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a65x_noPMP_noSuperScalar_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a65x_noPMP_noSuperScalar_axi.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a60x_zcmt_pmp.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a60x_zcmt_pmp.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a60x_zcmt_pmp_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a60x_zcmt_pmp_axi.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a6_imac_sv32.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a6_imac_sv32.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a6_imac_sv32_obi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a6_imac_sv32_obi.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a65x_sv32.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a65x_sv32.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running smoke-tests-cv32a65x_sv32_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/smoke-tests-cv32a65x_sv32_axi.sh"
+
+echo ""
+echo "=============================================="
+echo "All smoke tests completed!"
+echo "=============================================="
\ No newline at end of file
diff --git a/verif/regress/smoke-tests-cv32a60x.sh b/verif/regress/smoke-tests-cv32a60x.sh
index a4f81ebdb6..24f6e33575 100644
--- a/verif/regress/smoke-tests-cv32a60x.sh
+++ b/verif/regress/smoke-tests-cv32a60x.sh
@@ -47,9 +47,24 @@ CC_OPTS="-static \
cd verif/sim/
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
make -C ../.. clean
make clean_all
-python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --iss_timeout=30000 --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+python3 cva6.py --iss_timeout=30000 --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a60x --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
make -C ../.. clean
make clean_all
diff --git a/verif/regress/smoke-tests-cv32a60x_axi.sh b/verif/regress/smoke-tests-cv32a60x_axi.sh
index 51c8dafad1..952e98f249 100644
--- a/verif/regress/smoke-tests-cv32a60x_axi.sh
+++ b/verif/regress/smoke-tests-cv32a60x_axi.sh
@@ -47,9 +47,24 @@ CC_OPTS="-static \
cd verif/sim/
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
make -C ../.. clean
make clean_all
-python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a60x_axi --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --iss_timeout=30000 --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a60x_axi --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
+python3 cva6.py --iss_timeout=30000 --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a60x_axi --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
make -C ../.. clean
make clean_all
diff --git a/verif/regress/smoke-tests-cv32a60x_zcmt_pmp.sh b/verif/regress/smoke-tests-cv32a60x_zcmt_pmp.sh
new file mode 100644
index 0000000000..3353949419
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a60x_zcmt_pmp.sh
@@ -0,0 +1,71 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static \
+ -mcmodel=medany \
+ -fvisibility=hidden \
+ -nostartfiles \
+ -g \
+ ../tests/custom/common/syscalls.c \
+ ../tests/custom/common/crt.S \
+ -I../tests/custom/env \
+ -I../tests/custom/common"
+
+
+cd verif/sim/
+
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
+make -C ../.. clean
+make clean_all
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --iss_timeout=30000 --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a60x_zcmt_pmp --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+python3 cva6.py --iss_timeout=30000 --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a60x_zcmt_pmp --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/smoke-tests-cv32a60x_zcmt_pmp_axi.sh b/verif/regress/smoke-tests-cv32a60x_zcmt_pmp_axi.sh
new file mode 100644
index 0000000000..af32e919bc
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a60x_zcmt_pmp_axi.sh
@@ -0,0 +1,71 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static \
+ -mcmodel=medany \
+ -fvisibility=hidden \
+ -nostartfiles \
+ -g \
+ ../tests/custom/common/syscalls.c \
+ ../tests/custom/common/crt.S \
+ -I../tests/custom/env \
+ -I../tests/custom/common"
+
+
+cd verif/sim/
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
+make -C ../.. clean
+make clean_all
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --iss_timeout=30000 --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a60x_zcmt_pmp_axi --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
+python3 cva6.py --iss_timeout=30000 --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a60x_zcmt_pmp_axi --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/smoke-tests-cv32a65x.sh b/verif/regress/smoke-tests-cv32a65x.sh
index 85ecb5b781..746252cf3c 100644
--- a/verif/regress/smoke-tests-cv32a65x.sh
+++ b/verif/regress/smoke-tests-cv32a65x.sh
@@ -46,8 +46,25 @@ CC_OPTS="-static \
cd verif/sim/
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
make -C ../.. clean
make clean_all
+
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a65x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
make -C ../.. clean
make clean_all
diff --git a/verif/regress/smoke-tests-cv32a65x_axi.sh b/verif/regress/smoke-tests-cv32a65x_axi.sh
index 9e19f2d6a9..76c7ac2830 100644
--- a/verif/regress/smoke-tests-cv32a65x_axi.sh
+++ b/verif/regress/smoke-tests-cv32a65x_axi.sh
@@ -46,8 +46,24 @@ CC_OPTS="-static \
cd verif/sim/
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
make -C ../.. clean
make clean_all
+
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a65x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a65x_axi --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
python3 cva6.py --iss_timeout=30000 --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x_axi --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
make -C ../.. clean
make clean_all
diff --git a/verif/regress/smoke-tests-cv32a65x_noPMP.sh b/verif/regress/smoke-tests-cv32a65x_noPMP.sh
new file mode 100644
index 0000000000..c9cc300705
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a65x_noPMP.sh
@@ -0,0 +1,72 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static \
+ -mcmodel=medany \
+ -fvisibility=hidden \
+ -nostartfiles \
+ -g \
+ ../tests/custom/common/syscalls.c \
+ ../tests/custom/common/crt.S \
+ -I../tests/custom/env \
+ -I../tests/custom/common"
+
+cd verif/sim/
+
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
+make -C ../.. clean
+make clean_all
+
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a65x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a65x_noPMP --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
+python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x_noPMP --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/smoke-tests-cv32a65x_noPMP_axi.sh b/verif/regress/smoke-tests-cv32a65x_noPMP_axi.sh
new file mode 100644
index 0000000000..bd8abea2ad
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a65x_noPMP_axi.sh
@@ -0,0 +1,71 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static \
+ -mcmodel=medany \
+ -fvisibility=hidden \
+ -nostartfiles \
+ -g \
+ ../tests/custom/common/syscalls.c \
+ ../tests/custom/common/crt.S \
+ -I../tests/custom/env \
+ -I../tests/custom/common"
+
+cd verif/sim/
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
+make -C ../.. clean
+make clean_all
+
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a65x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a65x_noPMP_axi --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
+python3 cva6.py --iss_timeout=30000 --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x_noPMP_axi --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/smoke-tests-cv32a65x_noPMP_noSuperScalar.sh b/verif/regress/smoke-tests-cv32a65x_noPMP_noSuperScalar.sh
new file mode 100644
index 0000000000..d92eada6e9
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a65x_noPMP_noSuperScalar.sh
@@ -0,0 +1,72 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static \
+ -mcmodel=medany \
+ -fvisibility=hidden \
+ -nostartfiles \
+ -g \
+ ../tests/custom/common/syscalls.c \
+ ../tests/custom/common/crt.S \
+ -I../tests/custom/env \
+ -I../tests/custom/common"
+
+cd verif/sim/
+
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
+make -C ../.. clean
+make clean_all
+
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a65x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a65x_noPMP_noSuperScalar --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
+python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x_noPMP_noSuperScalar --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/smoke-tests-cv32a65x_noPMP_noSuperScalar_axi.sh b/verif/regress/smoke-tests-cv32a65x_noPMP_noSuperScalar_axi.sh
new file mode 100644
index 0000000000..8280025540
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a65x_noPMP_noSuperScalar_axi.sh
@@ -0,0 +1,71 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static \
+ -mcmodel=medany \
+ -fvisibility=hidden \
+ -nostartfiles \
+ -g \
+ ../tests/custom/common/syscalls.c \
+ ../tests/custom/common/crt.S \
+ -I../tests/custom/env \
+ -I../tests/custom/common"
+
+cd verif/sim/
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
+make -C ../.. clean
+make clean_all
+
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a65x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a65x_noPMP_noSuperScalar_axi --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
+python3 cva6.py --iss_timeout=30000 --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x_noPMP_noSuperScalar_axi --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/smoke-tests-cv32a65x_sv32.sh b/verif/regress/smoke-tests-cv32a65x_sv32.sh
new file mode 100644
index 0000000000..70f5bf7444
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a65x_sv32.sh
@@ -0,0 +1,72 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static \
+ -mcmodel=medany \
+ -fvisibility=hidden \
+ -nostartfiles \
+ -g \
+ ../tests/custom/common/syscalls.c \
+ ../tests/custom/common/crt.S \
+ -I../tests/custom/env \
+ -I../tests/custom/common"
+
+cd verif/sim/
+
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
+make -C ../.. clean
+make clean_all
+
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a65x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a65x_sv32 --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
+python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x_sv32 --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/smoke-tests-cv32a65x_sv32_axi.sh b/verif/regress/smoke-tests-cv32a65x_sv32_axi.sh
new file mode 100644
index 0000000000..1942600e67
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a65x_sv32_axi.sh
@@ -0,0 +1,71 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static \
+ -mcmodel=medany \
+ -fvisibility=hidden \
+ -nostartfiles \
+ -g \
+ ../tests/custom/common/syscalls.c \
+ ../tests/custom/common/crt.S \
+ -I../tests/custom/env \
+ -I../tests/custom/common"
+
+cd verif/sim/
+
+# 32-bit configurations without MMU
+riscv_tests_list=(
+ rv32ui-p-add
+ rv32ui-p-lw
+ rv32ui-p-sw
+ rv32ui-p-beq
+ rv32ui-p-jal
+)
+
+make -C ../.. clean
+make clean_all
+
+for t in ${riscv_tests_list[@]} ; do
+ python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a65x-p.yaml --test $t --iss_yaml cva6.yaml --target cv32a65x_sv32_axi --iss=$DV_SIMULATORS $DV_OPTS
+ [[ $? > 0 ]] && ((errors++))
+done
+
+
+python3 cva6.py --iss_timeout=30000 --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a65x_sv32_axi --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/cv32a65x/linker/link.ld --gcc_opts="$CC_OPTS" $DV_OPTS --sv_seed 1
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/smoke-tests-cv32a6_imac_sv32_obi.sh b/verif/regress/smoke-tests-cv32a6_imac_sv32_obi.sh
new file mode 100644
index 0000000000..891e39b585
--- /dev/null
+++ b/verif/regress/smoke-tests-cv32a6_imac_sv32_obi.sh
@@ -0,0 +1,56 @@
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Jean-Roch COULON - Thales
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# install the required test suites
+source ./verif/regress/install-riscv-compliance.sh
+source ./verif/regress/install-riscv-tests.sh
+source ./verif/regress/install-riscv-arch-test.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+CC_OPTS="-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
+
+
+cd verif/sim/
+
+make -C ../.. clean
+make clean_all
+python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv32a60x.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32_obi --iss=$DV_SIMULATORS $DV_OPTS
+python3 cva6.py --testlist=../tests/testlist_riscv-tests-cv32a60x-p.yaml --test rv32ui-p-add --iss_yaml cva6.yaml --target cv32a6_imac_sv32_obi --iss=$DV_SIMULATORS $DV_OPTS
+python3 cva6.py --testlist=../tests/testlist_riscv-arch-test-cv32a60x.yaml --test rv32im-cadd-01 --iss_yaml cva6.yaml --target cv32a6_imac_sv32_obi --iss=$DV_SIMULATORS $DV_OPTS --linker=../../config/gen_from_riscv_config/linker/link.ld
+python3 cva6.py --c_tests ../tests/custom/hello_world/hello_world.c --iss_yaml cva6.yaml --target cv32a6_imac_sv32_obi --iss=$DV_SIMULATORS --linker=../../config/gen_from_riscv_config/linker/link.ld --gcc_opts="$CC_OPTS -nostdlib -lgcc" $DV_OPTS
+make -C ../.. clean
+make clean_all
+
+cd -
diff --git a/verif/regress/zcmt-tests-combined.sh b/verif/regress/zcmt-tests-combined.sh
new file mode 100644
index 0000000000..5894bb7fe2
--- /dev/null
+++ b/verif/regress/zcmt-tests-combined.sh
@@ -0,0 +1,67 @@
+#!/bin/bash
+# Copyright 2021 Thales DIS design services SAS
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Description: Combined smoke tests for all cv32a6x targets
+
+set -e
+
+SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+
+echo "=============================================="
+echo "Running combined zcmt tests for all targets"
+echo "=============================================="
+
+echo ""
+echo "----------------------------------------------"
+echo "Runningzcmt-tests-cv32a60x_zcmt_pmp_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/zcmt-tests-cv32a60x_zcmt_pmp_axi.sh"
+
+
+echo ""
+echo "----------------------------------------------"
+echo "Running zcmt-tests-cv32a60x_zcmt_pmp.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/zcmt-tests-cv32a60x_zcmt_pmp.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running zcmt-tests-cv32a65x_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/zcmt-tests-cv32a65x_axi.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running zcmt-tests-cv32a65x.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/zcmt-tests-cv32a65x.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running zcmt-tests-cv32a65x_noPMP_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/zcmt-tests-cv32a65x_noPMP_axi.sh"
+
+
+echo ""
+echo "----------------------------------------------"
+echo "Running zcmt-tests-cv32a65x_noPMP.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/zcmt-tests-cv32a65x_noPMP.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running zcmt-tests-cv32a65x_noPMP_noSuperScalar_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/zcmt-tests-cv32a65x_noPMP_noSuperScalar.sh"
+
+echo ""
+echo "----------------------------------------------"
+echo "Running zcmt-tests-cv32a65x_noPMP_noSuperScalar_axi.sh"
+echo "----------------------------------------------"
+source "$SCRIPT_DIR/zcmt-tests-cv32a65x_noPMP_noSuperScalar.sh"
\ No newline at end of file
diff --git a/verif/regress/zcmt-tests-cv32a60x_zcmt_pmp.sh b/verif/regress/zcmt-tests-cv32a60x_zcmt_pmp.sh
new file mode 100644
index 0000000000..7710130021
--- /dev/null
+++ b/verif/regress/zcmt-tests-cv32a60x_zcmt_pmp.sh
@@ -0,0 +1,46 @@
+# Copyright 2026 PlanV Technologies
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Angela Gonzalez - PlanV
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --target cv32a60x_zcmt_pmp --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long_ret.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a60x_zcmt_pmp --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a60x_zcmt_pmp --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a60x_zcmt_pmp --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/jvt_csr.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+
+make clean_all
+cd -
diff --git a/verif/regress/zcmt-tests-cv32a60x_zcmt_pmp_axi.sh b/verif/regress/zcmt-tests-cv32a60x_zcmt_pmp_axi.sh
new file mode 100644
index 0000000000..a108698702
--- /dev/null
+++ b/verif/regress/zcmt-tests-cv32a60x_zcmt_pmp_axi.sh
@@ -0,0 +1,46 @@
+# Copyright 2026 PlanV Technologies
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Angela Gonzalez - PlanV
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --target cv32a60x_zcmt_pmp_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long_ret.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a60x_zcmt_pmp_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a60x_zcmt_pmp_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a60x_zcmt_pmp_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/jvt_csr.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+
+make clean_all
+cd -
diff --git a/verif/regress/zcmt-tests-cv32a65x.sh b/verif/regress/zcmt-tests-cv32a65x.sh
new file mode 100644
index 0000000000..f6fa864d90
--- /dev/null
+++ b/verif/regress/zcmt-tests-cv32a65x.sh
@@ -0,0 +1,46 @@
+# Copyright 2026 PlanV Technologies
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Angela Gonzalez - PlanV
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --target cv32a65x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long_ret.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/jvt_csr.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+
+make clean_all
+cd -
diff --git a/verif/regress/zcmt-tests-cv32a65x_axi.sh b/verif/regress/zcmt-tests-cv32a65x_axi.sh
new file mode 100644
index 0000000000..5a7411755c
--- /dev/null
+++ b/verif/regress/zcmt-tests-cv32a65x_axi.sh
@@ -0,0 +1,46 @@
+# Copyright 2026 PlanV Technologies
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Angela Gonzalez - PlanV
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --target cv32a65x_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long_ret.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/jvt_csr.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+
+make clean_all
+cd -
diff --git a/verif/regress/zcmt-tests-cv32a65x_noPMP.sh b/verif/regress/zcmt-tests-cv32a65x_noPMP.sh
new file mode 100644
index 0000000000..27bca76198
--- /dev/null
+++ b/verif/regress/zcmt-tests-cv32a65x_noPMP.sh
@@ -0,0 +1,46 @@
+# Copyright 2026 PlanV Technologies
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Angela Gonzalez - PlanV
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --target cv32a65x_noPMP --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long_ret.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/jvt_csr.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+
+make clean_all
+cd -
diff --git a/verif/regress/zcmt-tests-cv32a65x_noPMP_axi.sh b/verif/regress/zcmt-tests-cv32a65x_noPMP_axi.sh
new file mode 100644
index 0000000000..ae5bbec931
--- /dev/null
+++ b/verif/regress/zcmt-tests-cv32a65x_noPMP_axi.sh
@@ -0,0 +1,46 @@
+# Copyright 2026 PlanV Technologies
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Angela Gonzalez - PlanV
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --target cv32a65x_noPMP_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long_ret.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/jvt_csr.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+
+make clean_all
+cd -
diff --git a/verif/regress/zcmt-tests-cv32a65x_noPMP_noSuperScalar.sh b/verif/regress/zcmt-tests-cv32a65x_noPMP_noSuperScalar.sh
new file mode 100644
index 0000000000..c18f0d05f8
--- /dev/null
+++ b/verif/regress/zcmt-tests-cv32a65x_noPMP_noSuperScalar.sh
@@ -0,0 +1,46 @@
+# Copyright 2026 PlanV Technologies
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Angela Gonzalez - PlanV
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --target cv32a65x_noPMP_noSuperScalar --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long_ret.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_noSuperScalar --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_noSuperScalar --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_noSuperScalar --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/jvt_csr.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+
+make clean_all
+cd -
diff --git a/verif/regress/zcmt-tests-cv32a65x_noPMP_noSuperScalar_axi.sh b/verif/regress/zcmt-tests-cv32a65x_noPMP_noSuperScalar_axi.sh
new file mode 100644
index 0000000000..cbad8f32bb
--- /dev/null
+++ b/verif/regress/zcmt-tests-cv32a65x_noPMP_noSuperScalar_axi.sh
@@ -0,0 +1,46 @@
+# Copyright 2026 PlanV Technologies
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https://solderpad.org/licenses/
+#
+# Original Author: Angela Gonzalez - PlanV
+
+# where are the tools
+if ! [ -n "$RISCV" ]; then
+ echo "Error: RISCV variable undefined"
+ return
+fi
+
+if ! [ -n "$DV_SIMULATORS" ]; then
+ DV_SIMULATORS=vcs-testharness,spike
+fi
+
+# install the required tools
+if [[ "$DV_SIMULATORS" == *"veri-testharness"* ]]; then
+ source ./verif/regress/install-verilator.sh
+fi
+source ./verif/regress/install-spike.sh
+
+# setup sim env
+source ./verif/sim/setup-env.sh
+
+echo "$SPIKE_INSTALL_DIR$"
+
+if ! [ -n "$UVM_VERBOSITY" ]; then
+ export UVM_VERBOSITY=UVM_NONE
+fi
+
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+
+cd verif/sim/
+make clean_all
+
+python3 cva6.py --target cv32a65x_noPMP_noSuperScalar_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long_ret.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_noSuperScalar_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jalt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_noSuperScalar_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/cm_jt_long.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+python3 cva6.py --target cv32a65x_noPMP_noSuperScalar_axi --iss=$DV_SIMULATORS --iss_yaml=cva6.yaml --asm_tests ../tests/custom/zcmt/jvt_csr.S --linker=../tests/custom/zcmt/link.ld --gcc_opts="-static -mcmodel=medany -fvisibility=hidden -nostdlib"
+
+make clean_all
+cd -
diff --git a/verif/sim/Makefile b/verif/sim/Makefile
index 05b63cea90..11eeed2bb6 100644
--- a/verif/sim/Makefile
+++ b/verif/sim/Makefile
@@ -355,8 +355,7 @@ questa_uvm_comp:
-suppress vlog-2745 -suppress vlog-8386 \
-suppress vlog-8607 \
+define+UNSUPPORTED_WITH+ \
- +define+QUESTA+ \
- $(cov-comp-opt) $(isscomp_opts)
+ +define+QUESTA
vopt -work $(VSIM_WORK_DIR) \
-64 +acc uvmt_cva6_tb -o uvmt_cva6_tb_opt
@@ -364,6 +363,7 @@ questa_uvm_run:
@echo "[QUESTA] Running Model"
vsim -64 \
$(COMMON_RUN_UVM_FLAGS) \
+ $(COMMON_RUN_ARGS) \
-sv_lib $(QUESTASIM_HOME)/uvm-1.2/linux_x86_64/uvm_dpi \
-c -do "run -all; " \
-work $(VSIM_WORK_DIR) -t 1ns \
@@ -371,13 +371,14 @@ questa_uvm_run:
-suppress 3829 -suppress vsim-8386\
+permissive \
-sv_seed 0 \
- $(cov-run-opt) $(issrun_opts) \
+ -noautoldlibpath \
+define+UNSUPPORTED_WITH+ \
+ $(issrun_opts) \
uvmt_cva6_tb_opt
+ $(tool_path)/spike-dasm --isa=$(variant) < ./trace_rvfi_hart_00.dasm > $(log)
+ grep $(isspostrun_opts) ./trace_rvfi_hart_00.dasm
# TODO: Add support for waveform collection.
- #$(tool_path)/spike-dasm --isa=$(variant) < $(path_var)/trace_rvfi_hart_00.dasm > $(log)
- #grep $(isspostrun_opts) $(path_var)/trace_rvfi_hart_00.dasm
questa-uvm:
make questa_uvm_comp
@@ -457,6 +458,7 @@ clean_all: vcs_clean_all
rm -f trace*.log
rm -f trace*.dasm
rm -f *.vpd *.fsdb *.vcd *.fst
+ rm -f *.trace
help:
@echo "Shell environment:"
diff --git a/verif/sim/cva6.py b/verif/sim/cva6.py
index 2244aa6814..26c9100508 100644
--- a/verif/sim/cva6.py
+++ b/verif/sim/cva6.py
@@ -943,18 +943,48 @@ def load_config(args, cwd):
args.mabi = "ilp32"
args.isa = "rv32imc_zba_zbb_zbs_zbc"
args.priv = "m"
+ elif base == "cv32a60x_zcmt_pmp":
+ args.mabi = "ilp32"
+ args.isa = "rv32imc_zba_zbb_zbs_zbc"
+ args.priv = "m"
elif base == "cv32a65x":
args.mabi = "ilp32"
args.isa = "rv32imc_zba_zbb_zbs_zbc"
args.priv = "m"
+ elif base == "cv32a65x_noPMP":
+ args.mabi = "ilp32"
+ args.isa = "rv32imc_zba_zbb_zbs_zbc"
+ args.priv = "m"
+ elif base == "cv32a65x_noPMP_noSuperScalar":
+ args.mabi = "ilp32"
+ args.isa = "rv32imc_zba_zbb_zbs_zbc"
+ args.priv = "m"
elif base == "cv32a60x_axi":
args.mabi = "ilp32"
args.isa = "rv32imc_zba_zbb_zbs_zbc"
args.priv = "m"
+ elif base == "cv32a60x_zcmt_pmp_axi":
+ args.mabi = "ilp32"
+ args.isa = "rv32imc_zba_zbb_zbs_zbc"
+ args.priv = "m"
elif base == "cv32a65x_axi":
args.mabi = "ilp32"
args.isa = "rv32imc_zba_zbb_zbs_zbc"
args.priv = "m"
+ elif base == "cv32a65x_noPMP_axi":
+ args.mabi = "ilp32"
+ args.isa = "rv32imc_zba_zbb_zbs_zbc"
+ args.priv = "m"
+ elif base == "cv32a65x_noPMP_noSuperScalar_axi":
+ args.mabi = "ilp32"
+ args.isa = "rv32imc_zba_zbb_zbs_zbc"
+ args.priv = "m"
+ elif base == "cv32a65x_sv32":
+ args.mabi = "ilp32"
+ args.isa = "rv32imc_zba_zbb_zbs_zbc"
+ elif base == "cv32a65x_sv32_axi":
+ args.mabi = "ilp32"
+ args.isa = "rv32imc_zba_zbb_zbs_zbc"
elif base == "cv64a6_mmu":
args.mabi = "lp64"
args.isa = "rv64imac_zba_zbb_zbs_zbc"
@@ -964,6 +994,9 @@ def load_config(args, cwd):
elif base == "cv32a6_imac_sv32":
args.mabi = "ilp32"
args.isa = "rv32imac_zbkb"
+ elif base == "cv32a6_imac_sv32_obi":
+ args.mabi = "ilp32"
+ args.isa = "rv32imac_zbkb"
elif base == "cv32a6_imafc_sv32":
args.mabi = "ilp32f"
args.isa = "rv32imafc"
@@ -1102,7 +1135,7 @@ def check_spike_version():
def check_verilator_version():
- REQUIRED_VERILATOR_VERSION = "5.008"
+ REQUIRED_VERILATOR_VERSION = "5.024"
verilator_version_string = run_cmd("verilator --version")
logging.info(f"Verilator Version: {verilator_version_string.strip()}")
diff --git a/verif/sim/dv b/verif/sim/dv
index f0c570d112..7e54b678ab 160000
--- a/verif/sim/dv
+++ b/verif/sim/dv
@@ -1 +1 @@
-Subproject commit f0c570d11236f94f9c5449870223a5ac717cc580
+Subproject commit 7e54b678ab7499040336255550cdbd99ae887431
diff --git a/verif/tb/uvmt/cva6_tb_wrapper.sv b/verif/tb/uvmt/cva6_tb_wrapper.sv
index 37a3330200..a8493a0c01 100644
--- a/verif/tb/uvmt/cva6_tb_wrapper.sv
+++ b/verif/tb/uvmt/cva6_tb_wrapper.sv
@@ -47,49 +47,44 @@ import "DPI-C" function byte get_section(
output longint address,
output longint len
);
-import "DPI-C" context function read_section_sv(
+import "DPI-C" context function void read_section_sv(
input longint address,
inout byte buffer[]
);
`endif
-module cva6_tb_wrapper
- import uvmt_cva6_pkg::*;
-#(
- parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
- parameter type rvfi_instr_t = logic,
- parameter type rvfi_csr_elmt_t = logic,
- parameter type rvfi_csr_t = logic,
- parameter type rvfi_probes_instr_t = logic,
- parameter type rvfi_probes_csr_t = logic,
- parameter type rvfi_probes_t = logic,
-
- // CVXIF Types
- localparam type readregflags_t = `READREGFLAGS_T(CVA6Cfg),
- localparam type writeregflags_t = `WRITEREGFLAGS_T(CVA6Cfg),
- localparam type id_t = `ID_T(CVA6Cfg),
- localparam type hartid_t = `HARTID_T(CVA6Cfg),
- localparam type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t),
- localparam type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg),
- localparam type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartit_t, id_t),
- localparam type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t),
- localparam type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t),
- localparam type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t),
- localparam type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t),
- localparam type cvxif_req_t =
- `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t),
- localparam type cvxif_resp_t =
- `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t),
- `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_fetch, CVA6Cfg.ObiFetchbusCfg),
- `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_store, CVA6Cfg.ObiStorebusCfg),
- `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_load, CVA6Cfg.ObiLoadbusCfg),
- `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_amo, CVA6Cfg.ObiAmobusCfg),
- `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_mmu_ptw, CVA6Cfg.ObiMmuPtwbusCfg),
- `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_zcmt, CVA6Cfg.ObiZcmtbusCfg),
- //
-
- parameter int unsigned AXI_USER_EN = 0,
- parameter int unsigned NUM_WORDS = 2 ** 25
+module cva6_tb_wrapper import uvmt_cva6_pkg::*; #(
+ parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+ parameter type rvfi_instr_t = logic,
+ parameter type rvfi_csr_elmt_t = logic,
+ parameter type rvfi_csr_t = logic,
+ parameter type rvfi_probes_instr_t = logic,
+ parameter type rvfi_probes_csr_t = logic,
+ parameter type rvfi_probes_t = logic,
+ parameter type rvfi_to_iti_t = logic,
+ // CVXIF Types
+ localparam type readregflags_t = `READREGFLAGS_T(CVA6Cfg),
+ localparam type writeregflags_t = `WRITEREGFLAGS_T(CVA6Cfg),
+ localparam type id_t = `ID_T(CVA6Cfg),
+ localparam type hartid_t = `HARTID_T(CVA6Cfg),
+ localparam type x_compressed_req_t = `X_COMPRESSED_REQ_T(CVA6Cfg, hartid_t),
+ localparam type x_compressed_resp_t = `X_COMPRESSED_RESP_T(CVA6Cfg),
+ localparam type x_issue_req_t = `X_ISSUE_REQ_T(CVA6Cfg, hartit_t, id_t),
+ localparam type x_issue_resp_t = `X_ISSUE_RESP_T(CVA6Cfg, writeregflags_t, readregflags_t),
+ localparam type x_register_t = `X_REGISTER_T(CVA6Cfg, hartid_t, id_t, readregflags_t),
+ localparam type x_commit_t = `X_COMMIT_T(CVA6Cfg, hartid_t, id_t),
+ localparam type x_result_t = `X_RESULT_T(CVA6Cfg, hartid_t, id_t, writeregflags_t),
+ localparam type cvxif_req_t = `CVXIF_REQ_T(CVA6Cfg, x_compressed_req_t, x_issue_req_t, x_register_req_t, x_commit_t),
+ localparam type cvxif_resp_t = `CVXIF_RESP_T(CVA6Cfg, x_compressed_resp_t, x_issue_resp_t, x_result_t),
+ //
+ `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_fetch, CVA6Cfg.ObiFetchbusCfg),
+ `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_store, CVA6Cfg.ObiStorebusCfg),
+ `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_load, CVA6Cfg.ObiLoadbusCfg),
+ `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_amo, CVA6Cfg.ObiAmobusCfg),
+ `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_mmu_ptw, CVA6Cfg.ObiMmuPtwbusCfg),
+ `OBI_LOCALPARAM_TYPE_GLOBAL_ALL(obi_zcmt, CVA6Cfg.ObiZcmtbusCfg),
+ parameter int unsigned AXI_USER_EN = 0,
+ parameter int unsigned NUM_WORDS = 2**25
) (
input logic clk_i,
input logic rst_ni,
@@ -149,6 +144,7 @@ module cva6_tb_wrapper
rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr;
rvfi_probes_t rvfi_probes;
+ rvfi_to_iti_t rvfi_to_iti;
rvfi_csr_t rvfi_csr;
assign rvfi_o = rvfi_instr;
assign rvfi_csr_o = rvfi_csr;
@@ -431,31 +427,31 @@ module cva6_tb_wrapper
assign obi_load_rsp.r.r_optional.rchk = obi_load_slave.rchk;
if (CVA6Cfg.MmuPresent) begin
- //assign obi_mmu_ptw_slave.req = i_cva6.obi_fetch_req.req;
- //assign obi_mmu_ptw_slave.addr = i_cva6.obi_fetch_req.a.addr;
- //assign obi_mmu_ptw_slave.we = i_cva6.obi_fetch_req.a.we;
- //assign obi_mmu_ptw_slave.be = i_cva6.obi_fetch_req.a.be;
- //assign obi_mmu_ptw_slave.wdata = i_cva6.obi_fetch_req.a.wdata;
- //assign obi_mmu_ptw_slave.auser = i_cva6.obi_fetch_req.a.a_optional.auser;
- //assign obi_mmu_ptw_slave.wuser = i_cva6.obi_fetch_req.a.a_optional.wuser;
- //assign obi_mmu_ptw_slave.aid = i_cva6.obi_fetch_req.a.aid;
- //assign obi_mmu_ptw_slave.atop = i_cva6.obi_fetch_req.a.a_optional.atop;
- //assign obi_mmu_ptw_slave.memtype = i_cva6.obi_fetch_req.a.a_optional.memtype;
- //assign obi_mmu_ptw_slave.prot = i_cva6.obi_fetch_req.a.a_optional.prot;
- //assign obi_mmu_ptw_slave.reqpar = i_cva6.obi_fetch_req.reqpar;
- //assign obi_mmu_ptw_slave.achk = i_cva6.obi_fetch_req.a.a_optional.achk;
- //assign obi_mmu_ptw_slave.rready = i_cva6.obi_fetch_req.rready;
- //assign obi_mmu_ptw_slave.rreadypar = i_cva6.obi_fetch_req.rreadypar;
- //assign i_cva6.obi_fetch_rsp.gnt = obi_mmu_ptw_slave.gnt;
- //assign i_cva6.obi_fetch_rsp.gntpar = obi_mmu_ptw_slave.gntpar;
- //assign i_cva6.obi_fetch_rsp.rvalid = obi_mmu_ptw_slave.rvalid;
- //assign i_cva6.obi_fetch_rsp.r.rdata = obi_mmu_ptw_slave.rdata;
- //assign i_cva6.obi_fetch_rsp.r.err = obi_mmu_ptw_slave.err;
- //assign i_cva6.obi_fetch_rsp.r.r_optional.ruser = obi_mmu_ptw_slave.ruser;
- //assign i_cva6.obi_fetch_rsp.r.rid = obi_mmu_ptw_slave.rid;
- //assign i_cva6.obi_fetch_rsp.r.r_optional.exokay = obi_mmu_ptw_slave.exokay;
- //assign i_cva6.obi_fetch_rsp.rvalidpar = obi_mmu_ptw_slave.rvalidpar;
- //assign i_cva6.obi_fetch_rsp.r.r_optional.rchk = obi_mmu_ptw_slave.rchk;
+ assign obi_mmu_ptw_slave.req = obi_mmu_ptw_req.req;
+ assign obi_mmu_ptw_slave.addr = obi_mmu_ptw_req.a.addr;
+ assign obi_mmu_ptw_slave.we = obi_mmu_ptw_req.a.we;
+ assign obi_mmu_ptw_slave.be = obi_mmu_ptw_req.a.be;
+ assign obi_mmu_ptw_slave.wdata = obi_mmu_ptw_req.a.wdata;
+ assign obi_mmu_ptw_slave.auser = obi_mmu_ptw_req.a.a_optional.auser;
+ assign obi_mmu_ptw_slave.wuser = obi_mmu_ptw_req.a.a_optional.wuser;
+ assign obi_mmu_ptw_slave.aid = obi_mmu_ptw_req.a.aid;
+ assign obi_mmu_ptw_slave.atop = obi_mmu_ptw_req.a.a_optional.atop;
+ assign obi_mmu_ptw_slave.memtype = obi_mmu_ptw_req.a.a_optional.memtype;
+ assign obi_mmu_ptw_slave.prot = obi_mmu_ptw_req.a.a_optional.prot;
+ assign obi_mmu_ptw_slave.reqpar = obi_mmu_ptw_req.reqpar;
+ assign obi_mmu_ptw_slave.achk = obi_mmu_ptw_req.a.a_optional.achk;
+ assign obi_mmu_ptw_slave.rready = obi_mmu_ptw_req.rready;
+ assign obi_mmu_ptw_slave.rreadypar = obi_mmu_ptw_req.rreadypar;
+ assign obi_mmu_ptw_rsp.gnt = obi_mmu_ptw_slave.gnt;
+ assign obi_mmu_ptw_rsp.gntpar = obi_mmu_ptw_slave.gntpar;
+ assign obi_mmu_ptw_rsp.rvalid = obi_mmu_ptw_slave.rvalid;
+ assign obi_mmu_ptw_rsp.r.rdata = obi_mmu_ptw_slave.rdata;
+ assign obi_mmu_ptw_rsp.r.err = obi_mmu_ptw_slave.err;
+ assign obi_mmu_ptw_rsp.r.r_optional.ruser = obi_mmu_ptw_slave.ruser;
+ assign obi_mmu_ptw_rsp.r.rid = obi_mmu_ptw_slave.rid;
+ assign obi_mmu_ptw_rsp.r.r_optional.exokay = obi_mmu_ptw_slave.exokay;
+ assign obi_mmu_ptw_rsp.rvalidpar = obi_mmu_ptw_slave.rvalidpar;
+ assign obi_mmu_ptw_rsp.r.r_optional.rchk = obi_mmu_ptw_slave.rchk;
end
if (CVA6Cfg.RVZCMT) begin
@@ -494,13 +490,17 @@ module cva6_tb_wrapper
.CVA6Cfg (CVA6Cfg),
.rvfi_instr_t(rvfi_instr_t),
.rvfi_csr_t(rvfi_csr_t),
- .rvfi_probes_t(rvfi_probes_t)
+ .rvfi_probes_instr_t(rvfi_probes_instr_t),
+ .rvfi_probes_csr_t(rvfi_probes_csr_t),
+ .rvfi_probes_t(rvfi_probes_t),
+ .rvfi_to_iti_t(rvfi_to_iti_t)
) i_cva6_rvfi (
.clk_i (clk_i),
.rst_ni (rst_ni),
.rvfi_probes_i(rvfi_probes),
- .rvfi_instr_o (rvfi_instr),
- .rvfi_csr_o (rvfi_csr)
+ .rvfi_instr_o(rvfi_instr),
+ .rvfi_to_iti_o (rvfi_to_iti),
+ .rvfi_csr_o(rvfi_csr)
);
rvfi_tracer #(
@@ -558,7 +558,7 @@ module cva6_tb_wrapper
AXI_BUS #(
.AXI_ADDR_WIDTH(CVA6Cfg.AxiAddrWidth),
.AXI_DATA_WIDTH(CVA6Cfg.AxiDataWidth),
- .AXI_ID_WIDTH (ariane_axi_soc::IdWidthSlave),
+ .AXI_ID_WIDTH (CVA6Cfg.AxiIdWidth),
.AXI_USER_WIDTH(CVA6Cfg.AxiUserWidth)
) cva6_axi_bus ();
@@ -569,7 +569,7 @@ module cva6_tb_wrapper
);
axi2mem #(
- .AXI_ID_WIDTH (ariane_axi_soc::IdWidthSlave),
+ .AXI_ID_WIDTH (CVA6Cfg.AxiIdWidth),
.AXI_ADDR_WIDTH(CVA6Cfg.AxiAddrWidth),
.AXI_DATA_WIDTH(CVA6Cfg.AxiDataWidth),
.AXI_USER_WIDTH(CVA6Cfg.AxiUserWidth)
diff --git a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv
index 02170fe60a..61c199efca 100644
--- a/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv
+++ b/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv
@@ -22,6 +22,7 @@ module uvmt_cva6_dut_wrap # (
parameter type rvfi_probes_instr_t = logic,
parameter type rvfi_probes_csr_t = logic,
parameter type rvfi_probes_t = logic,
+ parameter type rvfi_to_iti_t = logic,
//
parameter int unsigned AXI_USER_EN = 0,
parameter int unsigned NUM_WORDS = 2**25
@@ -58,6 +59,7 @@ module uvmt_cva6_dut_wrap # (
.rvfi_probes_instr_t(rvfi_probes_instr_t),
.rvfi_probes_csr_t ( rvfi_probes_csr_t ),
.rvfi_probes_t ( rvfi_probes_t ),
+ .rvfi_to_iti_t ( rvfi_to_iti_t ),
//
.AXI_USER_EN (AXI_USER_EN),
.NUM_WORDS (NUM_WORDS)
diff --git a/verif/tb/uvmt/uvmt_cva6_tb.sv b/verif/tb/uvmt/uvmt_cva6_tb.sv
index b0c060c217..e91d745722 100644
--- a/verif/tb/uvmt/uvmt_cva6_tb.sv
+++ b/verif/tb/uvmt/uvmt_cva6_tb.sv
@@ -41,6 +41,7 @@ module uvmt_cva6_tb;
localparam type rvfi_instr_t = `RVFI_INSTR_T(CVA6Cfg);
localparam type rvfi_csr_elmt_t = `RVFI_CSR_ELMT_T(CVA6Cfg);
localparam type rvfi_csr_t = `RVFI_CSR_T(CVA6Cfg, rvfi_csr_elmt_t);
+ localparam type rvfi_to_iti_t = `RVFI_TO_ITI_T(CVA6Cfg);
// RVFI PROBES
localparam type rvfi_probes_instr_t = `RVFI_PROBES_INSTR_T(CVA6Cfg);
@@ -163,16 +164,18 @@ module uvmt_cva6_tb;
.ACHK_WIDTH(CVA6Cfg.ObiLoadbusCfg.OptionalCfg.AChkWidth),
.RCHK_WIDTH(CVA6Cfg.ObiLoadbusCfg.OptionalCfg.RChkWidth),
.IS_1P2(1)) obi_load_assert(.obi(obi_load_if));
- //bind uvmt_cva6_dut_wrap uvma_obi_memory_assert_if_wrp #(
- // .AUSER_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.AUserWidth),
- // .WUSER_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.WUserWidth),
- // .RUSER_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.RUserWidth),
- // .ADDR_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.AddrWidth),
- // .DATA_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.DataWidth),
- // .ID_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.IdWidth),
- // .ACHK_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.AChkWidth),
- // .RCHK_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.RChkWidth),
- // .IS_1P2(1)) obi_mmu_ptw_assert(.obi(obi_mmu_ptw_if));
+ if (CVA6Cfg.MmuPresent) begin
+ bind uvmt_cva6_dut_wrap uvma_obi_memory_assert_if_wrp #(
+ .AUSER_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.AUserWidth),
+ .WUSER_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.WUserWidth),
+ .RUSER_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.RUserWidth),
+ .ADDR_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.AddrWidth),
+ .DATA_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.DataWidth),
+ .ID_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.IdWidth),
+ .ACHK_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.AChkWidth),
+ .RCHK_WIDTH(CVA6Cfg.ObiMmuPtwbusCfg.OptionalCfg.RChkWidth),
+ .IS_1P2(1)) obi_mmu_ptw_assert(.obi(obi_mmu_ptw_if));
+ end
end
uvme_cva6_core_cntrl_if core_cntrl_if();
@@ -219,6 +222,7 @@ module uvmt_cva6_tb;
.rvfi_probes_instr_t(rvfi_probes_instr_t ),
.rvfi_probes_csr_t ( rvfi_probes_csr_t ),
.rvfi_probes_t ( rvfi_probes_t ),
+ .rvfi_to_iti_t ( rvfi_to_iti_t ),
//
.AXI_USER_EN (CVA6Cfg.AXI_USER_EN),
.NUM_WORDS (NUM_WORDS)
@@ -507,6 +511,7 @@ module uvmt_cva6_tb;
uvm_config_db#(virtual uvma_obi_memory_if)::set(.cntxt(null), .inst_name("*obi_memory_load_agent"), .field_name("vif"), .value(obi_load_if));
uvm_config_db#(virtual uvma_obi_memory_if)::set(.cntxt(null), .inst_name("*obi_memory_amo_agent"), .field_name("vif"), .value(obi_amo_if));
uvm_config_db#(virtual uvma_obi_memory_if)::set(.cntxt(null), .inst_name("*obi_memory_zcmt_agent"), .field_name("vif"), .value(obi_zcmt_if));
+ uvm_config_db#(virtual uvma_obi_memory_if)::set(.cntxt(null), .inst_name("*obi_memory_mmu_ptw_agent"), .field_name("vif"), .value(obi_mmu_ptw_if));
uvm_config_db#(virtual uvmt_rvfi_if#( .CVA6Cfg(CVA6Cfg), .rvfi_instr_t(rvfi_instr_t), .rvfi_csr_t (rvfi_csr_t)))::set(.cntxt(null), .inst_name("*"), .field_name("rvfi_vif"), .value(rvfi_if));
uvm_config_db#(virtual uvme_cva6_core_cntrl_if)::set(.cntxt(null), .inst_name("*"), .field_name("core_cntrl_vif"), .value(core_cntrl_if));
uvm_config_db#(virtual uvma_interrupt_if)::set(.cntxt(null), .inst_name("*"), .field_name("interrupt_vif"), .value(interrupt_vif));
diff --git a/verif/tests/custom/ITI/iti_asm.S b/verif/tests/custom/ITI/iti_asm.S
new file mode 100644
index 0000000000..de4e8674f3
--- /dev/null
+++ b/verif/tests/custom/ITI/iti_asm.S
@@ -0,0 +1,35 @@
+// Copyright (c) 2025 Thales DIS design services SAS
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+// Author: Maxime Colson - Thales
+// Date: 20/03/2025
+// Contributors:
+// Darshak Sheladiya, SYSGO GmbH
+// Umberto Laghi, UNIBO
+
+.section .text
+.align 1
+.align 4
+.global branch_test
+.type branch_test, @function
+
+
+branch_test:
+ li x12,10
+ loop:
+ bne x13,x13, branch_test
+ bne x13,x13, branch_test
+ bne x13,x13, branch_test
+ bne x13,x13, branch_test
+ la x11, branch_test
+ lw x10, 0(x11)
+ bne x13,x13, branch_test
+ bne x13,x13, branch_test
+ bne x13,x13, branch_test
+ bne x13,x13, branch_test
+ bne x13,x13, branch_test
+ bne x13,x13, branch_test
+ addi x12,x12, -1
+ bne x12, x0, loop
+
+
+ jalr x0,0(ra)
diff --git a/verif/tests/custom/ITI/test_iti_asm.c b/verif/tests/custom/ITI/test_iti_asm.c
new file mode 100644
index 0000000000..bbb506395e
--- /dev/null
+++ b/verif/tests/custom/ITI/test_iti_asm.c
@@ -0,0 +1,16 @@
+// Copyright (c) 2025 Thales DIS design services SAS
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+// Author: Maxime Colson - Thales
+// Date: 20/03/2025
+// Contributors:
+// Darshak Sheladiya, SYSGO GmbH
+// Umberto Laghi, UNIBO
+
+//This test will be improved by taking into account other scenarios
+
+void branch_test();
+
+int main(int argc, char* arg[]) {
+ branch_test();
+ return 0;
+}
diff --git a/verif/tests/custom/ITI/test_iti_asm.o b/verif/tests/custom/ITI/test_iti_asm.o
new file mode 100755
index 0000000000..3aeb07aa9a
Binary files /dev/null and b/verif/tests/custom/ITI/test_iti_asm.o differ
diff --git a/verif/tests/custom/pmp/decreasing_entries_test.S b/verif/tests/custom/pmp/decreasing_entries_test.S
new file mode 100644
index 0000000000..9ad2c3dc7c
--- /dev/null
+++ b/verif/tests/custom/pmp/decreasing_entries_test.S
@@ -0,0 +1,98 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# decreasing_entries_test.S (TST04-4)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # Configure PMP using decreasing entries of TOR.
+
+ # From 0xB000_0000 to 0xC000_0000 Read-Write-Execute.
+ li t0, 0x30000000
+ csrw pmpaddr7, t0
+
+ # From 0xA000_0000 to 0xB000_0000 Read-Write-Execute.
+ li t0, 0x2c000000
+ csrw pmpaddr6, t0
+
+ # From 0x9000_0000 to 0xA000_0000 Read-Write-Execute.
+ li t0, 0x28000000
+ csrw pmpaddr5, t0
+
+ # From 0x8000_0000 to 0x9000_0000 Read-Write-Execute.
+ li t0, 0x24000000
+ csrw pmpaddr4, t0
+
+ # From 0x0002_0000 to 0x8000_0000 no Permissions.
+ li t0, 0x20000000
+ csrw pmpaddr3, t0
+
+ # From 0x0001_0000 to 0x0002_0000 only Execute.
+ li t0, 0x00008000
+ csrw pmpaddr2, t0
+
+ # From 0x0000_1000 to 0x0001_0000 no Permissions.
+ li t0, 0x00004000
+ csrw pmpaddr1, t0
+
+ # From 0x0000_0000 to 0x0000_1000 only Execute.
+ li t0, 0x00000400
+ csrw pmpaddr0, t0
+
+
+ # Addr 4-7 configs, written in cfg1, with LOCK OFF, and TOR.
+ li t0, 0x0f0f0f0f
+ csrw pmpcfg1, t0
+
+ # Addr 0-3 configs, written in cfg0, with LOCK OFF, and TOR.
+ li t0, 0x080c080c
+ csrw pmpcfg0, t0
+
+
+ # Do the READ-WRITE test.
+
+ # Check 1 read-write test, at 0x8800_0000.
+ li t1, 0x88000000
+ li t2, 0xEFFACED1
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 2 read-write test, at 0x9800_0000.
+ li t1, 0x98000000
+ li t2, 0xACCEDED2
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 3 read-write test, at 0xA800_0000.
+ li t1, 0xA8000000
+ li t2, 0xDEFACED3
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 4 read-write test, at 0xB800_0000.
+ li t1, 0xB8000000
+ li t2, 0xDEC0DED4
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/pmp/defined_matches_test.S b/verif/tests/custom/pmp/defined_matches_test.S
new file mode 100644
index 0000000000..2df2a84512
--- /dev/null
+++ b/verif/tests/custom/pmp/defined_matches_test.S
@@ -0,0 +1,48 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# defined_matches_test.S (TST10-1, TST10-2)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # Check a Memory Access succeeds if no PMP entry is defined.
+ li t1, 0x90000000
+ li t2, 0xC0D1F1ED
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Set up a PMP entry using NAPOT, from 0x8000_0000 to 0xA0000_0000, Read-Write-Execute.
+ li t0, 0x0000001f
+ csrw pmpcfg0, t0
+ csrr t1, pmpcfg0
+ bne t0, t1, fail
+ li t0, 0x23ffffff
+ csrw pmpaddr0, t0
+ csrr t1, pmpaddr0
+ bne t0, t1, fail
+
+ # Check a memory access succeeds if no PMP entry matches.
+ li t1, 0xB0000000
+ li t2, 0xCA5CADED
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/pmp/double_entries_test.S b/verif/tests/custom/pmp/double_entries_test.S
new file mode 100644
index 0000000000..a7e7ef988d
--- /dev/null
+++ b/verif/tests/custom/pmp/double_entries_test.S
@@ -0,0 +1,72 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# double_entries_test.S (TST04-2)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # Set up PMP using NAPOT, from 0xB000_0000 to 0xC000_0000, Read-Write.
+ li t0, 0x001b0000
+ csrw pmpcfg1, t0
+ csrr t1, pmpcfg1
+ bne t0, t1, fail
+ li t0, 0x2dffffff
+ csrw pmpaddr6, t0
+ csrr t1, pmpaddr6
+ bne t0, t1, fail
+
+ # Set up PMP using NAPOT, from 0x8000_0000 to 0x9000_0000, Read-Write.
+ li t0, 0x001b0000
+ csrw pmpcfg0, t0
+ csrr t1, pmpcfg0
+ bne t0, t1, fail
+ li t0, 0x21ffffff
+ csrw pmpaddr2, t0
+ csrr t1, pmpaddr2
+ bne t0, t1, fail
+
+ # Read-Write check in 0xB800_0000.
+ li t1, 0xB8000000
+ li t2, 0xC0D1F1ED
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Read-Write check in 0x8800_0000.
+ li t1, 0x88000000
+ li t2, 0xCA5CADED
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check that all other addr / cfg are zero.
+ csrr t0, pmpaddr0
+ bne t0, zero, fail
+ csrr t0, pmpaddr1
+ bne t0, zero, fail
+ csrr t0, pmpaddr3
+ bne t0, zero, fail
+ csrr t0, pmpaddr4
+ bne t0, zero, fail
+ csrr t0, pmpaddr5
+ bne t0, zero, fail
+ csrr t0, pmpaddr7
+ bne t0, zero, fail
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/pmp/exact_csrr_test.S b/verif/tests/custom/pmp/exact_csrr_test.S
new file mode 100644
index 0000000000..a5839c029e
--- /dev/null
+++ b/verif/tests/custom/pmp/exact_csrr_test.S
@@ -0,0 +1,99 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# exact_csrr_test.S (TST05-1)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # Write in addresses and check what is written.
+
+ # Checking PMP ADDR 0
+ li t0, 0xFACADE00
+ csrw pmpaddr0, t0
+ csrr t1, pmpaddr0
+ bne t0, t1, fail
+ csrw pmpaddr0, zero
+
+ # Checking PMP ADDR 1
+ li t0, 0xFACADE02
+ csrw pmpaddr1, t0
+ csrr t1, pmpaddr1
+ bne t0, t1, fail
+ csrw pmpaddr1, zero
+
+ # Checking PMP ADDR 2
+ li t0, 0xFACADE04
+ csrw pmpaddr2, t0
+ csrr t1, pmpaddr2
+ bne t0, t1, fail
+ csrw pmpaddr2, zero
+
+ # Checking PMP ADDR 3
+ li t0, 0xFACADE06
+ csrw pmpaddr3, t0
+ csrr t1, pmpaddr3
+ bne t0, t1, fail
+ csrw pmpaddr3, zero
+
+ # Checking PMP ADDR 4
+ li t0, 0xFACADE08
+ csrw pmpaddr4, t0
+ csrr t1, pmpaddr4
+ bne t0, t1, fail
+ csrw pmpaddr4, zero
+
+ # Checking PMP ADDR 5
+ li t0, 0xFACADE0A
+ csrw pmpaddr5, t0
+ csrr t1, pmpaddr5
+ bne t0, t1, fail
+ csrw pmpaddr5, zero
+
+ # Checking PMP ADDR 6
+ li t0, 0xFACADE0C
+ csrw pmpaddr6, t0
+ csrr t1, pmpaddr6
+ bne t0, t1, fail
+ csrw pmpaddr6, zero
+
+ # Checking PMP ADDR 7
+ li t0, 0xFACADE0E
+ csrw pmpaddr7, t0
+ csrr t1, pmpaddr7
+ bne t0, t1, fail
+ csrw pmpaddr7, zero
+
+
+ # Write in configurations and check what is written, except for the reserved combinations with R=0 and W=1.
+
+ # Checking PMP CFG 0
+ li t0, 0x01030304
+ csrw pmpcfg0, t0
+ csrr t1, pmpcfg0
+ bne t0, t1, fail
+ csrw pmpcfg0, zero
+
+ # Checking PMP CFG 1
+ li t0, 0x04050507
+ csrw pmpcfg1, t0
+ csrr t1, pmpcfg1
+ bne t0, t1, fail
+ csrw pmpcfg1, zero
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/pmp/granularity_test.S b/verif/tests/custom/pmp/granularity_test.S
new file mode 100644
index 0000000000..e341d0c8ad
--- /dev/null
+++ b/verif/tests/custom/pmp/granularity_test.S
@@ -0,0 +1,44 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# granularity_test.S (TST01)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # Configure PMP to find its granularity.
+
+ # Write all zeroes in cfg0.
+ li t0, 0
+ csrw pmpcfg0, t0
+
+ # Write all ones in addr0.
+ li t1, -1
+ csrw pmpaddr0, t1
+
+ # Read the value back.
+ csrr t2, pmpaddr0
+
+ # Check for granularity 8 = 2^(1+2) <=> G = 1.
+ # As per: https://docs.openhwgroup.org/projects/cva6-user-manual/01_cva6_user/PMP.html
+ # Which states: The PMP grain is 2**G+2. Only a PMP granularity of 8 bytes (G=1) is supported in CVA6.
+ # And from the RISC-V Spec: G is the index of the least-significant bit set, the PMP granularity is 2^(G+2) bytes.
+ li t3, 0xFFFFFFFE
+ bne t2, t3, fail
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/pmp/locked_outside_napot_test.S b/verif/tests/custom/pmp/locked_outside_napot_test.S
new file mode 100644
index 0000000000..cc653b1cff
--- /dev/null
+++ b/verif/tests/custom/pmp/locked_outside_napot_test.S
@@ -0,0 +1,45 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# locked_outside_napot_test.S (TST14-26, TST14-36)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # Set up PMP using NAPOT, from 0x8000_0000 to 0xB000_0000.
+ li t2, 0x25ffffff
+ csrw pmpaddr0, t2
+
+ # Configure it with LOCK ON, Read-Write-Execute.
+ li t0, 0x0000009f
+ csrw pmpcfg0, t0
+ csrr t1, pmpcfg0
+ bne t0, t1, fail
+
+ # Check pmpaddr after switching to NAPOT (and lock)
+ csrr t0, pmpaddr0
+ bne t0, t2, fail
+
+ # Check a memory access succeeds when outside the LOCKED entry.
+ li t1, 0xB8000000
+ li t2, 0xC0D1F1ED
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/pmp/locked_outside_tor_test.S b/verif/tests/custom/pmp/locked_outside_tor_test.S
new file mode 100644
index 0000000000..6db06b9566
--- /dev/null
+++ b/verif/tests/custom/pmp/locked_outside_tor_test.S
@@ -0,0 +1,61 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# locked_outside_tor_test.S (TST16-26, TST16-36)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # From 0x0000_0000 to 0x0000_1000 only Execute.
+ li t0, 0x00000400
+ csrw pmpaddr0, t0
+
+ # From 0x0000_1000 to 0x0001_0000 no Permissions.
+ li t0, 0x00004000
+ csrw pmpaddr1, t0
+
+ # From 0x0001_0000 to 0x0002_0000 only Execute.
+ li t0, 0x00008000
+ csrw pmpaddr2, t0
+
+ # From 0x0002_0000 to 0x8000_0000 no Permissions.
+ li t0, 0x20000000
+ csrw pmpaddr3, t0
+
+ # From 0x8000_0000 to 0xB000_0000 Read-Write-Execute.
+ li t0, 0x2C000000
+ csrw pmpaddr4, t0
+
+ # Configure the TOR areas with LOCK ON.
+ li t0, 0x888c888c
+ csrw pmpcfg0, t0
+ csrr t1, pmpcfg0
+ bne t0, t1, fail
+ li t0, 0x0000008f
+ csrw pmpcfg1, t0
+ csrr t1, pmpcfg1
+ bne t0, t1, fail
+
+ # Check a memory access succeeds when outside the LOCKED entry.
+ li t1, 0xB8000000
+ li t2, 0xC0D1F1ED
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/pmp/lsu_napot_test.S b/verif/tests/custom/pmp/lsu_napot_test.S
new file mode 100644
index 0000000000..9a7c97fb4e
--- /dev/null
+++ b/verif/tests/custom/pmp/lsu_napot_test.S
@@ -0,0 +1,111 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# lsu_napot_test.S (TST14-11, TST14-21, TST14-31)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # Configure PMP using NAPOT.
+
+ # From 0x0000_0000 to 0x0000_1000 only Execute.
+ li t0, 0x000001ff
+ csrw pmpaddr0, t0
+
+ # From 0x0001_0000 to 0x0002_0000 only Execute.
+ li t0, 0x00005fff
+ csrw pmpaddr1, t0
+
+ # From 0x8000_0000 to 0xC000_0000 Read-Write-Execute.
+ li t0, 0x27ffffff
+ csrw pmpaddr2, t0
+
+
+ # Addr 0-2 configs, written in cfg0, with LOCK OFF, and NAPOT.
+ li t0, 0x001f1c1c
+ csrw pmpcfg0, t0
+ csrr t1, pmpcfg0
+ bne t0, t1, fail
+
+
+ # Do the READ-WRITE test.
+
+ # Check 1 read-write test, at 0x8000_0000.
+ li t1, 0x80000000
+ li t2, 0xEFFACED1
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 2 read-write test, at 0x9000_0000.
+ li t1, 0x90000000
+ li t2, 0xACCEDED2
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 3 read-write test, at 0xA000_0000.
+ li t1, 0xA0000000
+ li t2, 0xDEFACED3
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 4 read-write test, at 0xB000_0000.
+ li t1, 0xB0000000
+ li t2, 0xDEC0DED4
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+
+ # Do the EXEC "RET" test.
+
+ # Exec test 1, at 0x0000_0800.
+ li t0, 0x00000800
+ li t1, 0x8082
+ sw t1, 0(t0)
+ lw t2, 0(t0)
+ bne t1, t2, fail
+ jalr t0
+
+ # Exec test 2, at 0x0001_8000.
+ li t0, 0x00018000
+ li t1, 0x8082
+ sw t1, 0(t0)
+ lw t2, 0(t0)
+ bne t1, t2, fail
+ jalr t0
+
+ # Exec test 3, at 0x9800_0000.
+ li t0, 0x98000000
+ li t1, 0x8082
+ sw t1, 0(t0)
+ lw t2, 0(t0)
+ bne t1, t2, fail
+ jalr t0
+
+ # Exec test 4, at 0xA800_0000.
+ li t0, 0xA8000000
+ li t1, 0x8082
+ sw t1, 0(t0)
+ lw t2, 0(t0)
+ bne t1, t2, fail
+ jalr t0
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/pmp/lsu_tor_test.S b/verif/tests/custom/pmp/lsu_tor_test.S
new file mode 100644
index 0000000000..7989e66239
--- /dev/null
+++ b/verif/tests/custom/pmp/lsu_tor_test.S
@@ -0,0 +1,125 @@
+# ------------------------------------------------------------------------------
+# Copyright 2024 Robert Bosch GmbH
+#
+# SPDX-License-Identifier: SHL-0.51
+#
+# Original Author: Konstantinos LEVENTOS - Robert Bosch France SAS
+# ------------------------------------------------------------------------------
+# lsu_tor_test.S (TST16-11, TST16-21, TST16-31)
+# ------------------------------------------------------------------------------
+
+ .text
+ .globl main
+main:
+
+ # Configure PMP using TOR.
+
+ # From 0x0000_0000 to 0x0000_1000 only Execute.
+ li t0, 0x00000400
+ csrw pmpaddr0, t0
+
+ # From 0x0000_1000 to 0x0001_0000 no Permissions.
+ li t0, 0x00004000
+ csrw pmpaddr1, t0
+
+ # From 0x0001_0000 to 0x0002_0000 only Execute.
+ li t0, 0x00008000
+ csrw pmpaddr2, t0
+
+ # From 0x0002_0000 to 0x8000_0000 no Permissions.
+ li t0, 0x20000000
+ csrw pmpaddr3, t0
+
+ # From 0x8000_0000 to 0xC000_0000 Read-Write-Execute.
+ li t0, 0x30000000
+ csrw pmpaddr4, t0
+
+
+ # Addr 0-3 configs, written in cfg0, with LOCK OFF, and TOR.
+ li t0, 0x080c080c
+ csrw pmpcfg0, t0
+ csrr t1, pmpcfg0
+ bne t0, t1, fail
+
+ # Addr 4 config, written in cfg1, with LOCK OFF, and TOR.
+ li t0, 0x0000000f
+ csrw pmpcfg1, t0
+ csrr t1, pmpcfg1
+ bne t0, t1, fail
+
+
+ # Do the READ-WRITE test.
+
+ # Check 1 read-write test, at 0x8000_0000.
+ li t1, 0x80000000
+ li t2, 0xEFFACED1
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 2 read-write test, at 0x9000_0000.
+ li t1, 0x90000000
+ li t2, 0xACCEDED2
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 3 read-write test, at 0xA000_0000.
+ li t1, 0xA0000000
+ li t2, 0xDEFACED3
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+ # Check 4 read-write test, at 0xB000_0000.
+ li t1, 0xB0000000
+ li t2, 0xDEC0DED4
+ sw t2, 0(t1)
+ lw t3, 0(t1)
+ bne t2, t3, fail
+
+
+ # Do the EXEC "RET" test.
+
+ # Exec test 1, at 0x0000_0800.
+ li t0, 0xA0000800
+ li t1, 0x8082
+ sw t1, 0(t0)
+ lw t2, 0(t0)
+ bne t1, t2, fail
+ jalr t0
+
+ # Exec test 2, at 0x0001_8000.
+ li t0, 0xB0018000
+ li t1, 0x8082
+ sw t1, 0(t0)
+ lw t2, 0(t0)
+ bne t1, t2, fail
+ jalr t0
+
+ # Exec test 3, at 0x9800_0000.
+ li t0, 0x98000000
+ li t1, 0x8082
+ sw t1, 0(t0)
+ lw t2, 0(t0)
+ bne t1, t2, fail
+ jalr t0
+
+ # Exec test 4, at 0xA800_0000.
+ li t0, 0xA8000000
+ li t1, 0x8082
+ sw t1, 0(t0)
+ lw t2, 0(t0)
+ bne t1, t2, fail
+ jalr t0
+
+
+pass:
+ # Success post-processing
+ li a0, 0x0;
+ jal exit;
+
+fail:
+ # Failure post-processing
+ li a0, 0x1;
+ jal exit;
diff --git a/verif/tests/custom/zcmt/cm_jalt.S b/verif/tests/custom/zcmt/cm_jalt.S
deleted file mode 100644
index 46e1ff79ab..0000000000
--- a/verif/tests/custom/zcmt/cm_jalt.S
+++ /dev/null
@@ -1,62 +0,0 @@
-.globl _start
-_start:
- la t0, trap_handler
- csrw mtvec, t0
-
- la a1, target1
- la t0, __jvt_base$
-
- sw a1, 128(t0) //cm.jalt entry start from index >=32
-
- csrw jvt, t0
-
- fence.i
- # Perform jump using the index from JVT
- cm.jalt 32
-
- li t1, 1
- addi x20,x20, 9
- j write_tohost
-
-
-
-
-exit:
- j write_tohost
-
-write_tohost:
- li x1, 1
- la t0, tohost
- sw x1, 0(t0)
- j write_tohost
-
-
-# Jump Vector Table (JVT) Section
-# Create a separate section for the JVT
-.section .riscv.jvt, "ax"
-.align 6 # Align the JVT on a 64-byte boundary (6 = 2^6 = 64)
-__jvt_base$:
- .word 0x80000054
- .word 0x80000800
- .word 0x80000802
- .word 0x80000804
-
-# Target Addresses (Where cm.jalt will jump)
-target0:
- li x5, 99
- j write_tohost
-target1:
- li x2, 99
- j write_tohost
-
-target2:
- addi x2,x20, 5
- j write_tohost
-
-
-trap_handler:
- j exit
-
-
-.align 6; .global tohost; tohost: .dword 0;
-.align 6; .global fromhost; fromhost: .dword 0;
diff --git a/verif/tests/custom/zcmt/cm_jalt_long.S b/verif/tests/custom/zcmt/cm_jalt_long.S
index 51f0e3f002..9031394875 100644
--- a/verif/tests/custom/zcmt/cm_jalt_long.S
+++ b/verif/tests/custom/zcmt/cm_jalt_long.S
@@ -1,59 +1,57 @@
-.globl _start
-_start:
- la t0, trap_handler
- csrw mtvec, t0
+#include "riscv_test.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+ la t0, trap_handler
+ csrw mtvec, t0
la a1, target1
la t0, __jvt_base$
- sw a1, 128(t0) //cm.jalt entry start from index >=32
+ sw a1, 256(t0) // cm.jalt entry start from index >=32
- csrw jvt, t0
+ csrw jvt, t0
fence.i
- # Perform jump using the index from JVT
- cm.jalt 32
+ //Perform jump using the index from JVT
+ cm.jalt 64
li t1, 1
- addi x20,x20, 9
- j write_tohost
-
-
-exit:
- j write_tohost
-
-write_tohost:
- li x1, 1
- la t0, tohost
- sw x1, 0(t0)
- j write_tohost
-
+ addi x20, x20, 9
+ j failure
-# Jump Vector Table (JVT) Section
-# Create a separate section for the JVT
-.section .riscv.jvt, "ax"
-.align 6 # Align the JVT on a 64-byte boundary (6 = 2^6 = 64)
-__jvt_base$:
- .word 0x80000054
- .word 0x80000800
- .word 0x80000802
- .word 0x80000804
-
-# Target Addresses (Where cm.jalt will jump)
-.align 20
target1:
li x2, 99
- lui t0, %hi(write_tohost) # Load upper 20 bits of target address into t0
- addi t0, t0, %lo(write_tohost) # Add the lower 12 bits to t0
- jalr x0, 0(t0)
-
-
+ j success
trap_handler:
- lui t0, %hi(write_tohost) # Load upper 20 bits of target address into t0
- addi t0, t0, %lo(write_tohost) # Add the lower 12 bits to t0
- jalr x0, 0(t0)
-
-
-.align 6; .global tohost; tohost: .dword 0;
-.align 6; .global fromhost; fromhost: .dword 0;
\ No newline at end of file
+ j failure
+
+// jump to this label to signal that the test failed
+failure:
+ li x1, 1
+ slli x1, x1, 1
+ addi x1, x1, 1
+ sw x1, tohost, t5
+ self_loop_2: j self_loop_2
+
+// jump to this label to signal that the test passed
+success:
+ li x1, 0
+ slli x1, x1, 1
+ addi x1, x1, 1
+ sw x1, tohost, t5
+ self_loop: j self_loop
+
+
+RVTEST_CODE_END
+
+.data
+RVTEST_DATA_BEGIN
+ // Jump Vector Table (JVT)
+ .align 6
+__jvt_base$:
+ .space 256 //Reserve space for indices 0-63 (unused)
+ .word 0 //Entry 64 (will be overwritten by test)
+RVTEST_DATA_END
\ No newline at end of file
diff --git a/verif/tests/custom/zcmt/cm_jalt_long_ret.S b/verif/tests/custom/zcmt/cm_jalt_long_ret.S
index 7dfc6f0a4b..28969110ee 100644
--- a/verif/tests/custom/zcmt/cm_jalt_long_ret.S
+++ b/verif/tests/custom/zcmt/cm_jalt_long_ret.S
@@ -1,57 +1,61 @@
-.globl _start
-_start:
- la t0, trap_handler
- csrw mtvec, t0
+#include "riscv_test.h"
+
+RVTEST_RV32M
+RVTEST_CODE_BEGIN
+
+ la t0, trap_handler
+ csrw mtvec, t0
la a1, target1
la t0, __jvt_base$
- sw a1, 128(t0) //cm.jalt entry start from index >=32
+ sw a1, 256(t0) // cm.jalt entry start from index >=32
- csrw jvt, t0
+ csrw jvt, t0
fence.i
- # Perform jump using the index from JVT
- cm.jalt 32
+ cm.jalt 64
li t1, 1
- addi x20,x20, 9
- j write_tohost
-
-
-exit:
- j write_tohost
+ addi x20, x20, 9
+ j success
-write_tohost:
- li x1, 1
- la t0, tohost
- sw x1, 0(t0)
- j write_tohost
+// trap handler
+trap_handler:
+ lui t0, %hi(failure) # Load upper 20 bits of address of 'success' into t0
+ addi t0, t0, %lo(failure) # Add lower 12 bits to form full address
+ jalr x0, 0(t0)
-# Jump Vector Table (JVT) Section
-# Create a separate section for the JVT
-.section .riscv.jvt, "ax"
-.align 6 # Align the JVT on a 64-byte boundary (6 = 2^6 = 64)
-__jvt_base$:
- .word 0x80000054
- .word 0x80000800
- .word 0x80000802
- .word 0x80000804
-
-# Target Addresses (Where cm.jalt will jump)
-.align 20
+// cm.jalt target label
target1:
li x2, 99
ret
-
-
-trap_handler:
- lui t0, %hi(write_tohost) # Load upper 20 bits of target address into t0
- addi t0, t0, %lo(write_tohost) # Add the lower 12 bits to t0
- jalr x0, 0(t0)
+// failure path
+failure:
+ li x1, 1
+ slli x1, x1, 1
+ addi x1, x1, 1
+ sw x1, tohost, t5
+ self_loop_2: j self_loop_2
+
+// success path
+success:
+ li x1, 0
+ slli x1, x1, 1
+ addi x1, x1, 1
+ sw x1, tohost, t5
+ self_loop: j self_loop
-.align 6; .global tohost; tohost: .dword 0;
-.align 6; .global fromhost; fromhost: .dword 0;
\ No newline at end of file
+RVTEST_CODE_END
+
+.data
+RVTEST_DATA_BEGIN
+
+ .align 6
+__jvt_base$:
+ .space 256 //Reserve space for indices 0-63 (unused)
+ .word 0 //Entry 64 (will be overwritten by test)
+RVTEST_DATA_END
\ No newline at end of file
diff --git a/verif/tests/custom/zcmt/cm_jalt_ret.S b/verif/tests/custom/zcmt/cm_jalt_ret.S
deleted file mode 100644
index 82eaf36cc4..0000000000
--- a/verif/tests/custom/zcmt/cm_jalt_ret.S
+++ /dev/null
@@ -1,62 +0,0 @@
-.globl _start
-_start:
- la t0, trap_handler
- csrw mtvec, t0
-
- la a1, target1
- la t0, __jvt_base$
-
- sw a1, 128(t0) //cm.jalt entry start from index >=32
-
- csrw jvt, t0
-
- fence.i
- # Perform jump using the index from JVT
- cm.jalt 32
-
- li t1, 1
- addi x20,x20, 9
- j write_tohost
-
-
-
-
-exit:
- j write_tohost
-
-write_tohost:
- li x1, 1
- la t0, tohost
- sw x1, 0(t0)
- j write_tohost
-
-
-# Jump Vector Table (JVT) Section
-# Create a separate section for the JVT
-.section .riscv.jvt, "ax"
-.align 6 # Align the JVT on a 64-byte boundary (6 = 2^6 = 64)
-__jvt_base$:
- .word 0x80000054
- .word 0x80000800
- .word 0x80000802
- .word 0x80000804
-
-# Target Addresses (Where cm.jalt will jump)
-target0:
- li x5, 9
- j write_tohost
-target1:
- li x2, 99
- ret
-
-target2:
- addi x2,x20, 5
- j write_tohost
-
-
-trap_handler:
- j exit
-
-
-.align 6; .global tohost; tohost: .dword 0;
-.align 6; .global fromhost; fromhost: .dword 0;
diff --git a/verif/tests/custom/zcmt/cm_jt.S b/verif/tests/custom/zcmt/cm_jt.S
deleted file mode 100644
index b2dd88a49c..0000000000
--- a/verif/tests/custom/zcmt/cm_jt.S
+++ /dev/null
@@ -1,58 +0,0 @@
-.globl _start
-_start:
- la t0, trap_handler
- csrw mtvec, t0
-
- la a1, target1
- la t0, __jvt_base$
-
- sw a1, 0(t0)
-
- csrw jvt, t0
-
- fence.i
-
- cm.jt 0 # Perform jump using the index 0 from JVT
-
- addi x18,x18, 3
- j target2
-
-exit:
- j write_tohost
-
-write_tohost:
- li x1, 1
- la t0, tohost
- sw x1, 0(t0)
- j write_tohost
-
-
-
-# Jump Vector Table (JVT) Section
-# Create a separate section for the JVT
-.section .riscv.jvt, "ax"
-.align 6 # Align the JVT on a 64-byte boundary (6 = 2^6 = 64)
-__jvt_base$:
- .word 0x80000054
- .word 0x80000800
- .word 0x80000802
- .word 0x80000804
-
-# Target Addresses (Where cm.jt will jump)
-target0:
- j write_tohost
-target1:
- addi x6,x0, 7
- j write_tohost
-
-target2:
- addi x2,x20, 5
- j write_tohost
-
-
-trap_handler:
- j exit
-
-
-.align 6; .global tohost; tohost: .dword 0;
-.align 6; .global fromhost; fromhost: .dword 0;
diff --git a/verif/tests/custom/zcmt/cm_jt_long.S b/verif/tests/custom/zcmt/cm_jt_long.S
index 5020464ad2..29a7aa658d 100644
--- a/verif/tests/custom/zcmt/cm_jt_long.S
+++ b/verif/tests/custom/zcmt/cm_jt_long.S
@@ -1,5 +1,8 @@
-.globl _start
-_start:
+#include "riscv_test.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
la t0, trap_handler
csrw mtvec, t0
@@ -15,38 +18,48 @@ _start:
cm.jt 0 # Perform jump using the index 0 from JVT
addi x18,x18, 3
+ j failure
-write_tohost:
- li x1, 1
- la t0, tohost
- sw x1, 0(t0)
- j write_tohost
-
-
-
-# Jump Vector Table (JVT) Section
-# Create a separate section for the JVT
-.section .riscv.jvt, "ax"
-.align 6 # Align the JVT on a 64-byte boundary (6 = 2^6 = 64)
-__jvt_base$:
- .word 0x80000054
- .word 0x80000800
- .word 0x80000802
- .word 0x80000804
-
-# Target Addresses (Where cm.jt will jump)
-.align 20
target1:
addi x6,x0, 6
- la t0, write_tohost # Load upper 20 bits of target address into t0
- jalr x0, 0(t0)
+ j success
trap_handler:
- lui t0, %hi(write_tohost) # Load upper 20 bits of target address into t0
- addi t0, t0, %lo(write_tohost) # Add the lower 12 bits to t0
+ lui t0, %hi(failure) # Load upper 20 bits of target address into t0
+ addi t0, t0, %lo(failure) # Add the lower 12 bits to t0
jalr x0, 0(t0)
+// jump to this label to signal that the test failed
+failure:
+ li x1, 1
+ slli x1, x1, 1
+ addi x1, x1, 1
+ sw x1, tohost, t5
+ self_loop_2: j self_loop_2
+
+// jump to this label to signal that the test passed
+success:
+ li x1, 0
+ slli x1, x1, 1
+ addi x1, x1, 1
+ sw x1, tohost, t5
+ self_loop: j self_loop
+
+RVTEST_CODE_END
+
+.data
+
+RVTEST_DATA_BEGIN
+
+// Jump Vector Table (JVT) Section
+.section .riscv.jvt, "ax"
+.align 6
+__jvt_base$:
+ .word 0x80000054
+ .word 0x80000800
+ .word 0x80000802
+ .word 0x80000804
+
-.align 6; .global tohost; tohost: .dword 0;
-.align 6; .global fromhost; fromhost: .dword 0;
+RVTEST_DATA_END
\ No newline at end of file
diff --git a/verif/tests/custom/zcmt/encoding.h b/verif/tests/custom/zcmt/encoding.h
new file mode 100644
index 0000000000..696e55a9ed
--- /dev/null
+++ b/verif/tests/custom/zcmt/encoding.h
@@ -0,0 +1,1475 @@
+// See LICENSE for license details.
+
+#ifndef RISCV_CSR_ENCODING_H
+#define RISCV_CSR_ENCODING_H
+
+#define MSTATUS_UIE 0x00000001
+#define MSTATUS_SIE 0x00000002
+#define MSTATUS_HIE 0x00000004
+#define MSTATUS_MIE 0x00000008
+#define MSTATUS_UPIE 0x00000010
+#define MSTATUS_SPIE 0x00000020
+#define MSTATUS_HPIE 0x00000040
+#define MSTATUS_MPIE 0x00000080
+#define MSTATUS_SPP 0x00000100
+#define MSTATUS_HPP 0x00000600
+#define MSTATUS_MPP 0x00001800
+#define MSTATUS_FS 0x00006000
+#define MSTATUS_XS 0x00018000
+#define MSTATUS_MPRV 0x00020000
+#define MSTATUS_SUM 0x00040000
+#define MSTATUS_MXR 0x00080000
+#define MSTATUS_TVM 0x00100000
+#define MSTATUS_TW 0x00200000
+#define MSTATUS_TSR 0x00400000
+#define MSTATUS32_SD 0x80000000
+#define MSTATUS_UXL 0x0000000300000000
+#define MSTATUS_SXL 0x0000000C00000000
+#define MSTATUS64_SD 0x8000000000000000
+
+#define SSTATUS_UIE 0x00000001
+#define SSTATUS_SIE 0x00000002
+#define SSTATUS_UPIE 0x00000010
+#define SSTATUS_SPIE 0x00000020
+#define SSTATUS_SPP 0x00000100
+#define SSTATUS_FS 0x00006000
+#define SSTATUS_XS 0x00018000
+#define SSTATUS_SUM 0x00040000
+#define SSTATUS_MXR 0x00080000
+#define SSTATUS32_SD 0x80000000
+#define SSTATUS_UXL 0x0000000300000000
+#define SSTATUS64_SD 0x8000000000000000
+
+#define DCSR_XDEBUGVER (3U<<30)
+#define DCSR_NDRESET (1<<29)
+#define DCSR_FULLRESET (1<<28)
+#define DCSR_EBREAKM (1<<15)
+#define DCSR_EBREAKH (1<<14)
+#define DCSR_EBREAKS (1<<13)
+#define DCSR_EBREAKU (1<<12)
+#define DCSR_STOPCYCLE (1<<10)
+#define DCSR_STOPTIME (1<<9)
+#define DCSR_CAUSE (7<<6)
+#define DCSR_DEBUGINT (1<<5)
+#define DCSR_HALT (1<<3)
+#define DCSR_STEP (1<<2)
+#define DCSR_PRV (3<<0)
+
+#define DCSR_CAUSE_NONE 0
+#define DCSR_CAUSE_SWBP 1
+#define DCSR_CAUSE_HWBP 2
+#define DCSR_CAUSE_DEBUGINT 3
+#define DCSR_CAUSE_STEP 4
+#define DCSR_CAUSE_HALT 5
+
+#define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
+#define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
+#define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
+
+#define MCONTROL_SELECT (1<<19)
+#define MCONTROL_TIMING (1<<18)
+#define MCONTROL_ACTION (0x3f<<12)
+#define MCONTROL_CHAIN (1<<11)
+#define MCONTROL_MATCH (0xf<<7)
+#define MCONTROL_M (1<<6)
+#define MCONTROL_H (1<<5)
+#define MCONTROL_S (1<<4)
+#define MCONTROL_U (1<<3)
+#define MCONTROL_EXECUTE (1<<2)
+#define MCONTROL_STORE (1<<1)
+#define MCONTROL_LOAD (1<<0)
+
+#define MCONTROL_TYPE_NONE 0
+#define MCONTROL_TYPE_MATCH 2
+
+#define MCONTROL_ACTION_DEBUG_EXCEPTION 0
+#define MCONTROL_ACTION_DEBUG_MODE 1
+#define MCONTROL_ACTION_TRACE_START 2
+#define MCONTROL_ACTION_TRACE_STOP 3
+#define MCONTROL_ACTION_TRACE_EMIT 4
+
+#define MCONTROL_MATCH_EQUAL 0
+#define MCONTROL_MATCH_NAPOT 1
+#define MCONTROL_MATCH_GE 2
+#define MCONTROL_MATCH_LT 3
+#define MCONTROL_MATCH_MASK_LOW 4
+#define MCONTROL_MATCH_MASK_HIGH 5
+
+#define MIP_SSIP (1 << IRQ_S_SOFT)
+#define MIP_HSIP (1 << IRQ_H_SOFT)
+#define MIP_MSIP (1 << IRQ_M_SOFT)
+#define MIP_STIP (1 << IRQ_S_TIMER)
+#define MIP_HTIP (1 << IRQ_H_TIMER)
+#define MIP_MTIP (1 << IRQ_M_TIMER)
+#define MIP_SEIP (1 << IRQ_S_EXT)
+#define MIP_HEIP (1 << IRQ_H_EXT)
+#define MIP_MEIP (1 << IRQ_M_EXT)
+
+#define SIP_SSIP MIP_SSIP
+#define SIP_STIP MIP_STIP
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
+
+#define SATP32_MODE 0x80000000
+#define SATP32_ASID 0x7FC00000
+#define SATP32_PPN 0x003FFFFF
+#define SATP64_MODE 0xF000000000000000
+#define SATP64_ASID 0x0FFFF00000000000
+#define SATP64_PPN 0x00000FFFFFFFFFFF
+
+#define SATP_MODE_OFF 0
+#define SATP_MODE_SV32 1
+#define SATP_MODE_SV39 8
+#define SATP_MODE_SV48 9
+#define SATP_MODE_SV57 10
+#define SATP_MODE_SV64 11
+
+#define PMP_R 0x01
+#define PMP_W 0x02
+#define PMP_X 0x04
+#define PMP_A 0x18
+#define PMP_L 0x80
+#define PMP_SHIFT 2
+
+#define PMP_TOR 0x08
+#define PMP_NA4 0x10
+#define PMP_NAPOT 0x18
+
+#define IRQ_S_SOFT 1
+#define IRQ_H_SOFT 2
+#define IRQ_M_SOFT 3
+#define IRQ_S_TIMER 5
+#define IRQ_H_TIMER 6
+#define IRQ_M_TIMER 7
+#define IRQ_S_EXT 9
+#define IRQ_H_EXT 10
+#define IRQ_M_EXT 11
+#define IRQ_COP 12
+#define IRQ_HOST 13
+
+#define DEFAULT_RSTVEC 0x00001000
+#define CLINT_BASE 0x02000000
+#define CLINT_SIZE 0x000c0000
+#define EXT_IO_BASE 0x40000000
+#define DRAM_BASE 0x80000000
+
+// page table entry (PTE) fields
+#define PTE_V 0x001 // Valid
+#define PTE_R 0x002 // Read
+#define PTE_W 0x004 // Write
+#define PTE_X 0x008 // Execute
+#define PTE_U 0x010 // User
+#define PTE_G 0x020 // Global
+#define PTE_A 0x040 // Accessed
+#define PTE_D 0x080 // Dirty
+#define PTE_SOFT 0x300 // Reserved for Software
+
+#define PTE_PPN_SHIFT 10
+
+#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
+
+#ifdef __riscv
+
+#if __riscv_xlen == 64
+# define MSTATUS_SD MSTATUS64_SD
+# define SSTATUS_SD SSTATUS64_SD
+# define RISCV_PGLEVEL_BITS 9
+# define SATP_MODE SATP64_MODE
+#else
+# define MSTATUS_SD MSTATUS32_SD
+# define SSTATUS_SD SSTATUS32_SD
+# define RISCV_PGLEVEL_BITS 10
+# define SATP_MODE SATP32_MODE
+#endif
+#define RISCV_PGSHIFT 12
+#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
+
+#ifndef __ASSEMBLER__
+
+#ifdef __GNUC__
+
+#define read_csr(reg) ({ unsigned long __tmp; \
+ asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
+ __tmp; })
+
+#define write_csr(reg, val) ({ \
+ asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
+
+#define swap_csr(reg, val) ({ unsigned long __tmp; \
+ asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
+ __tmp; })
+
+#define set_csr(reg, bit) ({ unsigned long __tmp; \
+ asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+ __tmp; })
+
+#define clear_csr(reg, bit) ({ unsigned long __tmp; \
+ asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
+ __tmp; })
+
+#define rdtime() read_csr(time)
+#define rdcycle() read_csr(cycle)
+#define rdinstret() read_csr(instret)
+
+#endif
+
+#endif
+
+#endif
+
+#endif
+/* Automatically generated by parse-opcodes. */
+#ifndef RISCV_ENCODING_H
+#define RISCV_ENCODING_H
+#define MATCH_BEQ 0x63
+#define MASK_BEQ 0x707f
+#define MATCH_BNE 0x1063
+#define MASK_BNE 0x707f
+#define MATCH_BLT 0x4063
+#define MASK_BLT 0x707f
+#define MATCH_BGE 0x5063
+#define MASK_BGE 0x707f
+#define MATCH_BLTU 0x6063
+#define MASK_BLTU 0x707f
+#define MATCH_BGEU 0x7063
+#define MASK_BGEU 0x707f
+#define MATCH_JALR 0x67
+#define MASK_JALR 0x707f
+#define MATCH_JAL 0x6f
+#define MASK_JAL 0x7f
+#define MATCH_LUI 0x37
+#define MASK_LUI 0x7f
+#define MATCH_AUIPC 0x17
+#define MASK_AUIPC 0x7f
+#define MATCH_ADDI 0x13
+#define MASK_ADDI 0x707f
+#define MATCH_SLLI 0x1013
+#define MASK_SLLI 0xfc00707f
+#define MATCH_SLTI 0x2013
+#define MASK_SLTI 0x707f
+#define MATCH_SLTIU 0x3013
+#define MASK_SLTIU 0x707f
+#define MATCH_XORI 0x4013
+#define MASK_XORI 0x707f
+#define MATCH_SRLI 0x5013
+#define MASK_SRLI 0xfc00707f
+#define MATCH_SRAI 0x40005013
+#define MASK_SRAI 0xfc00707f
+#define MATCH_ORI 0x6013
+#define MASK_ORI 0x707f
+#define MATCH_ANDI 0x7013
+#define MASK_ANDI 0x707f
+#define MATCH_ADD 0x33
+#define MASK_ADD 0xfe00707f
+#define MATCH_SUB 0x40000033
+#define MASK_SUB 0xfe00707f
+#define MATCH_SLL 0x1033
+#define MASK_SLL 0xfe00707f
+#define MATCH_SLT 0x2033
+#define MASK_SLT 0xfe00707f
+#define MATCH_SLTU 0x3033
+#define MASK_SLTU 0xfe00707f
+#define MATCH_XOR 0x4033
+#define MASK_XOR 0xfe00707f
+#define MATCH_SRL 0x5033
+#define MASK_SRL 0xfe00707f
+#define MATCH_SRA 0x40005033
+#define MASK_SRA 0xfe00707f
+#define MATCH_OR 0x6033
+#define MASK_OR 0xfe00707f
+#define MATCH_AND 0x7033
+#define MASK_AND 0xfe00707f
+#define MATCH_ADDIW 0x1b
+#define MASK_ADDIW 0x707f
+#define MATCH_SLLIW 0x101b
+#define MASK_SLLIW 0xfe00707f
+#define MATCH_SRLIW 0x501b
+#define MASK_SRLIW 0xfe00707f
+#define MATCH_SRAIW 0x4000501b
+#define MASK_SRAIW 0xfe00707f
+#define MATCH_ADDW 0x3b
+#define MASK_ADDW 0xfe00707f
+#define MATCH_SUBW 0x4000003b
+#define MASK_SUBW 0xfe00707f
+#define MATCH_SLLW 0x103b
+#define MASK_SLLW 0xfe00707f
+#define MATCH_SRLW 0x503b
+#define MASK_SRLW 0xfe00707f
+#define MATCH_SRAW 0x4000503b
+#define MASK_SRAW 0xfe00707f
+#define MATCH_LB 0x3
+#define MASK_LB 0x707f
+#define MATCH_LH 0x1003
+#define MASK_LH 0x707f
+#define MATCH_LW 0x2003
+#define MASK_LW 0x707f
+#define MATCH_LD 0x3003
+#define MASK_LD 0x707f
+#define MATCH_LBU 0x4003
+#define MASK_LBU 0x707f
+#define MATCH_LHU 0x5003
+#define MASK_LHU 0x707f
+#define MATCH_LWU 0x6003
+#define MASK_LWU 0x707f
+#define MATCH_SB 0x23
+#define MASK_SB 0x707f
+#define MATCH_SH 0x1023
+#define MASK_SH 0x707f
+#define MATCH_SW 0x2023
+#define MASK_SW 0x707f
+#define MATCH_SD 0x3023
+#define MASK_SD 0x707f
+#define MATCH_FENCE 0xf
+#define MASK_FENCE 0x707f
+#define MATCH_FENCE_I 0x100f
+#define MASK_FENCE_I 0x707f
+#define MATCH_MUL 0x2000033
+#define MASK_MUL 0xfe00707f
+#define MATCH_MULH 0x2001033
+#define MASK_MULH 0xfe00707f
+#define MATCH_MULHSU 0x2002033
+#define MASK_MULHSU 0xfe00707f
+#define MATCH_MULHU 0x2003033
+#define MASK_MULHU 0xfe00707f
+#define MATCH_DIV 0x2004033
+#define MASK_DIV 0xfe00707f
+#define MATCH_DIVU 0x2005033
+#define MASK_DIVU 0xfe00707f
+#define MATCH_REM 0x2006033
+#define MASK_REM 0xfe00707f
+#define MATCH_REMU 0x2007033
+#define MASK_REMU 0xfe00707f
+#define MATCH_MULW 0x200003b
+#define MASK_MULW 0xfe00707f
+#define MATCH_DIVW 0x200403b
+#define MASK_DIVW 0xfe00707f
+#define MATCH_DIVUW 0x200503b
+#define MASK_DIVUW 0xfe00707f
+#define MATCH_REMW 0x200603b
+#define MASK_REMW 0xfe00707f
+#define MATCH_REMUW 0x200703b
+#define MASK_REMUW 0xfe00707f
+#define MATCH_AMOADD_W 0x202f
+#define MASK_AMOADD_W 0xf800707f
+#define MATCH_AMOXOR_W 0x2000202f
+#define MASK_AMOXOR_W 0xf800707f
+#define MATCH_AMOOR_W 0x4000202f
+#define MASK_AMOOR_W 0xf800707f
+#define MATCH_AMOAND_W 0x6000202f
+#define MASK_AMOAND_W 0xf800707f
+#define MATCH_AMOMIN_W 0x8000202f
+#define MASK_AMOMIN_W 0xf800707f
+#define MATCH_AMOMAX_W 0xa000202f
+#define MASK_AMOMAX_W 0xf800707f
+#define MATCH_AMOMINU_W 0xc000202f
+#define MASK_AMOMINU_W 0xf800707f
+#define MATCH_AMOMAXU_W 0xe000202f
+#define MASK_AMOMAXU_W 0xf800707f
+#define MATCH_AMOSWAP_W 0x800202f
+#define MASK_AMOSWAP_W 0xf800707f
+#define MATCH_LR_W 0x1000202f
+#define MASK_LR_W 0xf9f0707f
+#define MATCH_SC_W 0x1800202f
+#define MASK_SC_W 0xf800707f
+#define MATCH_AMOADD_D 0x302f
+#define MASK_AMOADD_D 0xf800707f
+#define MATCH_AMOXOR_D 0x2000302f
+#define MASK_AMOXOR_D 0xf800707f
+#define MATCH_AMOOR_D 0x4000302f
+#define MASK_AMOOR_D 0xf800707f
+#define MATCH_AMOAND_D 0x6000302f
+#define MASK_AMOAND_D 0xf800707f
+#define MATCH_AMOMIN_D 0x8000302f
+#define MASK_AMOMIN_D 0xf800707f
+#define MATCH_AMOMAX_D 0xa000302f
+#define MASK_AMOMAX_D 0xf800707f
+#define MATCH_AMOMINU_D 0xc000302f
+#define MASK_AMOMINU_D 0xf800707f
+#define MATCH_AMOMAXU_D 0xe000302f
+#define MASK_AMOMAXU_D 0xf800707f
+#define MATCH_AMOSWAP_D 0x800302f
+#define MASK_AMOSWAP_D 0xf800707f
+#define MATCH_LR_D 0x1000302f
+#define MASK_LR_D 0xf9f0707f
+#define MATCH_SC_D 0x1800302f
+#define MASK_SC_D 0xf800707f
+#define MATCH_ECALL 0x73
+#define MASK_ECALL 0xffffffff
+#define MATCH_EBREAK 0x100073
+#define MASK_EBREAK 0xffffffff
+#define MATCH_URET 0x200073
+#define MASK_URET 0xffffffff
+#define MATCH_SRET 0x10200073
+#define MASK_SRET 0xffffffff
+#define MATCH_MRET 0x30200073
+#define MASK_MRET 0xffffffff
+#define MATCH_DRET 0x7b200073
+#define MASK_DRET 0xffffffff
+#define MATCH_SFENCE_VMA 0x12000073
+#define MASK_SFENCE_VMA 0xfe007fff
+#define MATCH_WFI 0x10500073
+#define MASK_WFI 0xffffffff
+#define MATCH_CSRRW 0x1073
+#define MASK_CSRRW 0x707f
+#define MATCH_CSRRS 0x2073
+#define MASK_CSRRS 0x707f
+#define MATCH_CSRRC 0x3073
+#define MASK_CSRRC 0x707f
+#define MATCH_CSRRWI 0x5073
+#define MASK_CSRRWI 0x707f
+#define MATCH_CSRRSI 0x6073
+#define MASK_CSRRSI 0x707f
+#define MATCH_CSRRCI 0x7073
+#define MASK_CSRRCI 0x707f
+#define MATCH_FADD_S 0x53
+#define MASK_FADD_S 0xfe00007f
+#define MATCH_FSUB_S 0x8000053
+#define MASK_FSUB_S 0xfe00007f
+#define MATCH_FMUL_S 0x10000053
+#define MASK_FMUL_S 0xfe00007f
+#define MATCH_FDIV_S 0x18000053
+#define MASK_FDIV_S 0xfe00007f
+#define MATCH_FSGNJ_S 0x20000053
+#define MASK_FSGNJ_S 0xfe00707f
+#define MATCH_FSGNJN_S 0x20001053
+#define MASK_FSGNJN_S 0xfe00707f
+#define MATCH_FSGNJX_S 0x20002053
+#define MASK_FSGNJX_S 0xfe00707f
+#define MATCH_FMIN_S 0x28000053
+#define MASK_FMIN_S 0xfe00707f
+#define MATCH_FMAX_S 0x28001053
+#define MASK_FMAX_S 0xfe00707f
+#define MATCH_FSQRT_S 0x58000053
+#define MASK_FSQRT_S 0xfff0007f
+#define MATCH_FADD_D 0x2000053
+#define MASK_FADD_D 0xfe00007f
+#define MATCH_FSUB_D 0xa000053
+#define MASK_FSUB_D 0xfe00007f
+#define MATCH_FMUL_D 0x12000053
+#define MASK_FMUL_D 0xfe00007f
+#define MATCH_FDIV_D 0x1a000053
+#define MASK_FDIV_D 0xfe00007f
+#define MATCH_FSGNJ_D 0x22000053
+#define MASK_FSGNJ_D 0xfe00707f
+#define MATCH_FSGNJN_D 0x22001053
+#define MASK_FSGNJN_D 0xfe00707f
+#define MATCH_FSGNJX_D 0x22002053
+#define MASK_FSGNJX_D 0xfe00707f
+#define MATCH_FMIN_D 0x2a000053
+#define MASK_FMIN_D 0xfe00707f
+#define MATCH_FMAX_D 0x2a001053
+#define MASK_FMAX_D 0xfe00707f
+#define MATCH_FCVT_S_D 0x40100053
+#define MASK_FCVT_S_D 0xfff0007f
+#define MATCH_FCVT_D_S 0x42000053
+#define MASK_FCVT_D_S 0xfff0007f
+#define MATCH_FSQRT_D 0x5a000053
+#define MASK_FSQRT_D 0xfff0007f
+#define MATCH_FADD_Q 0x6000053
+#define MASK_FADD_Q 0xfe00007f
+#define MATCH_FSUB_Q 0xe000053
+#define MASK_FSUB_Q 0xfe00007f
+#define MATCH_FMUL_Q 0x16000053
+#define MASK_FMUL_Q 0xfe00007f
+#define MATCH_FDIV_Q 0x1e000053
+#define MASK_FDIV_Q 0xfe00007f
+#define MATCH_FSGNJ_Q 0x26000053
+#define MASK_FSGNJ_Q 0xfe00707f
+#define MATCH_FSGNJN_Q 0x26001053
+#define MASK_FSGNJN_Q 0xfe00707f
+#define MATCH_FSGNJX_Q 0x26002053
+#define MASK_FSGNJX_Q 0xfe00707f
+#define MATCH_FMIN_Q 0x2e000053
+#define MASK_FMIN_Q 0xfe00707f
+#define MATCH_FMAX_Q 0x2e001053
+#define MASK_FMAX_Q 0xfe00707f
+#define MATCH_FCVT_S_Q 0x40300053
+#define MASK_FCVT_S_Q 0xfff0007f
+#define MATCH_FCVT_Q_S 0x46000053
+#define MASK_FCVT_Q_S 0xfff0007f
+#define MATCH_FCVT_D_Q 0x42300053
+#define MASK_FCVT_D_Q 0xfff0007f
+#define MATCH_FCVT_Q_D 0x46100053
+#define MASK_FCVT_Q_D 0xfff0007f
+#define MATCH_FSQRT_Q 0x5e000053
+#define MASK_FSQRT_Q 0xfff0007f
+#define MATCH_FLE_S 0xa0000053
+#define MASK_FLE_S 0xfe00707f
+#define MATCH_FLT_S 0xa0001053
+#define MASK_FLT_S 0xfe00707f
+#define MATCH_FEQ_S 0xa0002053
+#define MASK_FEQ_S 0xfe00707f
+#define MATCH_FLE_D 0xa2000053
+#define MASK_FLE_D 0xfe00707f
+#define MATCH_FLT_D 0xa2001053
+#define MASK_FLT_D 0xfe00707f
+#define MATCH_FEQ_D 0xa2002053
+#define MASK_FEQ_D 0xfe00707f
+#define MATCH_FLE_Q 0xa6000053
+#define MASK_FLE_Q 0xfe00707f
+#define MATCH_FLT_Q 0xa6001053
+#define MASK_FLT_Q 0xfe00707f
+#define MATCH_FEQ_Q 0xa6002053
+#define MASK_FEQ_Q 0xfe00707f
+#define MATCH_FCVT_W_S 0xc0000053
+#define MASK_FCVT_W_S 0xfff0007f
+#define MATCH_FCVT_WU_S 0xc0100053
+#define MASK_FCVT_WU_S 0xfff0007f
+#define MATCH_FCVT_L_S 0xc0200053
+#define MASK_FCVT_L_S 0xfff0007f
+#define MATCH_FCVT_LU_S 0xc0300053
+#define MASK_FCVT_LU_S 0xfff0007f
+#define MATCH_FMV_X_W 0xe0000053
+#define MASK_FMV_X_W 0xfff0707f
+#define MATCH_FCLASS_S 0xe0001053
+#define MASK_FCLASS_S 0xfff0707f
+#define MATCH_FCVT_W_D 0xc2000053
+#define MASK_FCVT_W_D 0xfff0007f
+#define MATCH_FCVT_WU_D 0xc2100053
+#define MASK_FCVT_WU_D 0xfff0007f
+#define MATCH_FCVT_L_D 0xc2200053
+#define MASK_FCVT_L_D 0xfff0007f
+#define MATCH_FCVT_LU_D 0xc2300053
+#define MASK_FCVT_LU_D 0xfff0007f
+#define MATCH_FMV_X_D 0xe2000053
+#define MASK_FMV_X_D 0xfff0707f
+#define MATCH_FCLASS_D 0xe2001053
+#define MASK_FCLASS_D 0xfff0707f
+#define MATCH_FCVT_W_Q 0xc6000053
+#define MASK_FCVT_W_Q 0xfff0007f
+#define MATCH_FCVT_WU_Q 0xc6100053
+#define MASK_FCVT_WU_Q 0xfff0007f
+#define MATCH_FCVT_L_Q 0xc6200053
+#define MASK_FCVT_L_Q 0xfff0007f
+#define MATCH_FCVT_LU_Q 0xc6300053
+#define MASK_FCVT_LU_Q 0xfff0007f
+#define MATCH_FMV_X_Q 0xe6000053
+#define MASK_FMV_X_Q 0xfff0707f
+#define MATCH_FCLASS_Q 0xe6001053
+#define MASK_FCLASS_Q 0xfff0707f
+#define MATCH_FCVT_S_W 0xd0000053
+#define MASK_FCVT_S_W 0xfff0007f
+#define MATCH_FCVT_S_WU 0xd0100053
+#define MASK_FCVT_S_WU 0xfff0007f
+#define MATCH_FCVT_S_L 0xd0200053
+#define MASK_FCVT_S_L 0xfff0007f
+#define MATCH_FCVT_S_LU 0xd0300053
+#define MASK_FCVT_S_LU 0xfff0007f
+#define MATCH_FMV_W_X 0xf0000053
+#define MASK_FMV_W_X 0xfff0707f
+#define MATCH_FCVT_D_W 0xd2000053
+#define MASK_FCVT_D_W 0xfff0007f
+#define MATCH_FCVT_D_WU 0xd2100053
+#define MASK_FCVT_D_WU 0xfff0007f
+#define MATCH_FCVT_D_L 0xd2200053
+#define MASK_FCVT_D_L 0xfff0007f
+#define MATCH_FCVT_D_LU 0xd2300053
+#define MASK_FCVT_D_LU 0xfff0007f
+#define MATCH_FMV_D_X 0xf2000053
+#define MASK_FMV_D_X 0xfff0707f
+#define MATCH_FCVT_Q_W 0xd6000053
+#define MASK_FCVT_Q_W 0xfff0007f
+#define MATCH_FCVT_Q_WU 0xd6100053
+#define MASK_FCVT_Q_WU 0xfff0007f
+#define MATCH_FCVT_Q_L 0xd6200053
+#define MASK_FCVT_Q_L 0xfff0007f
+#define MATCH_FCVT_Q_LU 0xd6300053
+#define MASK_FCVT_Q_LU 0xfff0007f
+#define MATCH_FMV_Q_X 0xf6000053
+#define MASK_FMV_Q_X 0xfff0707f
+#define MATCH_FLW 0x2007
+#define MASK_FLW 0x707f
+#define MATCH_FLD 0x3007
+#define MASK_FLD 0x707f
+#define MATCH_FLQ 0x4007
+#define MASK_FLQ 0x707f
+#define MATCH_FSW 0x2027
+#define MASK_FSW 0x707f
+#define MATCH_FSD 0x3027
+#define MASK_FSD 0x707f
+#define MATCH_FSQ 0x4027
+#define MASK_FSQ 0x707f
+#define MATCH_FMADD_S 0x43
+#define MASK_FMADD_S 0x600007f
+#define MATCH_FMSUB_S 0x47
+#define MASK_FMSUB_S 0x600007f
+#define MATCH_FNMSUB_S 0x4b
+#define MASK_FNMSUB_S 0x600007f
+#define MATCH_FNMADD_S 0x4f
+#define MASK_FNMADD_S 0x600007f
+#define MATCH_FMADD_D 0x2000043
+#define MASK_FMADD_D 0x600007f
+#define MATCH_FMSUB_D 0x2000047
+#define MASK_FMSUB_D 0x600007f
+#define MATCH_FNMSUB_D 0x200004b
+#define MASK_FNMSUB_D 0x600007f
+#define MATCH_FNMADD_D 0x200004f
+#define MASK_FNMADD_D 0x600007f
+#define MATCH_FMADD_Q 0x6000043
+#define MASK_FMADD_Q 0x600007f
+#define MATCH_FMSUB_Q 0x6000047
+#define MASK_FMSUB_Q 0x600007f
+#define MATCH_FNMSUB_Q 0x600004b
+#define MASK_FNMSUB_Q 0x600007f
+#define MATCH_FNMADD_Q 0x600004f
+#define MASK_FNMADD_Q 0x600007f
+#define MATCH_C_NOP 0x1
+#define MASK_C_NOP 0xffff
+#define MATCH_C_ADDI16SP 0x6101
+#define MASK_C_ADDI16SP 0xef83
+#define MATCH_C_JR 0x8002
+#define MASK_C_JR 0xf07f
+#define MATCH_C_JALR 0x9002
+#define MASK_C_JALR 0xf07f
+#define MATCH_C_EBREAK 0x9002
+#define MASK_C_EBREAK 0xffff
+#define MATCH_C_LD 0x6000
+#define MASK_C_LD 0xe003
+#define MATCH_C_SD 0xe000
+#define MASK_C_SD 0xe003
+#define MATCH_C_ADDIW 0x2001
+#define MASK_C_ADDIW 0xe003
+#define MATCH_C_LDSP 0x6002
+#define MASK_C_LDSP 0xe003
+#define MATCH_C_SDSP 0xe002
+#define MASK_C_SDSP 0xe003
+#define MATCH_C_ADDI4SPN 0x0
+#define MASK_C_ADDI4SPN 0xe003
+#define MATCH_C_FLD 0x2000
+#define MASK_C_FLD 0xe003
+#define MATCH_C_LW 0x4000
+#define MASK_C_LW 0xe003
+#define MATCH_C_FLW 0x6000
+#define MASK_C_FLW 0xe003
+#define MATCH_C_FSD 0xa000
+#define MASK_C_FSD 0xe003
+#define MATCH_C_SW 0xc000
+#define MASK_C_SW 0xe003
+#define MATCH_C_FSW 0xe000
+#define MASK_C_FSW 0xe003
+#define MATCH_C_ADDI 0x1
+#define MASK_C_ADDI 0xe003
+#define MATCH_C_JAL 0x2001
+#define MASK_C_JAL 0xe003
+#define MATCH_C_LI 0x4001
+#define MASK_C_LI 0xe003
+#define MATCH_C_LUI 0x6001
+#define MASK_C_LUI 0xe003
+#define MATCH_C_SRLI 0x8001
+#define MASK_C_SRLI 0xec03
+#define MATCH_C_SRAI 0x8401
+#define MASK_C_SRAI 0xec03
+#define MATCH_C_ANDI 0x8801
+#define MASK_C_ANDI 0xec03
+#define MATCH_C_SUB 0x8c01
+#define MASK_C_SUB 0xfc63
+#define MATCH_C_XOR 0x8c21
+#define MASK_C_XOR 0xfc63
+#define MATCH_C_OR 0x8c41
+#define MASK_C_OR 0xfc63
+#define MATCH_C_AND 0x8c61
+#define MASK_C_AND 0xfc63
+#define MATCH_C_SUBW 0x9c01
+#define MASK_C_SUBW 0xfc63
+#define MATCH_C_ADDW 0x9c21
+#define MASK_C_ADDW 0xfc63
+#define MATCH_C_J 0xa001
+#define MASK_C_J 0xe003
+#define MATCH_C_BEQZ 0xc001
+#define MASK_C_BEQZ 0xe003
+#define MATCH_C_BNEZ 0xe001
+#define MASK_C_BNEZ 0xe003
+#define MATCH_C_SLLI 0x2
+#define MASK_C_SLLI 0xe003
+#define MATCH_C_FLDSP 0x2002
+#define MASK_C_FLDSP 0xe003
+#define MATCH_C_LWSP 0x4002
+#define MASK_C_LWSP 0xe003
+#define MATCH_C_FLWSP 0x6002
+#define MASK_C_FLWSP 0xe003
+#define MATCH_C_MV 0x8002
+#define MASK_C_MV 0xf003
+#define MATCH_C_ADD 0x9002
+#define MASK_C_ADD 0xf003
+#define MATCH_C_FSDSP 0xa002
+#define MASK_C_FSDSP 0xe003
+#define MATCH_C_SWSP 0xc002
+#define MASK_C_SWSP 0xe003
+#define MATCH_C_FSWSP 0xe002
+#define MASK_C_FSWSP 0xe003
+#define MATCH_CUSTOM0 0xb
+#define MASK_CUSTOM0 0x707f
+#define MATCH_CUSTOM0_RS1 0x200b
+#define MASK_CUSTOM0_RS1 0x707f
+#define MATCH_CUSTOM0_RS1_RS2 0x300b
+#define MASK_CUSTOM0_RS1_RS2 0x707f
+#define MATCH_CUSTOM0_RD 0x400b
+#define MASK_CUSTOM0_RD 0x707f
+#define MATCH_CUSTOM0_RD_RS1 0x600b
+#define MASK_CUSTOM0_RD_RS1 0x707f
+#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b
+#define MASK_CUSTOM0_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM1 0x2b
+#define MASK_CUSTOM1 0x707f
+#define MATCH_CUSTOM1_RS1 0x202b
+#define MASK_CUSTOM1_RS1 0x707f
+#define MATCH_CUSTOM1_RS1_RS2 0x302b
+#define MASK_CUSTOM1_RS1_RS2 0x707f
+#define MATCH_CUSTOM1_RD 0x402b
+#define MASK_CUSTOM1_RD 0x707f
+#define MATCH_CUSTOM1_RD_RS1 0x602b
+#define MASK_CUSTOM1_RD_RS1 0x707f
+#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b
+#define MASK_CUSTOM1_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM2 0x5b
+#define MASK_CUSTOM2 0x707f
+#define MATCH_CUSTOM2_RS1 0x205b
+#define MASK_CUSTOM2_RS1 0x707f
+#define MATCH_CUSTOM2_RS1_RS2 0x305b
+#define MASK_CUSTOM2_RS1_RS2 0x707f
+#define MATCH_CUSTOM2_RD 0x405b
+#define MASK_CUSTOM2_RD 0x707f
+#define MATCH_CUSTOM2_RD_RS1 0x605b
+#define MASK_CUSTOM2_RD_RS1 0x707f
+#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b
+#define MASK_CUSTOM2_RD_RS1_RS2 0x707f
+#define MATCH_CUSTOM3 0x7b
+#define MASK_CUSTOM3 0x707f
+#define MATCH_CUSTOM3_RS1 0x207b
+#define MASK_CUSTOM3_RS1 0x707f
+#define MATCH_CUSTOM3_RS1_RS2 0x307b
+#define MASK_CUSTOM3_RS1_RS2 0x707f
+#define MATCH_CUSTOM3_RD 0x407b
+#define MASK_CUSTOM3_RD 0x707f
+#define MATCH_CUSTOM3_RD_RS1 0x607b
+#define MASK_CUSTOM3_RD_RS1 0x707f
+#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
+#define MASK_CUSTOM3_RD_RS1_RS2 0x707f
+#define CSR_FFLAGS 0x1
+#define CSR_FRM 0x2
+#define CSR_FCSR 0x3
+#define CSR_CYCLE 0xc00
+#define CSR_TIME 0xc01
+#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
+#define CSR_SSTATUS 0x100
+#define CSR_SIE 0x104
+#define CSR_STVEC 0x105
+#define CSR_SCOUNTEREN 0x106
+#define CSR_SSCRATCH 0x140
+#define CSR_SEPC 0x141
+#define CSR_SCAUSE 0x142
+#define CSR_STVAL 0x143
+#define CSR_SIP 0x144
+#define CSR_SATP 0x180
+#define CSR_MSTATUS 0x300
+#define CSR_MISA 0x301
+#define CSR_MEDELEG 0x302
+#define CSR_MIDELEG 0x303
+#define CSR_MIE 0x304
+#define CSR_MTVEC 0x305
+#define CSR_MCOUNTEREN 0x306
+#define CSR_MSCRATCH 0x340
+#define CSR_MEPC 0x341
+#define CSR_MCAUSE 0x342
+#define CSR_MTVAL 0x343
+#define CSR_MIP 0x344
+#define CSR_PMPCFG0 0x3a0
+#define CSR_PMPCFG1 0x3a1
+#define CSR_PMPCFG2 0x3a2
+#define CSR_PMPCFG3 0x3a3
+#define CSR_PMPADDR0 0x3b0
+#define CSR_PMPADDR1 0x3b1
+#define CSR_PMPADDR2 0x3b2
+#define CSR_PMPADDR3 0x3b3
+#define CSR_PMPADDR4 0x3b4
+#define CSR_PMPADDR5 0x3b5
+#define CSR_PMPADDR6 0x3b6
+#define CSR_PMPADDR7 0x3b7
+#define CSR_PMPADDR8 0x3b8
+#define CSR_PMPADDR9 0x3b9
+#define CSR_PMPADDR10 0x3ba
+#define CSR_PMPADDR11 0x3bb
+#define CSR_PMPADDR12 0x3bc
+#define CSR_PMPADDR13 0x3bd
+#define CSR_PMPADDR14 0x3be
+#define CSR_PMPADDR15 0x3bf
+#define CSR_TSELECT 0x7a0
+#define CSR_TDATA1 0x7a1
+#define CSR_TDATA2 0x7a2
+#define CSR_TDATA3 0x7a3
+#define CSR_DCSR 0x7b0
+#define CSR_DPC 0x7b1
+#define CSR_DSCRATCH 0x7b2
+#define CSR_DSCRATCH0 CSR_DSCRATCH
+#define CSR_DSCRATCH1 0x7b3
+#define CSR_MCYCLE 0xb00
+#define CSR_MINSTRET 0xb02
+#define CSR_MHPMCOUNTER3 0xb03
+#define CSR_MHPMCOUNTER4 0xb04
+#define CSR_MHPMCOUNTER5 0xb05
+#define CSR_MHPMCOUNTER6 0xb06
+#define CSR_MHPMCOUNTER7 0xb07
+#define CSR_MHPMCOUNTER8 0xb08
+#define CSR_MHPMCOUNTER9 0xb09
+#define CSR_MHPMCOUNTER10 0xb0a
+#define CSR_MHPMCOUNTER11 0xb0b
+#define CSR_MHPMCOUNTER12 0xb0c
+#define CSR_MHPMCOUNTER13 0xb0d
+#define CSR_MHPMCOUNTER14 0xb0e
+#define CSR_MHPMCOUNTER15 0xb0f
+#define CSR_MHPMCOUNTER16 0xb10
+#define CSR_MHPMCOUNTER17 0xb11
+#define CSR_MHPMCOUNTER18 0xb12
+#define CSR_MHPMCOUNTER19 0xb13
+#define CSR_MHPMCOUNTER20 0xb14
+#define CSR_MHPMCOUNTER21 0xb15
+#define CSR_MHPMCOUNTER22 0xb16
+#define CSR_MHPMCOUNTER23 0xb17
+#define CSR_MHPMCOUNTER24 0xb18
+#define CSR_MHPMCOUNTER25 0xb19
+#define CSR_MHPMCOUNTER26 0xb1a
+#define CSR_MHPMCOUNTER27 0xb1b
+#define CSR_MHPMCOUNTER28 0xb1c
+#define CSR_MHPMCOUNTER29 0xb1d
+#define CSR_MHPMCOUNTER30 0xb1e
+#define CSR_MHPMCOUNTER31 0xb1f
+#define CSR_MHPMEVENT3 0x323
+#define CSR_MHPMEVENT4 0x324
+#define CSR_MHPMEVENT5 0x325
+#define CSR_MHPMEVENT6 0x326
+#define CSR_MHPMEVENT7 0x327
+#define CSR_MHPMEVENT8 0x328
+#define CSR_MHPMEVENT9 0x329
+#define CSR_MHPMEVENT10 0x32a
+#define CSR_MHPMEVENT11 0x32b
+#define CSR_MHPMEVENT12 0x32c
+#define CSR_MHPMEVENT13 0x32d
+#define CSR_MHPMEVENT14 0x32e
+#define CSR_MHPMEVENT15 0x32f
+#define CSR_MHPMEVENT16 0x330
+#define CSR_MHPMEVENT17 0x331
+#define CSR_MHPMEVENT18 0x332
+#define CSR_MHPMEVENT19 0x333
+#define CSR_MHPMEVENT20 0x334
+#define CSR_MHPMEVENT21 0x335
+#define CSR_MHPMEVENT22 0x336
+#define CSR_MHPMEVENT23 0x337
+#define CSR_MHPMEVENT24 0x338
+#define CSR_MHPMEVENT25 0x339
+#define CSR_MHPMEVENT26 0x33a
+#define CSR_MHPMEVENT27 0x33b
+#define CSR_MHPMEVENT28 0x33c
+#define CSR_MHPMEVENT29 0x33d
+#define CSR_MHPMEVENT30 0x33e
+#define CSR_MHPMEVENT31 0x33f
+#define CSR_MVENDORID 0xf11
+#define CSR_MARCHID 0xf12
+#define CSR_MIMPID 0xf13
+#define CSR_MHARTID 0xf14
+#define CSR_CYCLEH 0xc80
+#define CSR_TIMEH 0xc81
+#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
+#define CSR_MCYCLEH 0xb80
+#define CSR_MINSTRETH 0xb82
+#define CSR_MHPMCOUNTER3H 0xb83
+#define CSR_MHPMCOUNTER4H 0xb84
+#define CSR_MHPMCOUNTER5H 0xb85
+#define CSR_MHPMCOUNTER6H 0xb86
+#define CSR_MHPMCOUNTER7H 0xb87
+#define CSR_MHPMCOUNTER8H 0xb88
+#define CSR_MHPMCOUNTER9H 0xb89
+#define CSR_MHPMCOUNTER10H 0xb8a
+#define CSR_MHPMCOUNTER11H 0xb8b
+#define CSR_MHPMCOUNTER12H 0xb8c
+#define CSR_MHPMCOUNTER13H 0xb8d
+#define CSR_MHPMCOUNTER14H 0xb8e
+#define CSR_MHPMCOUNTER15H 0xb8f
+#define CSR_MHPMCOUNTER16H 0xb90
+#define CSR_MHPMCOUNTER17H 0xb91
+#define CSR_MHPMCOUNTER18H 0xb92
+#define CSR_MHPMCOUNTER19H 0xb93
+#define CSR_MHPMCOUNTER20H 0xb94
+#define CSR_MHPMCOUNTER21H 0xb95
+#define CSR_MHPMCOUNTER22H 0xb96
+#define CSR_MHPMCOUNTER23H 0xb97
+#define CSR_MHPMCOUNTER24H 0xb98
+#define CSR_MHPMCOUNTER25H 0xb99
+#define CSR_MHPMCOUNTER26H 0xb9a
+#define CSR_MHPMCOUNTER27H 0xb9b
+#define CSR_MHPMCOUNTER28H 0xb9c
+#define CSR_MHPMCOUNTER29H 0xb9d
+#define CSR_MHPMCOUNTER30H 0xb9e
+#define CSR_MHPMCOUNTER31H 0xb9f
+#define CAUSE_MISALIGNED_FETCH 0x0
+#define CAUSE_FETCH_ACCESS 0x1
+#define CAUSE_ILLEGAL_INSTRUCTION 0x2
+#define CAUSE_BREAKPOINT 0x3
+#define CAUSE_MISALIGNED_LOAD 0x4
+#define CAUSE_LOAD_ACCESS 0x5
+#define CAUSE_MISALIGNED_STORE 0x6
+#define CAUSE_STORE_ACCESS 0x7
+#define CAUSE_USER_ECALL 0x8
+#define CAUSE_SUPERVISOR_ECALL 0x9
+#define CAUSE_HYPERVISOR_ECALL 0xa
+#define CAUSE_MACHINE_ECALL 0xb
+#define CAUSE_FETCH_PAGE_FAULT 0xc
+#define CAUSE_LOAD_PAGE_FAULT 0xd
+#define CAUSE_STORE_PAGE_FAULT 0xf
+#endif
+#ifdef DECLARE_INSN
+DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
+DECLARE_INSN(bne, MATCH_BNE, MASK_BNE)
+DECLARE_INSN(blt, MATCH_BLT, MASK_BLT)
+DECLARE_INSN(bge, MATCH_BGE, MASK_BGE)
+DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU)
+DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU)
+DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR)
+DECLARE_INSN(jal, MATCH_JAL, MASK_JAL)
+DECLARE_INSN(lui, MATCH_LUI, MASK_LUI)
+DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC)
+DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI)
+DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI)
+DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI)
+DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU)
+DECLARE_INSN(xori, MATCH_XORI, MASK_XORI)
+DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI)
+DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI)
+DECLARE_INSN(ori, MATCH_ORI, MASK_ORI)
+DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI)
+DECLARE_INSN(add, MATCH_ADD, MASK_ADD)
+DECLARE_INSN(sub, MATCH_SUB, MASK_SUB)
+DECLARE_INSN(sll, MATCH_SLL, MASK_SLL)
+DECLARE_INSN(slt, MATCH_SLT, MASK_SLT)
+DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU)
+DECLARE_INSN(xor, MATCH_XOR, MASK_XOR)
+DECLARE_INSN(srl, MATCH_SRL, MASK_SRL)
+DECLARE_INSN(sra, MATCH_SRA, MASK_SRA)
+DECLARE_INSN(or, MATCH_OR, MASK_OR)
+DECLARE_INSN(and, MATCH_AND, MASK_AND)
+DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW)
+DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW)
+DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW)
+DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW)
+DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW)
+DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW)
+DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW)
+DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW)
+DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW)
+DECLARE_INSN(lb, MATCH_LB, MASK_LB)
+DECLARE_INSN(lh, MATCH_LH, MASK_LH)
+DECLARE_INSN(lw, MATCH_LW, MASK_LW)
+DECLARE_INSN(ld, MATCH_LD, MASK_LD)
+DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU)
+DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU)
+DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU)
+DECLARE_INSN(sb, MATCH_SB, MASK_SB)
+DECLARE_INSN(sh, MATCH_SH, MASK_SH)
+DECLARE_INSN(sw, MATCH_SW, MASK_SW)
+DECLARE_INSN(sd, MATCH_SD, MASK_SD)
+DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE)
+DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I)
+DECLARE_INSN(mul, MATCH_MUL, MASK_MUL)
+DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH)
+DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU)
+DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU)
+DECLARE_INSN(div, MATCH_DIV, MASK_DIV)
+DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU)
+DECLARE_INSN(rem, MATCH_REM, MASK_REM)
+DECLARE_INSN(remu, MATCH_REMU, MASK_REMU)
+DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW)
+DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW)
+DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW)
+DECLARE_INSN(remw, MATCH_REMW, MASK_REMW)
+DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW)
+DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W)
+DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W)
+DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W)
+DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W)
+DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W)
+DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W)
+DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W)
+DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W)
+DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W)
+DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W)
+DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W)
+DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D)
+DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D)
+DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D)
+DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D)
+DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D)
+DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D)
+DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D)
+DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D)
+DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D)
+DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D)
+DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D)
+DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
+DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
+DECLARE_INSN(uret, MATCH_URET, MASK_URET)
+DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
+DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
+DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
+DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
+DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
+DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
+DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
+DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC)
+DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI)
+DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI)
+DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI)
+DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S)
+DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S)
+DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S)
+DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S)
+DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S)
+DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S)
+DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S)
+DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S)
+DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S)
+DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S)
+DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D)
+DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D)
+DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D)
+DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D)
+DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D)
+DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D)
+DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D)
+DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D)
+DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
+DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
+DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
+DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
+DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
+DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
+DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
+DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
+DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
+DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
+DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
+DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
+DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
+DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
+DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
+DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
+DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
+DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
+DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
+DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
+DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
+DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
+DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
+DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
+DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
+DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
+DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
+DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
+DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
+DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
+DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
+DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
+DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
+DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
+DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
+DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
+DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
+DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
+DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
+DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
+DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
+DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
+DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
+DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
+DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
+DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
+DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
+DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
+DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
+DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
+DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
+DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
+DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
+DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
+DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
+DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
+DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
+DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
+DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
+DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
+DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
+DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
+DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
+DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
+DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
+DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
+DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
+DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
+DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
+DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S)
+DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
+DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
+DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
+DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
+DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
+DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
+DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
+DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
+DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
+DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
+DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
+DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR)
+DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK)
+DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD)
+DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD)
+DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW)
+DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP)
+DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
+DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
+DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD)
+DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW)
+DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW)
+DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD)
+DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW)
+DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW)
+DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI)
+DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL)
+DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI)
+DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI)
+DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI)
+DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI)
+DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI)
+DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB)
+DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR)
+DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR)
+DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND)
+DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW)
+DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW)
+DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J)
+DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ)
+DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ)
+DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI)
+DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP)
+DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
+DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP)
+DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV)
+DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD)
+DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP)
+DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP)
+DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP)
+DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0)
+DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1)
+DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2)
+DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD)
+DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1)
+DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, MASK_CUSTOM0_RD_RS1_RS2)
+DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1)
+DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1)
+DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2)
+DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD)
+DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1)
+DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, MASK_CUSTOM1_RD_RS1_RS2)
+DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2)
+DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1)
+DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2)
+DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD)
+DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1)
+DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, MASK_CUSTOM2_RD_RS1_RS2)
+DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3)
+DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1)
+DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2)
+DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD)
+DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
+DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
+#endif
+#ifdef DECLARE_CSR
+DECLARE_CSR(fflags, CSR_FFLAGS)
+DECLARE_CSR(frm, CSR_FRM)
+DECLARE_CSR(fcsr, CSR_FCSR)
+DECLARE_CSR(cycle, CSR_CYCLE)
+DECLARE_CSR(time, CSR_TIME)
+DECLARE_CSR(instret, CSR_INSTRET)
+DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3)
+DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4)
+DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5)
+DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6)
+DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7)
+DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8)
+DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9)
+DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10)
+DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11)
+DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12)
+DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13)
+DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14)
+DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15)
+DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16)
+DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17)
+DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18)
+DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19)
+DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20)
+DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21)
+DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22)
+DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23)
+DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24)
+DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25)
+DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26)
+DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27)
+DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28)
+DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29)
+DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30)
+DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
+DECLARE_CSR(sstatus, CSR_SSTATUS)
+DECLARE_CSR(sie, CSR_SIE)
+DECLARE_CSR(stvec, CSR_STVEC)
+DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
+DECLARE_CSR(sscratch, CSR_SSCRATCH)
+DECLARE_CSR(sepc, CSR_SEPC)
+DECLARE_CSR(scause, CSR_SCAUSE)
+DECLARE_CSR(stval, CSR_STVAL)
+DECLARE_CSR(sip, CSR_SIP)
+DECLARE_CSR(satp, CSR_SATP)
+DECLARE_CSR(mstatus, CSR_MSTATUS)
+DECLARE_CSR(misa, CSR_MISA)
+DECLARE_CSR(medeleg, CSR_MEDELEG)
+DECLARE_CSR(mideleg, CSR_MIDELEG)
+DECLARE_CSR(mie, CSR_MIE)
+DECLARE_CSR(mtvec, CSR_MTVEC)
+DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
+DECLARE_CSR(mscratch, CSR_MSCRATCH)
+DECLARE_CSR(mepc, CSR_MEPC)
+DECLARE_CSR(mcause, CSR_MCAUSE)
+DECLARE_CSR(mtval, CSR_MTVAL)
+DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
+DECLARE_CSR(tselect, CSR_TSELECT)
+DECLARE_CSR(tdata1, CSR_TDATA1)
+DECLARE_CSR(tdata2, CSR_TDATA2)
+DECLARE_CSR(tdata3, CSR_TDATA3)
+DECLARE_CSR(dcsr, CSR_DCSR)
+DECLARE_CSR(dpc, CSR_DPC)
+DECLARE_CSR(dscratch, CSR_DSCRATCH)
+DECLARE_CSR(dscratch0, CSR_DSCRATCH0)
+DECLARE_CSR(dscratch1, CSR_DSCRATCH1)
+DECLARE_CSR(mcycle, CSR_MCYCLE)
+DECLARE_CSR(minstret, CSR_MINSTRET)
+DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3)
+DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4)
+DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5)
+DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6)
+DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7)
+DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8)
+DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9)
+DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10)
+DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11)
+DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12)
+DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13)
+DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14)
+DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15)
+DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16)
+DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17)
+DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18)
+DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19)
+DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20)
+DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21)
+DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22)
+DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23)
+DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24)
+DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25)
+DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26)
+DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27)
+DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
+DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
+DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
+DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
+DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
+DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
+DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
+DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6)
+DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7)
+DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8)
+DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9)
+DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10)
+DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11)
+DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12)
+DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13)
+DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14)
+DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15)
+DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16)
+DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17)
+DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18)
+DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19)
+DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20)
+DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21)
+DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22)
+DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23)
+DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24)
+DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25)
+DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26)
+DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27)
+DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28)
+DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29)
+DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30)
+DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31)
+DECLARE_CSR(mvendorid, CSR_MVENDORID)
+DECLARE_CSR(marchid, CSR_MARCHID)
+DECLARE_CSR(mimpid, CSR_MIMPID)
+DECLARE_CSR(mhartid, CSR_MHARTID)
+DECLARE_CSR(cycleh, CSR_CYCLEH)
+DECLARE_CSR(timeh, CSR_TIMEH)
+DECLARE_CSR(instreth, CSR_INSTRETH)
+DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H)
+DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H)
+DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H)
+DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H)
+DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H)
+DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H)
+DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H)
+DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H)
+DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H)
+DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H)
+DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H)
+DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H)
+DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H)
+DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H)
+DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H)
+DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H)
+DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H)
+DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H)
+DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H)
+DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H)
+DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H)
+DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H)
+DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H)
+DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H)
+DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H)
+DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H)
+DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H)
+DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H)
+DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H)
+DECLARE_CSR(mcycleh, CSR_MCYCLEH)
+DECLARE_CSR(minstreth, CSR_MINSTRETH)
+DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H)
+DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H)
+DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H)
+DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H)
+DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H)
+DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H)
+DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H)
+DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H)
+DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H)
+DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H)
+DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H)
+DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H)
+DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H)
+DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H)
+DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H)
+DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H)
+DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H)
+DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H)
+DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H)
+DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H)
+DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H)
+DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H)
+DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H)
+DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H)
+DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H)
+DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
+DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
+DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
+DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
+#endif
+#ifdef DECLARE_CAUSE
+DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
+DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
+DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
+DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
+DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
+DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
+DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
+DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
+DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
+DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
+DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
+DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
+DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
+DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
+DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
+#endif
\ No newline at end of file
diff --git a/verif/tests/custom/zcmt/jvt_csr.S b/verif/tests/custom/zcmt/jvt_csr.S
index 4ccd3d9fd2..f1d770902d 100644
--- a/verif/tests/custom/zcmt/jvt_csr.S
+++ b/verif/tests/custom/zcmt/jvt_csr.S
@@ -1,5 +1,8 @@
-.globl _start
-_start:
+#include "riscv_test.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
la t0, trap_handler
csrw mtvec, t0
la t0, __jvt_base$
@@ -8,44 +11,44 @@ _start:
fence.i
csrr x7, jvt
- j exit
-
-exit:
- j write_tohost
-
-write_tohost:
- li x1, 1
- la t0, tohost
- sw x1, 0(t0)
- j write_tohost
+ j success
-
-# Jump Vector Table (JVT) Section
-# Create a separate section for the JVT
-.section .riscv.jvt, "ax"
-.align 6 # Align the JVT on a 64-byte boundary (6 = 2^6 = 64)
-__jvt_base$:
- .word 0x80000054
- .word 0x80000800
- .word 0x80000802
- .word 0x80000804
-
-# Target Addresses (Where cm.jt will jump)
-target0:
- j write_tohost
-target1:
- addi x6,x0, 7
- j write_tohost
-
-target2:
- addi x2,x20, 5
- j write_tohost
-
-
trap_handler:
- j exit
+ lui t0, %hi(failure) # Load upper 20 bits of target address into t0
+ addi t0, t0, %lo(failure) # Add the lower 12 bits to t0
+ jalr x0, 0(t0)
+
+// jump to this label to signal that the test failed
+failure:
+ li x1, 1
+ slli x1, x1, 1
+ addi x1, x1, 1
+ sw x1, tohost, t5
+ self_loop_2: j self_loop_2
+
+// jump to this label to signal that the test passed
+success:
+ li x1, 0
+ slli x1, x1, 1
+ addi x1, x1, 1
+ sw x1, tohost, t5
+ self_loop: j self_loop
+
+RVTEST_CODE_END
+
+.data
+
+RVTEST_DATA_BEGIN
+
+// Jump Vector Table (JVT) Section
+.section .riscv.jvt, "ax"
+.align 6
+__jvt_base$:
+ .word 0x80000054
+ .word 0x80000800
+ .word 0x80000802
+ .word 0x80000804
-.align 6; .global tohost; tohost: .dword 0;
-.align 6; .global fromhost; fromhost: .dword 0;
+RVTEST_DATA_END
\ No newline at end of file
diff --git a/verif/tests/custom/zcmt/link.ld b/verif/tests/custom/zcmt/link.ld
new file mode 100644
index 0000000000..ae985b0a8d
--- /dev/null
+++ b/verif/tests/custom/zcmt/link.ld
@@ -0,0 +1,81 @@
+/*======================================================================*/
+/* Proxy kernel linker script */
+/*======================================================================*/
+/* This is the linker script used when building the proxy kernel. */
+
+/*----------------------------------------------------------------------*/
+/* Setup */
+/*----------------------------------------------------------------------*/
+
+/* The OUTPUT_ARCH command specifies the machine architecture where the
+ argument is one of the names used in the BFD library. More
+ specifically one of the entires in bfd/cpu-mips.c */
+
+OUTPUT_ARCH( "riscv" )
+ENTRY(_start)
+
+/*----------------------------------------------------------------------*/
+/* Sections */
+/*----------------------------------------------------------------------*/
+
+SECTIONS
+{
+
+ /* text: test code section */
+ . = 0x80000000;
+ _start_text = .;
+ .text.init : { *(.text.init) }
+
+ . = ALIGN(0x1000);
+ .tohost : { *(.tohost) }
+
+ . = ALIGN(0x1000);
+ .uvmif : { *(.uvmif) }
+
+ . = ALIGN(0x1000);
+ .text : { *(.text) }
+ . = ALIGN(0x1000);
+ .text.startup : { *(.text.startup) }
+ . = ALIGN(0x1000);
+ _end_text = .;
+ . = ALIGN(0x1000);
+ .rodata : { *(.rodata*)}
+ . = ALIGN(0x8);
+ . = ALIGN(0x1000);
+ .page_table : { *(.page_table) }
+ .user_stack : { *(.user_stack) }
+ .kernel_data : { *(.kernel_data) }
+ .kernel_stack : { *(.kernel_stack) }
+
+ /* data segment */
+ .data : { *(.data) }
+
+ .sdata : {
+ __global_pointer$ = . + 0x800;
+ *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata*)
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ }
+
+ /* bss segment */
+ .sbss : {
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ }
+ .bss : { *(.bss) }
+
+ /* thread-local data segment */
+ .tdata :
+ {
+ _tdata_begin = .;
+ *(.tdata)
+ _tdata_end = .;
+ }
+ .tbss :
+ {
+ *(.tbss)
+ _tbss_end = .;
+ }
+
+ /* End of uninitalized data segement */
+ _end = .;
+}
\ No newline at end of file
diff --git a/verif/tests/custom/zcmt/riscv_test.h b/verif/tests/custom/zcmt/riscv_test.h
new file mode 100644
index 0000000000..384b06138b
--- /dev/null
+++ b/verif/tests/custom/zcmt/riscv_test.h
@@ -0,0 +1,272 @@
+// See LICENSE for license details.
+
+#ifndef _ENV_PHYSICAL_SINGLE_CORE_H
+#define _ENV_PHYSICAL_SINGLE_CORE_H
+
+#include "encoding.h"
+
+//-----------------------------------------------------------------------
+// Begin Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_RV64U \
+ .macro init; \
+ .endm
+
+#define RVTEST_RV64UF \
+ .macro init; \
+ RVTEST_FP_ENABLE; \
+ .endm
+
+#define RVTEST_RV64UV \
+ .macro init; \
+ RVTEST_VECTOR_ENABLE; \
+ .endm
+
+#define RVTEST_RV32U \
+ .macro init; \
+ .endm
+
+#define RVTEST_RV32UF \
+ .macro init; \
+ RVTEST_FP_ENABLE; \
+ .endm
+
+#define RVTEST_RV32UV \
+ .macro init; \
+ RVTEST_VECTOR_ENABLE; \
+ .endm
+
+#define RVTEST_RV64M \
+ .macro init; \
+ RVTEST_ENABLE_MACHINE; \
+ .endm
+
+#define RVTEST_RV64S \
+ .macro init; \
+ RVTEST_ENABLE_SUPERVISOR; \
+ .endm
+
+#define RVTEST_RV32M \
+ .macro init; \
+ RVTEST_ENABLE_MACHINE; \
+ .endm
+
+#define RVTEST_RV32S \
+ .macro init; \
+ RVTEST_ENABLE_SUPERVISOR; \
+ .endm
+
+#if __riscv_xlen == 64
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1:
+#else
+# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1:
+#endif
+
+#define INIT_XREG \
+ li x1, 0; \
+ li x2, 0; \
+ li x3, 0; \
+ li x4, 0; \
+ li x5, 0; \
+ li x6, 0; \
+ li x7, 0; \
+ li x8, 0; \
+ li x9, 0; \
+ li x10, 0; \
+ li x11, 0; \
+ li x12, 0; \
+ li x13, 0; \
+ li x14, 0; \
+ li x15, 0; \
+ li x16, 0; \
+ li x17, 0; \
+ li x18, 0; \
+ li x19, 0; \
+ li x20, 0; \
+ li x21, 0; \
+ li x22, 0; \
+ li x23, 0; \
+ li x24, 0; \
+ li x25, 0; \
+ li x26, 0; \
+ li x27, 0; \
+ li x28, 0; \
+ li x29, 0; \
+ li x30, 0; \
+ li x31, 0;
+
+#define INIT_PMP \
+ la t0, 1f; \
+ csrw mtvec, t0; \
+ /* Set up a PMP to permit all accesses */ \
+ li t0, (1 << (31 + (__riscv_xlen / 64) * (53 - 31))) - 1; \
+ csrw pmpaddr0, t0; \
+ li t0, PMP_NAPOT | PMP_R | PMP_W | PMP_X; \
+ csrw pmpcfg0, t0; \
+ .align 2; \
+1:
+
+#define INIT_SATP \
+ la t0, 1f; \
+ csrw mtvec, t0; \
+ csrwi satp, 0; \
+ .align 2; \
+1:
+
+#define DELEGATE_NO_TRAPS \
+ la t0, 1f; \
+ csrw mtvec, t0; \
+ csrwi medeleg, 0; \
+ csrwi mideleg, 0; \
+ csrwi mie, 0; \
+ .align 2; \
+1:
+
+#define RVTEST_ENABLE_SUPERVISOR \
+ li a0, MSTATUS_MPP & (MSTATUS_MPP >> 1); \
+ csrs mstatus, a0; \
+ li a0, SIP_SSIP | SIP_STIP; \
+ csrs mideleg, a0; \
+
+#define RVTEST_ENABLE_MACHINE \
+ li a0, MSTATUS_MPP; \
+ csrs mstatus, a0; \
+
+#define RVTEST_FP_ENABLE \
+ li a0, MSTATUS_FS & (MSTATUS_FS >> 1); \
+ csrs mstatus, a0; \
+ csrwi fcsr, 0
+
+#define RVTEST_VECTOR_ENABLE \
+ li a0, (MSTATUS_VS & (MSTATUS_VS >> 1)) | \
+ (MSTATUS_FS & (MSTATUS_FS >> 1)); \
+ csrs mstatus, a0; \
+ csrwi fcsr, 0; \
+ csrwi vcsr, 0;
+
+#define RISCV_MULTICORE_DISABLE \
+ csrr a0, mhartid; \
+ 1: bnez a0, 1b
+
+#define EXTRA_TVEC_USER
+#define EXTRA_TVEC_MACHINE
+#define EXTRA_INIT
+#define EXTRA_INIT_TIMER
+
+#define INTERRUPT_HANDLER j other_exception /* No interrupts should occur */
+
+#define RVTEST_CODE_BEGIN \
+ .section .text.init; \
+ .align 6; \
+ .weak stvec_handler; \
+ .weak mtvec_handler; \
+ .globl _start; \
+_start: \
+ /* reset vector */ \
+ j reset_vector; \
+ .align 2; \
+trap_vector: \
+ /* test whether the test came from pass/fail */ \
+ csrr t5, mcause; \
+ li t6, CAUSE_USER_ECALL; \
+ beq t5, t6, write_tohost; \
+ li t6, CAUSE_SUPERVISOR_ECALL; \
+ beq t5, t6, write_tohost; \
+ li t6, CAUSE_MACHINE_ECALL; \
+ beq t5, t6, write_tohost; \
+ /* if an mtvec_handler is defined, jump to it */ \
+ la t5, mtvec_handler; \
+ beqz t5, 1f; \
+ jr t5; \
+ /* was it an interrupt or an exception? */ \
+ 1: csrr t5, mcause; \
+ bgez t5, handle_exception; \
+ INTERRUPT_HANDLER; \
+handle_exception: \
+ /* we don't know how to handle whatever the exception was */ \
+ other_exception: \
+ /* some unhandlable exception occurred */ \
+ 1: ori TESTNUM, TESTNUM, 1337; \
+ write_tohost: \
+ sw TESTNUM, tohost, t5; \
+ j write_tohost; \
+reset_vector: \
+ INIT_XREG; \
+ RISCV_MULTICORE_DISABLE; \
+ INIT_SATP; \
+ INIT_PMP; \
+ DELEGATE_NO_TRAPS; \
+ li TESTNUM, 0; \
+ la t0, trap_vector; \
+ csrw mtvec, t0; \
+ CHECK_XLEN; \
+ /* if an stvec_handler is defined, delegate exceptions to it */ \
+ la t0, stvec_handler; \
+ beqz t0, 1f; \
+ csrw stvec, t0; \
+ li t0, (1 << CAUSE_LOAD_PAGE_FAULT) | \
+ (1 << CAUSE_STORE_PAGE_FAULT) | \
+ (1 << CAUSE_FETCH_PAGE_FAULT) | \
+ (1 << CAUSE_MISALIGNED_FETCH) | \
+ (1 << CAUSE_USER_ECALL) | \
+ (1 << CAUSE_BREAKPOINT); \
+ csrw medeleg, t0; \
+1: csrwi mstatus, 0; \
+ init; \
+ EXTRA_INIT; \
+ EXTRA_INIT_TIMER; \
+ la t0, 1f; \
+ csrw mepc, t0; \
+ csrr a0, mhartid; \
+ mret; \
+1:
+
+//-----------------------------------------------------------------------
+// End Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_CODE_END \
+ unimp
+
+//-----------------------------------------------------------------------
+// Pass/Fail Macro
+//-----------------------------------------------------------------------
+
+#define RVTEST_PASS \
+ fence; \
+ li TESTNUM, 1; \
+ li a7, 93; \
+ li a0, 0; \
+ ecall
+
+#define TESTNUM gp
+#define RVTEST_FAIL \
+ fence; \
+1: beqz TESTNUM, 1b; \
+ sll TESTNUM, TESTNUM, 1; \
+ or TESTNUM, TESTNUM, 1; \
+ li a7, 93; \
+ addi a0, TESTNUM, 0; \
+ ecall
+
+//-----------------------------------------------------------------------
+// Data Section Macro
+//-----------------------------------------------------------------------
+
+#define EXTRA_DATA
+
+#define RVTEST_DATA_BEGIN \
+ EXTRA_DATA \
+ .pushsection .tohost,"aw",@progbits; \
+ .align 6; .global tohost; tohost: .dword 0; \
+ .align 6; .global fromhost; fromhost: .dword 0; \
+ .popsection; \
+ .pushsection .uvmif,"aw",@progbits; \
+ .align 6; .global int_ack; int_ack: .dword 0; \
+ .popsection; \
+ .align 4; .global begin_signature; begin_signature:
+
+#define RVTEST_DATA_END .align 4; .global end_signature; end_signature:
+
+#endif
\ No newline at end of file
diff --git a/verif/tests/custom/zcmt/syscalls.c b/verif/tests/custom/zcmt/syscalls.c
new file mode 100644
index 0000000000..daa53cfcf3
--- /dev/null
+++ b/verif/tests/custom/zcmt/syscalls.c
@@ -0,0 +1,521 @@
+// See LICENSE for license details.
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "util.h"
+
+#define SYS_write 64
+
+#undef strcmp
+
+extern volatile uint64_t tohost;
+extern volatile uint64_t fromhost;
+
+// tohost is 64 bits wide, irrespective of XLEN. The structure expected in Spike is:
+// - tohost[63:56] == device (syscall: 0)
+// - tohost[55:48] == command (syscall: 0)
+// - tohost[47:0] == payload (syscall: address of magic_mem)
+//
+// magic_mem for a syscall contains the following elements (XLEN bits each)
+// - syscall index (93 dec for syscall_exit, cf. Spike values in
+// riscv-isa-sim/fesvr/syscall.cc:140 and ff.)
+// - syscall args in the declaration order of the given syscall
+
+static uintptr_t syscall(uintptr_t which, uintptr_t arg0, uintptr_t arg1, uintptr_t arg2)
+{
+ // Arguments in magic_mem have XLEN bits each.
+ volatile uintptr_t magic_mem[8] __attribute__((aligned(64)));
+ magic_mem[0] = which;
+ magic_mem[1] = arg0;
+ magic_mem[2] = arg1;
+ magic_mem[3] = arg2;
+#ifdef __riscv_atomic // __sync_synchronize requires A extension
+ __sync_synchronize();
+#endif
+
+ // A WRITE_MEM transaction writing non-zero value to TOHOST triggers
+ // the environment (Spike or RTL harness).
+ // - here tohost is guaranteed non-NULL because magic_mem is a valid RISC-V
+ // pointer.
+ // - the environment acknowledges the env request by writing 0 into tohost.
+ // - the completion of the request is signalled by the environment through
+ // a write of a non-zero value into fromhost.
+ tohost = (((uint64_t) ((unsigned long int) magic_mem)) << 16) >> 16; // clear the DEV and CMD bytes, clip payload.
+ while (fromhost == 0)
+ ;
+ fromhost = 0;
+
+#ifdef __riscv_atomic // __sync_synchronize requires A extension
+ __sync_synchronize();
+#endif
+ return magic_mem[0];
+}
+
+#define NUM_COUNTERS 2
+static uintptr_t counters[NUM_COUNTERS];
+static char* counter_names[NUM_COUNTERS];
+
+void setStats(int enable)
+{
+ int i = 0;
+#define READ_CTR(name) do { \
+ while (i >= NUM_COUNTERS) ; \
+ uintptr_t csr = read_csr(name); \
+ if (!enable) { csr -= counters[i]; counter_names[i] = #name; } \
+ counters[i++] = csr; \
+ } while (0)
+
+ READ_CTR(mcycle);
+ READ_CTR(minstret);
+
+#undef READ_CTR
+}
+
+uintptr_t getStats(int counterid)
+{
+ return counters[counterid];
+}
+
+void __attribute__((noreturn)) tohost_exit(uintptr_t code)
+{
+ // Simply write PASS/FAIL result into 'tohost'.
+ // Left shift 'code' by 1 and set bit 0 to 1, but leave the 16 uppermost bits clear
+ // so that the syscall is properly recognized even if 'code' value is very large.
+ tohost = ((((uint64_t) code) << 17) >> 16) | 1;
+
+ // Do not care about the value returned by host.
+ // Leave 1 cycle of slack (one NOP instruction) to help debugging
+ // the termination mechanism if needed.
+ __asm__("nop\n\t");
+
+ // Go into an endless loop if the write into 'tohost' did not terminate the simulation.
+ while (1);
+}
+
+uintptr_t __attribute__((weak)) handle_trap(uintptr_t cause, uintptr_t epc, uintptr_t regs[32])
+{
+ tohost_exit(1337);
+}
+
+void exit(int code)
+{
+ tohost_exit(code);
+}
+
+void abort()
+{
+ exit(128 + SIGABRT);
+}
+
+void printstr(const char* s)
+{
+#if !NOPRINT
+ syscall(SYS_write, 1, (uintptr_t)s, strlen(s));
+#endif
+}
+
+void __attribute__((weak)) thread_entry(int cid, int nc)
+{
+ // multi-threaded programs override this function.
+ // for the case of single-threaded programs, only let core 0 proceed.
+ while (cid != 0);
+}
+
+int __attribute__((weak)) main(int argc, char** argv)
+{
+ // single-threaded programs override this function.
+ printstr("Implement main(), foo!\n");
+ return -1;
+}
+
+static void init_tls()
+{
+ register void* thread_pointer asm("tp");
+ extern char _tdata_begin, _tdata_end, _tbss_end;
+ size_t tdata_size = &_tdata_end - &_tdata_begin;
+ memcpy(thread_pointer, &_tdata_begin, tdata_size);
+ size_t tbss_size = &_tbss_end - &_tdata_end;
+ memset(thread_pointer + tdata_size, 0, tbss_size);
+}
+
+void _init(int cid, int nc)
+{
+ init_tls();
+ thread_entry(cid, nc);
+
+ // only single-threaded programs should ever get here.
+ int ret = main(0, 0);
+
+ char buf[NUM_COUNTERS * 32] __attribute__((aligned(64)));
+ char* pbuf = buf;
+ for (int i = 0; i < NUM_COUNTERS; i++)
+ if (counters[i])
+ pbuf += sprintf(pbuf, "%s = %d\n", counter_names[i], counters[i]);
+ if (pbuf != buf)
+ printstr(buf);
+
+ exit(ret);
+}
+
+int puts(const char *s)
+{
+ const char *p = s;
+
+ while (*p)
+ putchar(*p++);
+
+ putchar('\n');
+ return 0;
+}
+
+#undef putchar
+int putchar(int ch)
+{
+#if !NOPRINT
+ static __thread char buf[64] __attribute__((aligned(64)));
+ static __thread int buflen = 0;
+
+ buf[buflen++] = ch;
+
+ if (ch == '\n' || buflen == sizeof(buf))
+ {
+ syscall(SYS_write, 1, (uintptr_t)buf, buflen);
+ buflen = 0;
+ }
+#endif
+
+ return 0;
+}
+
+void printhex(uint64_t x)
+{
+ char str[17];
+ int i;
+ for (i = 0; i < 16; i++)
+ {
+ str[15-i] = (x & 0xF) + ((x & 0xF) < 10 ? '0' : 'a'-10);
+ x >>= 4;
+ }
+ str[16] = 0;
+
+ printstr(str);
+}
+
+static inline void printnum(void (*putch)(int, void**), void **putdat,
+ unsigned long long num, unsigned base, int width, int padc)
+{
+ unsigned digs[sizeof(num)*CHAR_BIT];
+ int pos = 0;
+
+ while (1)
+ {
+ digs[pos++] = num % base;
+ if (num < base)
+ break;
+ num /= base;
+ }
+
+ while (width-- > pos)
+ putch(padc, putdat);
+
+ while (pos-- > 0)
+ putch(digs[pos] + (digs[pos] >= 10 ? 'a' - 10 : '0'), putdat);
+}
+
+static unsigned long long getuint(va_list *ap, int lflag)
+{
+ if (lflag >= 2)
+ return va_arg(*ap, unsigned long long);
+ else if (lflag)
+ return va_arg(*ap, unsigned long);
+ else
+ return va_arg(*ap, unsigned int);
+}
+
+static long long getint(va_list *ap, int lflag)
+{
+ if (lflag >= 2)
+ return va_arg(*ap, long long);
+ else if (lflag)
+ return va_arg(*ap, long);
+ else
+ return va_arg(*ap, int);
+}
+
+static void vprintfmt(void (*putch)(int, void**), void **putdat, const char *fmt, va_list ap)
+{
+ register const char* p;
+ const char* last_fmt;
+ register int ch, err;
+ unsigned long long num;
+ int base, lflag, width, precision, altflag;
+ char padc;
+
+ while (1) {
+ while ((ch = *(unsigned char *) fmt) != '%') {
+ if (ch == '\0')
+ return;
+ fmt++;
+ putch(ch, putdat);
+ }
+ fmt++;
+
+ // Process a %-escape sequence
+ last_fmt = fmt;
+ padc = ' ';
+ width = -1;
+ precision = -1;
+ lflag = 0;
+ altflag = 0;
+ reswitch:
+ switch (ch = *(unsigned char *) fmt++) {
+
+ // flag to pad on the right
+ case '-':
+ padc = '-';
+ goto reswitch;
+
+ // flag to pad with 0's instead of spaces
+ case '0':
+ padc = '0';
+ goto reswitch;
+
+ // width field
+ case '1':
+ case '2':
+ case '3':
+ case '4':
+ case '5':
+ case '6':
+ case '7':
+ case '8':
+ case '9':
+ for (precision = 0; ; ++fmt) {
+ precision = precision * 10 + ch - '0';
+ ch = *fmt;
+ if (ch < '0' || ch > '9')
+ break;
+ }
+ goto process_precision;
+
+ case '*':
+ precision = va_arg(ap, int);
+ goto process_precision;
+
+ case '.':
+ if (width < 0)
+ width = 0;
+ goto reswitch;
+
+ case '#':
+ altflag = 1;
+ goto reswitch;
+
+ process_precision:
+ if (width < 0)
+ width = precision, precision = -1;
+ goto reswitch;
+
+ // long flag (doubled for long long)
+ case 'l':
+ lflag++;
+ goto reswitch;
+
+ // character
+ case 'c':
+ putch(va_arg(ap, int), putdat);
+ break;
+
+ // string
+ case 's':
+ if ((p = va_arg(ap, char *)) == NULL)
+ p = "(null)";
+ if (width > 0 && padc != '-')
+ for (width -= strnlen(p, precision); width > 0; width--)
+ putch(padc, putdat);
+ for (; (ch = *p) != '\0' && (precision < 0 || --precision >= 0); width--) {
+ putch(ch, putdat);
+ p++;
+ }
+ for (; width > 0; width--)
+ putch(' ', putdat);
+ break;
+
+ // (signed) decimal
+ case 'd':
+ num = getint(&ap, lflag);
+ if ((long long) num < 0) {
+ putch('-', putdat);
+ num = -(long long) num;
+ }
+ base = 10;
+ goto signed_number;
+
+ // unsigned decimal
+ case 'u':
+ base = 10;
+ goto unsigned_number;
+
+ // (unsigned) octal
+ case 'o':
+ // should do something with padding so it's always 3 octits
+ base = 8;
+ goto unsigned_number;
+
+ // pointer
+ case 'p':
+ static_assert(sizeof(long) == sizeof(void*));
+ lflag = 1;
+ putch('0', putdat);
+ putch('x', putdat);
+ /* fall through to 'x' */
+
+ // (unsigned) hexadecimal
+ case 'x':
+ base = 16;
+ unsigned_number:
+ num = getuint(&ap, lflag);
+ signed_number:
+ printnum(putch, putdat, num, base, width, padc);
+ break;
+
+ // escaped '%' character
+ case '%':
+ putch(ch, putdat);
+ break;
+
+ // unrecognized escape sequence - just print it literally
+ default:
+ putch('%', putdat);
+ fmt = last_fmt;
+ break;
+ }
+ }
+}
+
+int printf(const char* fmt, ...)
+{
+ va_list ap;
+ va_start(ap, fmt);
+
+ vprintfmt((void*)putchar, 0, fmt, ap);
+
+ va_end(ap);
+ return 0; // incorrect return value, but who cares, anyway?
+}
+
+int sprintf(char* str, const char* fmt, ...)
+{
+ va_list ap;
+ char* str0 = str;
+ va_start(ap, fmt);
+
+ void sprintf_putch(int ch, void** data)
+ {
+ char** pstr = (char**)data;
+ **pstr = ch;
+ (*pstr)++;
+ }
+
+ vprintfmt(sprintf_putch, (void**)&str, fmt, ap);
+ *str = 0;
+
+ va_end(ap);
+ return str - str0;
+}
+
+void* memcpy(void* dest, const void* src, size_t len)
+{
+ if ((((uintptr_t)dest | (uintptr_t)src | len) & (sizeof(uintptr_t)-1)) == 0) {
+ const uintptr_t* s = src;
+ uintptr_t *d = dest;
+ while (d < (uintptr_t*)(dest + len))
+ *d++ = *s++;
+ } else {
+ const char* s = src;
+ char *d = dest;
+ while (d < (char*)(dest + len))
+ *d++ = *s++;
+ }
+ return dest;
+}
+
+void* memset(void* dest, int byte, size_t len)
+{
+ if ((((uintptr_t)dest | len) & (sizeof(uintptr_t)-1)) == 0) {
+ uintptr_t word = byte & 0xFF;
+ word |= word << 8;
+ word |= word << 16;
+ word |= word << 16 << 16;
+
+ uintptr_t *d = dest;
+ while (d < (uintptr_t*)(dest + len))
+ *d++ = word;
+ } else {
+ char *d = dest;
+ while (d < (char*)(dest + len))
+ *d++ = byte;
+ }
+ return dest;
+}
+
+size_t strlen(const char *s)
+{
+ const char *p = s;
+ while (*p)
+ p++;
+ return p - s;
+}
+
+size_t strnlen(const char *s, size_t n)
+{
+ const char *p = s;
+ while (n-- && *p)
+ p++;
+ return p - s;
+}
+
+int strcmp(const char* s1, const char* s2)
+{
+ unsigned char c1, c2;
+
+ do {
+ c1 = *s1++;
+ c2 = *s2++;
+ } while (c1 != 0 && c1 == c2);
+
+ return c1 - c2;
+}
+
+char* strcpy(char* dest, const char* src)
+{
+ char* d = dest;
+ while ((*d++ = *src++))
+ ;
+ return dest;
+}
+
+long atol(const char* str)
+{
+ long res = 0;
+ int sign = 0;
+
+ while (*str == ' ')
+ str++;
+
+ if (*str == '-' || *str == '+') {
+ sign = *str == '-';
+ str++;
+ }
+
+ while (*str) {
+ res *= 10;
+ res += *str++ - '0';
+ }
+
+ return sign ? -res : res;
+}
\ No newline at end of file
diff --git a/verif/tests/custom/zcmt/util.h b/verif/tests/custom/zcmt/util.h
new file mode 100644
index 0000000000..1758ece6f5
--- /dev/null
+++ b/verif/tests/custom/zcmt/util.h
@@ -0,0 +1,92 @@
+// See LICENSE for license details.
+
+#ifndef __UTIL_H
+#define __UTIL_H
+
+extern void setStats(int enable);
+
+#include
+
+#define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; }
+
+static int verify(int n, const volatile int* test, const int* verify)
+{
+ int i;
+ // Unrolled for faster verification
+ for (i = 0; i < n/2*2; i+=2)
+ {
+ int t0 = test[i], t1 = test[i+1];
+ int v0 = verify[i], v1 = verify[i+1];
+ if (t0 != v0) return i+1;
+ if (t1 != v1) return i+2;
+ }
+ if (n % 2 != 0 && test[n-1] != verify[n-1])
+ return n;
+ return 0;
+}
+
+static int verifyDouble(int n, const volatile double* test, const double* verify)
+{
+ int i;
+ // Unrolled for faster verification
+ for (i = 0; i < n/2*2; i+=2)
+ {
+ double t0 = test[i], t1 = test[i+1];
+ double v0 = verify[i], v1 = verify[i+1];
+ int eq1 = t0 == v0, eq2 = t1 == v1;
+ if (!(eq1 & eq2)) return i+1+eq1;
+ }
+ if (n % 2 != 0 && test[n-1] != verify[n-1])
+ return n;
+ return 0;
+}
+
+static void __attribute__((noinline)) barrier(int ncores)
+{
+#ifdef __riscv_atomic // __sync_* builtins require A extension
+ static volatile int sense;
+ static volatile int count;
+ static __thread int threadsense;
+
+ __sync_synchronize();
+
+ threadsense = !threadsense;
+ if (__sync_fetch_and_add(&count, 1) == ncores-1)
+ {
+ count = 0;
+ sense = threadsense;
+ }
+ else while(sense != threadsense)
+ ;
+
+ __sync_synchronize();
+#endif // __riscv_atomic
+}
+
+static uint64_t lfsr(uint64_t x)
+{
+ uint64_t bit = (x ^ (x >> 1)) & 1;
+ return (x >> 1) | (bit << 62);
+}
+
+static uintptr_t insn_len(uintptr_t pc)
+{
+ return (*(unsigned short*)pc & 3) ? 4 : 2;
+}
+
+#ifdef __riscv
+#include "encoding.h"
+#endif
+
+#define stringify_1(s) #s
+#define stringify(s) stringify_1(s)
+#define stats(code, iter) do { \
+ unsigned long _c = -read_csr(mcycle), _i = -read_csr(minstret); \
+ code; \
+ _c += read_csr(mcycle), _i += read_csr(minstret); \
+ if (cid == 0) \
+ printf("\n%s: %ld cycles, %ld.%ld cycles/iter, %ld.%ld CPI\n", \
+ stringify(code), _c, _c/iter, 10*_c/iter%10, _c/_i, 10*_c/_i%10); \
+ } while(0)
+
+#endif //__UTIL_H
\ No newline at end of file
diff --git a/verif/tests/testlist_pmp-cv32a65x.yaml b/verif/tests/testlist_pmp-cv32a65x.yaml
new file mode 100644
index 0000000000..fa3da4cdd5
--- /dev/null
+++ b/verif/tests/testlist_pmp-cv32a65x.yaml
@@ -0,0 +1,77 @@
+# Copyright 2025 Thales CDI
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https:#solderpad.org/licenses/
+#
+# Original Author: Valentin Thomazic (valentin.thomazic@thalesgroup.com)
+
+# ================================================================================
+# Regression test list format
+# --------------------------------------------------------------------------------
+# testlist : Assembly test list
+# test : Assembly test name
+# description : Description of this test
+# gen_opts : Instruction generator options
+# iterations : Number of iterations of this test
+# no_iss : Enable/disable ISS simulator (Optional)
+# gen_test : Test name used by the instruction generator
+# asm_tests : Path to directed, hand-coded assembly test file or directory
+# rtl_test : RTL simulation test name
+# cmp_opts : Compile options passed to the instruction generator
+# sim_opts : Simulation options passed to the instruction generator
+# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
+# compare_opts : Options for the RTL & ISS trace comparison
+# gcc_opts : gcc compile options
+# --------------------------------------------------------------------------------
+
+common_test_config: &common_test_config
+ path_var: TESTS_PATH
+ gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
+
+testlist:
+ - test: decreasing_entries_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/decreasing_entries_test.S
+
+ - test: defined_matches
+ <<: *common_test_config
+ iterations: 0
+ asm_tests: /custom/pmp/defined_matches.S
+
+ - test: double_entries_test
+ <<: *common_test_config
+ iterations: 0
+ asm_tests: /custom/pmp/double_entries_test.S
+
+ - test: exact_csrr_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/exact_csrr_test.S
+
+ - test: granularity_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/granularity_test.S
+
+ - test: locked_outside_napot_test
+ <<: *common_test_config
+ iterations: 0
+ asm_tests: /custom/pmp/locked_outside_napot_test.S
+
+ - test: locked_outside_tor_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/locked_outside_tor_test.S
+
+ - test: lsu_napot_test
+ <<: *common_test_config
+ iterations: 0
+ asm_tests: /custom/pmp/lsu_napot_test.S
+
+ - test: lsu_tor_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/lsu_tor_test.S
diff --git a/verif/tests/testlist_pmp-cv32a65x_axi.yaml b/verif/tests/testlist_pmp-cv32a65x_axi.yaml
new file mode 100644
index 0000000000..fa3da4cdd5
--- /dev/null
+++ b/verif/tests/testlist_pmp-cv32a65x_axi.yaml
@@ -0,0 +1,77 @@
+# Copyright 2025 Thales CDI
+#
+# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0
+# You may obtain a copy of the License at https:#solderpad.org/licenses/
+#
+# Original Author: Valentin Thomazic (valentin.thomazic@thalesgroup.com)
+
+# ================================================================================
+# Regression test list format
+# --------------------------------------------------------------------------------
+# testlist : Assembly test list
+# test : Assembly test name
+# description : Description of this test
+# gen_opts : Instruction generator options
+# iterations : Number of iterations of this test
+# no_iss : Enable/disable ISS simulator (Optional)
+# gen_test : Test name used by the instruction generator
+# asm_tests : Path to directed, hand-coded assembly test file or directory
+# rtl_test : RTL simulation test name
+# cmp_opts : Compile options passed to the instruction generator
+# sim_opts : Simulation options passed to the instruction generator
+# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
+# compare_opts : Options for the RTL & ISS trace comparison
+# gcc_opts : gcc compile options
+# --------------------------------------------------------------------------------
+
+common_test_config: &common_test_config
+ path_var: TESTS_PATH
+ gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -lgcc"
+
+testlist:
+ - test: decreasing_entries_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/decreasing_entries_test.S
+
+ - test: defined_matches
+ <<: *common_test_config
+ iterations: 0
+ asm_tests: /custom/pmp/defined_matches.S
+
+ - test: double_entries_test
+ <<: *common_test_config
+ iterations: 0
+ asm_tests: /custom/pmp/double_entries_test.S
+
+ - test: exact_csrr_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/exact_csrr_test.S
+
+ - test: granularity_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/granularity_test.S
+
+ - test: locked_outside_napot_test
+ <<: *common_test_config
+ iterations: 0
+ asm_tests: /custom/pmp/locked_outside_napot_test.S
+
+ - test: locked_outside_tor_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/locked_outside_tor_test.S
+
+ - test: lsu_napot_test
+ <<: *common_test_config
+ iterations: 0
+ asm_tests: /custom/pmp/lsu_napot_test.S
+
+ - test: lsu_tor_test
+ <<: *common_test_config
+ iterations: 1
+ asm_tests: /custom/pmp/lsu_tor_test.S
diff --git a/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv b/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv
index eb6f7adc3d..8ba4eb6344 100644
--- a/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv
+++ b/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv
@@ -143,7 +143,7 @@ task uvmt_cva6_firmware_test_c::run_phase(uvm_phase phase);
`uvm_info("TEST", "Test FINISHED", UVM_NONE)
// Set sim_finished (otherwise tb will flag that sim was aborted)
uvm_config_db#(bit)::set(null, "", "sim_finished", 1);
- uvm_config_db#(int)::set(null, "", "test_exit_code", { 0'b0, tb_exit_vif.tb_exit_o[31:1] });
+ uvm_config_db#(int)::set(null, "", "test_exit_code", { 1'b0, tb_exit_vif.tb_exit_o[31:1] });
// Let the termination-triggering instruction appear in the log.
@(posedge env_cntxt.clknrst_cntxt.vif.clk);
// Let all pending AXI requests settle.
+
+
+
+
+
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+ 
+ 
+ 
+ 
+
+ 
+ 
+