diff --git a/verif/tests/testlist_riscv-csr-access-test-cv32a6_imac_sv32.yaml b/verif/tests/testlist_riscv-csr-access-test-cv32a6_imac_sv32.yaml
new file mode 100644
index 0000000000..dc0eaa0d1d
--- /dev/null
+++ b/verif/tests/testlist_riscv-csr-access-test-cv32a6_imac_sv32.yaml
@@ -0,0 +1,72 @@
+## // Copyright 2023 Thales
+## // SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+#
+# ================================================================================
+#                  Regression test list format
+# --------------------------------------------------------------------------------
+# testlist        : Assembly test list
+# test            : Assembly test name
+# description     : Description of this test
+# gen_opts        : Instruction generator options
+# iterations      : Number of iterations of this test
+# no_iss          : Enable/disable ISS simulator (Optional)
+# gen_test        : Test name used by the instruction generator
+# asm_tests       : Path to directed, hand-coded assembly test file or directory
+# rtl_test        : RTL simulation test name
+# cmp_opts        : Compile options passed to the instruction generator
+# sim_opts        : Simulation options passed to the instruction generator
+# no_post_compare : Enable/disable comparison of trace log and ISS log (Optional)
+# compare_opts    : Options for the RTL & ISS trace comparison
+# gcc_opts        : gcc compile options
+# --------------------------------------------------------------------------------
+
+common_test_config: &common_test_config
+  path_var: TESTS_PATH
+
+testlist:
+  - test: M_RW_CSR
+    iterations: 1
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S
+
+  - test: S_RW_CSR
+    iterations: 1
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S
+
+  - test: M_RO_CSR
+    iterations: 1
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S
+
+  - test: M_MCYCLE_CSR
+    iterations: 0
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_mcycle_csr_test_0.S
+
+  - test: M_MCYCLEH_CSR
+    iterations: 0
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_mcycleh_csr_test_0.S
+
+  - test: M_MINSTRET_CSR
+    iterations: 0
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_minstret_csr_test_0.S
+
+  - test: M_MINSTRETH_CSR
+    iterations: 0
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_minstreth_csr_test_0.S
+
+  - test: U_CYCLE_CSR
+    iterations: 0
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S
+
+  - test: U_INSTRET_CSR
+    iterations: 0
+    <<: *common_test_config
+    asm_tests: <path_var>/custom/CSR/csr_access_tests/riscv_instret_csr_test_0.S
+
+