diff --git a/migen/build/lattice/common.py b/migen/build/lattice/common.py
index b3c61135e..2f56baeb0 100644
--- a/migen/build/lattice/common.py
+++ b/migen/build/lattice/common.py
@@ -45,14 +45,24 @@ class LatticeECPXTrellisTristateImpl(Module):
     def __init__(self, io, o, oe, i):
         nbits, sign = value_bits_sign(io)
         for bit in range(nbits):
-            self.specials += \
-                Instance("TRELLIS_IO",
-                    p_DIR="BIDIR",
-                    i_B=io[bit],
-                    i_I=o[bit],
-                    o_O=i[bit],
-                    i_T=~oe,
-                )
+            if len(oe) == 1:
+                self.specials += \
+                    Instance("TRELLIS_IO",
+                        p_DIR="BIDIR",
+                        i_B=io[bit],
+                        i_I=o[bit],
+                        o_O=i[bit],
+                        i_T=~oe,
+                    )
+            else:
+                self.specials += \
+                    Instance("TRELLIS_IO",
+                        p_DIR="BIDIR",
+                        i_B=io[bit],
+                        i_I=o[bit],
+                        o_O=i[bit],
+                        i_T=~oe[bit],
+                    )
 
 class LatticeECPXTrellisTristate(Module):
     @staticmethod
@@ -99,15 +109,24 @@ def __init__(self, io, o, oe, i):
                 )
         else:
             for bit in range(nbits):
-                self.specials += \
-                    Instance("SB_IO",
-                        p_PIN_TYPE=C(0b101001, 6),
-                        io_PACKAGE_PIN=io[bit],
-                        i_OUTPUT_ENABLE=oe,
-                        i_D_OUT_0=o[bit],
-                        o_D_IN_0=i[bit],
-                    )
-
+                if len(oe) == 1:
+                    self.specials += \
+                        Instance("SB_IO",
+                                 p_PIN_TYPE=C(0b101001, 6),
+                                 io_PACKAGE_PIN=io[bit],
+                                 i_OUTPUT_ENABLE=oe,
+                                 i_D_OUT_0=o[bit],
+                                 o_D_IN_0=i[bit],
+                        )
+                else:
+                    self.specials += \
+                        Instance("SB_IO",
+                                 p_PIN_TYPE=C(0b101001, 6),
+                                 io_PACKAGE_PIN=io[bit],
+                                 i_OUTPUT_ENABLE=oe[bit],
+                                 i_D_OUT_0=o[bit],
+                                 o_D_IN_0=i[bit],
+                        )
 
 class LatticeiCE40Tristate(Module):
     @staticmethod
diff --git a/migen/fhdl/specials.py b/migen/fhdl/specials.py
index 3c3f8658b..7dc9fd159 100644
--- a/migen/fhdl/specials.py
+++ b/migen/fhdl/specials.py
@@ -110,11 +110,15 @@ def pe(e):
 
 class TSTriple:
     def __init__(self, bits_sign=None, min=None, max=None, reset_o=0, reset_oe=0, reset_i=0,
-                 name=None):
+                 name=None, per_bit_oe=False):
         self.o = Signal(bits_sign, min=min, max=max, reset=reset_o,
                         name=None if name is None else name + "_o")
-        self.oe = Signal(reset=reset_oe,
-                         name=None if name is None else name + "_oe")
+        if per_bit_oe:
+            self.oe = Signal(bits_sign, min=min, max=max, reset=reset_oe,
+                             name=None if name is None else name + "_oe")
+        else:
+            self.oe = Signal(reset=reset_oe,
+                             name=None if name is None else name + "_oe")
         self.i = Signal(bits_sign, min=min, max=max, reset=reset_i,
                         name=None if name is None else name + "_i")