Skip to content

[clkmgr, dv] Clock Manager DV ported to Mocha #560

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Draft
KolosKoblasz-Semify wants to merge 13 commits into
base: main
Choose a base branch
from
Draft

[clkmgr, dv] Clock Manager DV ported to Mocha #560

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
13 commits
Select commit Hold shift + click to select a range
e628e47
[rstmgr_dv, vendoring] Reset Manager paths patched
KolosKoblasz-Semify Apr 29, 2026
e959b5a
[rstmgr, vendoring] Patched Configfiles commited
KolosKoblasz-Semify May 8, 2026
947bd5b
[rstmgr_dv, vendoring] Template file patches added
KolosKoblasz-Semify May 15, 2026
cfb9b39
[rstmgr, vendoring] Fixed template files commited
KolosKoblasz-Semify May 15, 2026
d1396db
[rstmgr, dv] rstmgr added to top level dv
KolosKoblasz-Semify May 8, 2026
34901ce
[i2c, vendoring] Not needed .patch files removed
KolosKoblasz-Semify May 11, 2026
edbac61
[prim_xilinx, vendoring] Not needed .patch files removed
KolosKoblasz-Semify May 11, 2026
771b9f0
Update lowrisc_ip to lowRISC/opentitan@7e53929271
KolosKoblasz-Semify May 11, 2026
9af77e3
[rstmgr_dv, autogen] Autogenerated code added
KolosKoblasz-Semify May 15, 2026
5628665
[clkmgr, vendoring] Path fixes added to patch file
KolosKoblasz-Semify May 13, 2026
7690294
[clkmgr, vendoring] Modified template files commited
KolosKoblasz-Semify May 13, 2026
f8a94fb
[clkmgr, dv] Autogenerated files commited
KolosKoblasz-Semify May 13, 2026
07cd183
[clkmgr, dv] clkmgr added to mocha tests
KolosKoblasz-Semify May 13, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 2 additions & 0 deletions hw/top_chip/dv/mocha_sim_cfgs.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,9 @@
"{proj_root}/hw/vendor/lowrisc_ip/ip/prim/dv/prim_lfsr/prim_lfsr_sim_cfg.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/i2c_sim_cfg.hjson",
"{proj_root}/hw/top_chip/ip/xbar_peri/dv/autogen/xbar_peri_sim_cfg.hjson",
"{proj_root}/hw/top_chip/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson",
"{proj_root}/hw/top_chip/ip_autogen/gpio/dv/gpio_sim_cfg.hjson",
"{proj_root}/hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/ip/rom_ctrl/dv/rom_ctrl_32kB_sim_cfg.hjson",
"{proj_root}/hw/top_chip/tmp_sim_cfg/rv_dm_use_jtag_interface_sim_cfg.hjson",

Expand Down
4 changes: 2 additions & 2 deletions hw/top_chip/ip_autogen/alert_handler/dv/env/alert_handler_env_cfg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,9 +18,9 @@ class alert_handler_env_cfg extends cip_base_env_cfg #(.RAL_T(alert_handler_reg_

`uvm_object_new

virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
virtual function void initialize();
num_edn = 1;
super.initialize(csr_base_addr);
super.initialize();
shadow_update_err_status_fields[ral.loc_alert_cause[LocalShadowRegUpdateErr].la] = 1;
shadow_storage_err_status_fields[ral.loc_alert_cause[LocalShadowRegStorageErr].la] = 1;

Expand Down
14 changes: 7 additions & 7 deletions hw/top_chip/ip_autogen/clkmgr/data/clkmgr_testplan.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,14 +3,14 @@
// SPDX-License-Identifier: Apache-2.0
{
name: "clkmgr"
import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
"hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
"hw/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/shadow_reg_errors_testplan.hjson",
"clkmgr_sec_cm_testplan.hjson",
"hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson"]
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson"]
testpoints: [
{
name: smoke
Expand Down
16 changes: 8 additions & 8 deletions hw/top_chip/ip_autogen/clkmgr/dv/clkmgr_sim_cfg.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
tb: tb

// Simulator used to sign off this block
tool: vcs
tool: xcelium

// Fusesoc core file used for building the file list.
fusesoc_core: lowrisc:mocha_dv:clkmgr_sim:0.1
Expand All @@ -25,14 +25,14 @@

// Import additional common sim cfg files.
import_cfgs: [// Project wide common sim cfg file
"{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
// Common CIP test lists
"{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson"
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/shadow_reg_errors_tests.hjson"
]

// Add additional tops for simulation.
Expand Down
4 changes: 2 additions & 2 deletions hw/top_chip/ip_autogen/clkmgr/dv/env/clkmgr_env_cfg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -26,9 +26,9 @@ class clkmgr_env_cfg extends cip_base_env_cfg #(

`uvm_object_new

virtual function void initialize(bit [31:0] csr_base_addr = '1);
virtual function void initialize();
list_of_alerts = clkmgr_env_pkg::LIST_OF_ALERTS;
super.initialize(csr_base_addr);
super.initialize();

// This is for the integrity error test.
tl_intg_alert_name = "fatal_fault";
Expand Down
8 changes: 4 additions & 4 deletions hw/top_chip/ip_autogen/clkmgr/dv/env/seq_lib/clkmgr_regwen_vseq.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -11,16 +11,16 @@ class clkmgr_regwen_vseq extends clkmgr_base_vseq;

task check_jitter_regwen();
bit enable;
mubi4_t prev_value;
mubi4_t new_value;
logic [3:0] prev_value_bits;
mubi4_t new_value;

`DV_CHECK_STD_RANDOMIZE_FATAL(enable)
new_value = get_rand_mubi4_val(.t_weight(1), .f_weight(1), .other_weight(2));
`uvm_info(`gfn, $sformatf("Check jitter_regwen = %b", enable), UVM_MEDIUM)
csr_wr(.ptr(ral.jitter_regwen), .value(enable));
csr_rd(.ptr(ral.jitter_enable), .value(prev_value));
csr_rd(.ptr(ral.jitter_enable), .value(prev_value_bits));
csr_wr(.ptr(ral.jitter_enable), .value(new_value));
csr_rd_check(.ptr(ral. jitter_enable), .compare_value(enable ? new_value : prev_value));
csr_rd_check(.ptr(ral.jitter_enable), .compare_value(enable ? new_value : prev_value_bits));
`uvm_info(`gfn, "Check jitter_regwen done", UVM_MEDIUM)
endtask : check_jitter_regwen

Expand Down
56 changes: 52 additions & 4 deletions hw/top_chip/ip_autogen/clkmgr/rtl/clkmgr_reg_top.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -609,6 +609,18 @@ module clkmgr_reg_top (
// F[hi]: 8:0
logic async_io_meas_ctrl_shadowed_hi_err_update;
logic async_io_meas_ctrl_shadowed_hi_err_storage;
logic deglitched_io_meas_ctrl_shadowed_hi_err_storage;

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_io_meas_ctrl_shadowed_hi_err_storage_deglitch (
.clk_i (clk_io_i),
.rst_ni(rst_io_ni),
.d_i (async_io_meas_ctrl_shadowed_hi_err_storage),
.q_o (deglitched_io_meas_ctrl_shadowed_hi_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -617,7 +629,7 @@ module clkmgr_reg_top (
) u_io_meas_ctrl_shadowed_hi_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_io_meas_ctrl_shadowed_hi_err_storage),
.d_i(deglitched_io_meas_ctrl_shadowed_hi_err_storage),
.q_o(io_meas_ctrl_shadowed_hi_storage_err)
);

Expand Down Expand Up @@ -668,6 +680,18 @@ module clkmgr_reg_top (
// F[lo]: 17:9
logic async_io_meas_ctrl_shadowed_lo_err_update;
logic async_io_meas_ctrl_shadowed_lo_err_storage;
logic deglitched_io_meas_ctrl_shadowed_lo_err_storage;

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_io_meas_ctrl_shadowed_lo_err_storage_deglitch (
.clk_i (clk_io_i),
.rst_ni(rst_io_ni),
.d_i (async_io_meas_ctrl_shadowed_lo_err_storage),
.q_o (deglitched_io_meas_ctrl_shadowed_lo_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -676,7 +700,7 @@ module clkmgr_reg_top (
) u_io_meas_ctrl_shadowed_lo_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_io_meas_ctrl_shadowed_lo_err_storage),
.d_i(deglitched_io_meas_ctrl_shadowed_lo_err_storage),
.q_o(io_meas_ctrl_shadowed_lo_storage_err)
);

Expand Down Expand Up @@ -767,6 +791,18 @@ module clkmgr_reg_top (
// F[hi]: 8:0
logic async_main_meas_ctrl_shadowed_hi_err_update;
logic async_main_meas_ctrl_shadowed_hi_err_storage;
logic deglitched_main_meas_ctrl_shadowed_hi_err_storage;

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_main_meas_ctrl_shadowed_hi_err_storage_deglitch (
.clk_i (clk_main_i),
.rst_ni(rst_main_ni),
.d_i (async_main_meas_ctrl_shadowed_hi_err_storage),
.q_o (deglitched_main_meas_ctrl_shadowed_hi_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -775,7 +811,7 @@ module clkmgr_reg_top (
) u_main_meas_ctrl_shadowed_hi_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_main_meas_ctrl_shadowed_hi_err_storage),
.d_i(deglitched_main_meas_ctrl_shadowed_hi_err_storage),
.q_o(main_meas_ctrl_shadowed_hi_storage_err)
);

Expand Down Expand Up @@ -826,6 +862,18 @@ module clkmgr_reg_top (
// F[lo]: 17:9
logic async_main_meas_ctrl_shadowed_lo_err_update;
logic async_main_meas_ctrl_shadowed_lo_err_storage;
logic deglitched_main_meas_ctrl_shadowed_lo_err_storage;

// flop storage error to filter combinational glitches before sending it across CDC
prim_flop #(
.Width(1),
.ResetValue('0)
) u_main_meas_ctrl_shadowed_lo_err_storage_deglitch (
.clk_i (clk_main_i),
.rst_ni(rst_main_ni),
.d_i (async_main_meas_ctrl_shadowed_lo_err_storage),
.q_o (deglitched_main_meas_ctrl_shadowed_lo_err_storage)
);

// storage error is persistent and can be sampled at any time
prim_flop_2sync #(
Expand All @@ -834,7 +882,7 @@ module clkmgr_reg_top (
) u_main_meas_ctrl_shadowed_lo_err_storage_sync (
.clk_i,
.rst_ni,
.d_i(async_main_meas_ctrl_shadowed_lo_err_storage),
.d_i(deglitched_main_meas_ctrl_shadowed_lo_err_storage),
.q_o(main_meas_ctrl_shadowed_lo_storage_err)
);

Expand Down
4 changes: 2 additions & 2 deletions hw/top_chip/ip_autogen/gpio/dv/env/gpio_env_cfg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -24,9 +24,9 @@ class gpio_env_cfg extends cip_base_env_cfg #(
super.new(name);
endfunction

virtual function void initialize(bit [TL_AW-1:0] csr_base_addr = '1);
virtual function void initialize();
list_of_alerts = gpio_env_pkg::LIST_OF_ALERTS;
super.initialize(csr_base_addr);
super.initialize();
// set num_interrupts & num_alerts which will be used to create coverage and more
num_interrupts = ral.intr_state.get_n_used_bits();

Expand Down
4 changes: 2 additions & 2 deletions hw/top_chip/ip_autogen/pwrmgr/dv/env/pwrmgr_env_cfg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -31,9 +31,9 @@ class pwrmgr_env_cfg extends cip_base_env_cfg #(
// The run_phase object, to deal with objections.
uvm_phase run_phase;

virtual function void initialize(bit [31:0] csr_base_addr = '1);
virtual function void initialize();
list_of_alerts = pwrmgr_env_pkg::LIST_OF_ALERTS;
super.initialize(csr_base_addr);
super.initialize();
num_interrupts = ral.intr_state.get_n_used_bits();
`ASSERT_I(NumInstrMatch_A, num_interrupts == NUM_INTERRUPTS)
`uvm_info(`gfn, $sformatf("num_interrupts = %0d", num_interrupts), UVM_MEDIUM)
Expand Down
1 change: 0 additions & 1 deletion hw/top_chip/ip_autogen/pwrmgr/dv/env/seq_lib/pwrmgr_reset_invalid_vseq.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,6 @@ class pwrmgr_reset_invalid_vseq extends pwrmgr_base_vseq;

wait_for_rom_and_active();
check_reset_status('0);
$assertoff(0, "tb.dut.u_cdc.u_clr_reqack.SyncReqAckHoldReq");

for (int i = 0; i < num_of_target_states; ++i) begin
`uvm_info(`gfn, $sformatf("Starting new round %0d", i), UVM_MEDIUM)
Expand Down
12 changes: 6 additions & 6 deletions hw/top_chip/ip_autogen/rstmgr/data/rstmgr_testplan.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,12 @@
// SPDX-License-Identifier: Apache-2.0
{
name: "rstmgr"
import_testplans: ["hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
"hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
"hw/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
"hw/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_count_testplan.hjson",
"hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/sec_cm_fsm_testplan.hjson",
"rstmgr_sec_cm_testplan.hjson"]

testpoints: [
Expand Down
4 changes: 2 additions & 2 deletions hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_env_cfg.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -23,9 +23,9 @@ class rstmgr_env_cfg extends cip_base_env_cfg #(
virtual rstmgr_cascading_sva_if rstmgr_cascading_sva_vif;
virtual rstmgr_if rstmgr_vif;

virtual function void initialize(bit [31:0] csr_base_addr = '1);
virtual function void initialize();
list_of_alerts = rstmgr_env_pkg::LIST_OF_ALERTS;
super.initialize(csr_base_addr);
super.initialize();

tl_intg_alert_fields[ral.err_code.reg_intg_err] = 1;
m_tl_agent_cfg.max_outstanding_req = 1;
Expand Down
2 changes: 1 addition & 1 deletion hw/top_chip/ip_autogen/rstmgr/dv/env/rstmgr_if.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -65,5 +65,5 @@ interface rstmgr_if (
always_comb cpu_info_en = `PATH_TO_DUT.reg2hw.cpu_info_ctrl.en.q;

bit rst_ni_inactive;
always_comb rst_ni_inactive = resets_o.rst_lc_io_n[rstmgr_pkg::Domain0Sel];
always_comb rst_ni_inactive = resets_o.rst_io_n[rstmgr_pkg::Domain0Sel];
endinterface
6 changes: 3 additions & 3 deletions hw/top_chip/ip_autogen/rstmgr/dv/env/seq_lib/rstmgr_reset_vseq.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -115,8 +115,8 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
expected_cpu_enable = 0;

cfg.clk_rst_vif.wait_clks(8);
// Wait till rst_lc_n is inactive for non-aon.
`DV_WAIT(cfg.rstmgr_vif.resets_o.rst_lc_n[1])
// Wait till rst_io_n is inactive for non-aon.
`DV_WAIT(cfg.rstmgr_vif.resets_o.rst_io_n[1])

check_reset_info(get_reset_code(start_reset, 0), {reset_name[start_reset], " reset"});
check_alert_info_after_reset(expected_alert_dump, expected_alert_enable);
Expand Down Expand Up @@ -172,7 +172,7 @@ class rstmgr_reset_vseq extends rstmgr_base_vseq;
reset_done();

cfg.io_clk_rst_vif.wait_clks(8);
wait(cfg.rstmgr_vif.resets_o.rst_lc_n[1]);
wait(cfg.rstmgr_vif.resets_o.rst_io_n[1]);
check_reset_info(expected_reset_info_code);
check_alert_info_after_reset(.alert_dump(expected_alert_dump),
.enable(expected_alert_enable));
Expand Down
2 changes: 1 addition & 1 deletion hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_cnsty_chk/rstmgr_cnsty_chk_sim_cfg.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -21,7 +21,7 @@
testplan: "{self_dir}/data/rstmgr_cnsty_chk_testplan.hjson"

// Import additional common sim cfg files.
import_cfgs: ["{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson"]
import_cfgs: ["{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson"]


// Specific exclusion files.
Expand Down
14 changes: 7 additions & 7 deletions hw/top_chip/ip_autogen/rstmgr/dv/rstmgr_sim_cfg.hjson
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@
tb: tb

// Simulator used to sign off this block
tool: vcs
tool: xcelium

// Fusesoc core file used for building the file list.
fusesoc_core: lowrisc:mocha_dv:rstmgr_sim:0.1
Expand All @@ -25,16 +25,16 @@

// Import additional common sim cfg files.
import_cfgs: [// Project wide common sim cfg file
"{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
// Common CIP test lists
"{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
"{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
// Just run the stress_all sequence, and don't inject random
// resets since we may get overlapping resets due to sequences
// that inject them.
"{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"
"{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson"
]

// Specific exclusion files.
Expand Down
24 changes: 14 additions & 10 deletions hw/top_chip/ip_autogen/rstmgr/dv/sva/rstmgr_cascading_sva_if.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -158,17 +158,21 @@ interface rstmgr_cascading_sva_if (
`CASCADED_ASSERTS(CascadeEffAonToRstPorMain, effective_aon_rst_n[rstmgr_pkg::DomainAonSel],
resets_o.rst_por_n[rstmgr_pkg::DomainAonSel], SyncCycles, clk_main_i)

// Controlled by rst_lc_src_n.
`CASCADED_ASSERTS(CascadeLcToLcAon, rst_lc_src_n[rstmgr_pkg::DomainAonSel],
resets_o.rst_lc_aon_n[rstmgr_pkg::DomainAonSel], SysCycles, clk_aon_i)
`CASCADED_ASSERTS(CascadeLcToLc, rst_lc_src_n[rstmgr_pkg::Domain0Sel],
resets_o.rst_lc_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i)

// Controlled by rst_sys_src_n.
`CASCADED_ASSERTS(CascadeSysToSys, rst_sys_src_n[rstmgr_pkg::Domain0Sel],
resets_o.rst_sys_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_main_i)
`CASCADED_ASSERTS(CascadeLcToLcShadowed, rst_lc_src_n[rstmgr_pkg::Domain0Sel],
resets_o.rst_lc_shadowed_n[rstmgr_pkg::Domain0Sel], SysCycles, clk_main_i)
`CASCADED_ASSERTS(CascadeSysToMain_A, rst_sys_src_n[rstmgr_pkg::Domain0Sel],
resets_o.rst_main_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_main_i)

`CASCADED_ASSERTS(CascadeSysToIO_A, rst_sys_src_n[rstmgr_pkg::Domain0Sel],
resets_o.rst_io_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_io_i)

`CASCADED_ASSERTS(CascadeSysToSPIHost_A, rst_sys_src_n[rstmgr_pkg::Domain0Sel],
resets_o.rst_spi_host_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_io_i)

`CASCADED_ASSERTS(CascadeSysToSPIDevice_A, rst_sys_src_n[rstmgr_pkg::Domain0Sel],
resets_o.rst_spi_device_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_io_i)

`CASCADED_ASSERTS(CascadeSysToI2C_A, rst_sys_src_n[rstmgr_pkg::Domain0Sel],
resets_o.rst_i2c_n[rstmgr_pkg::Domain0Sel], PeriCycles, clk_io_i)

`undef FALL_ASSERT
`undef RISE_ASSERTS
Expand Down
Loading
Loading