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[spi_host] Low-level SD card support #446

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743f58f
[hw] Connect SPI Host to microSD card slot/model
elliotb-lowrisc May 7, 2026
5cc9042
[sw] Low-level SPI Host SD card helpers and tests
elliotb-lowrisc May 20, 2026
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3 changes: 3 additions & 0 deletions .gitignore
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Expand Up @@ -27,3 +27,6 @@ __pycache__
scratch/
# clangd
.cache

# SD card image file
sd.img
4 changes: 4 additions & 0 deletions doc/ref/dev_guide.md
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Expand Up @@ -153,6 +153,8 @@ To run the Verilator tests, first build the software, then run:
ctest --test-dir build/sw -R sim_verilator
```

The contents of the Verilator testbench SD card model can be set by providing an "sd.img" file in the repository root directory.

## FPGA

### OpenFPGALoader
Expand Down Expand Up @@ -214,6 +216,8 @@ Some peripheral tests require additional hardware to be connected to the Genesys

- I^2C: AS6212 Temperature Sensor connected to header "JA" according to PMOD Interface Type 6 (I^2C).
- i.e. header "JA" top-row left-to-right: VCC, GND, SDA, SCL, (NC), (NC)
- SPI Host: a FAT32-formatted SDHC/SDXC microSD card containing the "lorem.ips" file inserted in the onboard microSD slot.
- See "lorem_text.h" for details on the file contents.

## Verification

Expand Down
24 changes: 20 additions & 4 deletions hw/top_chip/data/pins_genesys2.xdc
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Expand Up @@ -12,6 +12,7 @@ set_property -dict { PACKAGE_PIN AB25 IOSTANDARD LVCMOS33 } [get_ports { ftdi_r

## GPIO
# Inputs
# User switches
set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS18 } [get_ports { gpio_i[0] }]; # SW0 (VADJ)
set_property -dict { PACKAGE_PIN G25 IOSTANDARD LVCMOS18 } [get_ports { gpio_i[1] }]; # SW1 (VADJ)
set_property -dict { PACKAGE_PIN H24 IOSTANDARD LVCMOS18 } [get_ports { gpio_i[2] }]; # SW2 (VADJ)
Expand All @@ -20,11 +21,13 @@ set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS18 } [get_ports { gpio_i
set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS18 } [get_ports { gpio_i[5] }]; # SW5 (VADJ)
set_property -dict { PACKAGE_PIN P26 IOSTANDARD LVCMOS33 } [get_ports { gpio_i[6] }]; # SW6 (VCC3V3)
set_property -dict { PACKAGE_PIN P27 IOSTANDARD LVCMOS33 } [get_ports { gpio_i[7] }]; # SW7 (VCC3V3)

# Bootstrap pin, should be pulled down during boot to enter bootstrap mode.
set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { gpio_i[8] }];
# Bootstrap pin, should be pulled down during boot to enter bootstrap mode.
set_property -dict { PACKAGE_PIN AB29 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { gpio_i[8] }]; # PROG_RXFN
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# Micro SD card presence detect line (low = card present)
set_property -dict { PACKAGE_PIN P28 IOSTANDARD LVCMOS33 } [get_ports { gpio_i[9] }]; # SD_CD

# Outputs
# User LEDs
set_property -dict { PACKAGE_PIN T28 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[0] }]; # LED0
set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[1] }]; # LED1
set_property -dict { PACKAGE_PIN U30 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[2] }]; # LED2
Expand All @@ -33,6 +36,8 @@ set_property -dict { PACKAGE_PIN V20 IOSTANDARD LVCMOS33 } [get_ports { gpio_o
set_property -dict { PACKAGE_PIN V26 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[5] }]; # LED5
set_property -dict { PACKAGE_PIN W24 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[6] }]; # LED6
set_property -dict { PACKAGE_PIN W23 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[7] }]; # LED7
# Micro SD card power (VDD) control (active-low, ext. pull-up)
set_property -dict { PACKAGE_PIN AE24 IOSTANDARD LVCMOS33 } [get_ports { gpio_o[8] }]; # SD_RESET

## UART
set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { uart_rx_i }];
Expand All @@ -48,7 +53,7 @@ set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { uart_t
set_property -dict { PACKAGE_PIN T26 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { i2c_scl_io }];
set_property -dict { PACKAGE_PIN T27 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { i2c_sda_io }];

## SPI (PMOD Header JD)
## SPI Device (PMOD Header JD)
set_property -dict { PACKAGE_PIN W28 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { spi_device_sd_o }];
set_property -dict { PACKAGE_PIN W27 IOSTANDARD LVCMOS33 PULLTYPE PULLDOWN } [get_ports { spi_device_sd_i }];
set_property -dict { PACKAGE_PIN W29 IOSTANDARD LVCMOS33 PULLTYPE PULLUP } [get_ports { spi_device_csb_i }];
Expand All @@ -71,3 +76,14 @@ set_property -dict { PACKAGE_PIN AJ11 IOSTANDARD LVCMOS15 } [get_ports { eth_tx
set_property -dict { PACKAGE_PIN AK10 IOSTANDARD LVCMOS15 } [get_ports { eth_tx_d[3] }];
set_property -dict { PACKAGE_PIN AF12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdc }];
set_property -dict { PACKAGE_PIN AG12 IOSTANDARD LVCMOS15 } [get_ports { eth_mdio }];

## SPI Host (MicroSD card slot)
set_property -dict { PACKAGE_PIN R28 IOSTANDARD LVCMOS33 } [get_ports { spi_host_sck_o }]; # SD_SCLK
set_property -dict { PACKAGE_PIN R26 IOSTANDARD LVCMOS33 } [get_ports { spi_host_sd_i }]; # SD_DAT0
set_property -dict { PACKAGE_PIN T30 IOSTANDARD LVCMOS33 } [get_ports { spi_host_csb_o }]; # SD_DAT3
set_property -dict { PACKAGE_PIN R29 IOSTANDARD LVCMOS33 } [get_ports { spi_host_sd_o }]; # SD_CMD
# SPI Host signal copies for external logic analyser on PMOD "JB"
set_property -dict { PACKAGE_PIN W26 IOSTANDARD LVCMOS33 } [get_ports { spi_host_sck_o_dbg_o }]; # JB2_N (PMOD 4)
set_property -dict { PACKAGE_PIN V25 IOSTANDARD LVCMOS33 } [get_ports { spi_host_sd_i_dbg_o }]; # JB2_P (PMOD 3)
set_property -dict { PACKAGE_PIN V29 IOSTANDARD LVCMOS33 } [get_ports { spi_host_csb_o_dbg_o }]; # JB1_P (PMOD 1)
set_property -dict { PACKAGE_PIN V30 IOSTANDARD LVCMOS33 } [get_ports { spi_host_sd_o_dbg_o }]; # JB1_N (PMOD 2)
1 change: 1 addition & 0 deletions hw/top_chip/dv/verilator/top_chip_verilator.core
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Expand Up @@ -27,6 +27,7 @@ filesets:
- lowrisc:dv:sw_test_status
- lowrisc:dv:dv_test_status
- lowrisc:sonata:i2cdpi
- lowrisc:sonata:spidevicedpi

files:
- dram_wrapper_sim.sv: { file_type: systemVerilogSource }
Expand Down
59 changes: 39 additions & 20 deletions hw/top_chip/dv/verilator/top_chip_verilator.sv
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Expand Up @@ -30,13 +30,21 @@ module top_chip_verilator (
logic uart_rx;
logic uart_tx;

// SPI signals
// SPI device signals
logic spi_device_sck;
logic spi_device_csb;
logic [3:0] qspi_device_sdo;
logic [3:0] qspi_device_sdo_en;
logic spi_device_sdi;

// SPI host signals
logic spi_host_sck, spi_host_csb;
logic spi_host_sck_en, spi_host_csb_en;
logic spi_host_input;
logic [3:0] spi_host_sd_output;
logic [3:0] spi_host_sd_en_output;
logic microsd_det;

// Noise source signals
logic rng_enable;
logic rng_valid;
Expand All @@ -46,9 +54,6 @@ module top_chip_verilator (
top_pkg::axi_dram_req_t dram_req;
top_pkg::axi_dram_resp_t dram_resp;

logic [3:0] spi_host_sd;
logic [3:0] spi_host_sd_en;

// CHERI Mocha top
top_chip_system #(
.SramInitFile(""),
Expand All @@ -57,7 +62,7 @@ module top_chip_verilator (
.clk_i,
.rst_ni,

.gpio_i (gpio_inputs),
.gpio_i ({gpio_inputs[31:10], microsd_det, gpio_inputs[8:0]}),
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@marnovandermaas marnovandermaas May 8, 2026

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This is a little bit ugly because the gpio_input now will just ignore any writes to bit index 9. I'm not sure how to solve it more cleanly though.

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@elliotb-lowrisc elliotb-lowrisc May 13, 2026

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Indeed, I'm open to better ideas

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@marnovandermaas marnovandermaas May 20, 2026

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The only thing I can think of is that it is probably better to put the microSD detection in the most significant bit rather than in the middle. What do you think?

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@ziuziakowska ziuziakowska May 20, 2026

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If you do change the GPIO, make sure to update this line in the devicetree and regenerate it: https://github.com/lowRISC/mocha/blob/main/sw/device/devicetree/mocha.dts#L76

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@elliotb-lowrisc elliotb-lowrisc May 20, 2026

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Introducing a gap in the range of GPI lines in use might make things trickier on the FPGA-side, where at the moment the input signal is only wide enough for the number of GPI lines assigned to pins. We could change it so that the FPGA GPI input is 32-bits wide and only assign some a subset to pins in the XDC file, or we could adopt #411 and have the mapping of board signals to GPI lines in the RTL rather than constraints, where it would be easier to assign some constant values.

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@elliotb-lowrisc elliotb-lowrisc May 21, 2026

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@marnovandermaas your thoughts would be appreciated

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@marnovandermaas marnovandermaas May 22, 2026

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I think I would go for a gap where the most significant bits are ones you cannot affect by the DPI and any future general purpose inputs that can be affected by the DPI can be added contiguously at the bottom. I'm happy for you to also implement the #411 at the same time if you think that's not too much work.

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@elliotb-lowrisc elliotb-lowrisc May 22, 2026

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Alright, I'll move the input to a higher index. I might do the rest of the FPGA pin remapping an a subsequent PR.

@ziuziakowska Is there documentation you could point me to for how to re-generate the device tree?

.gpio_o (gpio_outputs),
.gpio_en_o (gpio_en_outputs),

Expand All @@ -82,17 +87,15 @@ module top_chip_verilator (
.spi_device_sd_i ({3'h0, spi_device_sdi}), // SPI MOSI = QSPI DQ0
.spi_device_tpm_csb_i ('0),

.spi_host_sck_o ( ),
.spi_host_sck_en_o ( ),
.spi_host_csb_o ( ),
.spi_host_csb_en_o ( ),
.spi_host_sd_o (spi_host_sd),
.spi_host_sd_en_o (spi_host_sd_en),
// Mapping output 0 to input 1 because legacy SPI does not allow
// bi-directional wires.
// This only works in standard mode where sd_o[0]=COPI and
// sd_i[1]=CIPO.
.spi_host_sd_i ({2'b0, spi_host_sd_en[0] ? spi_host_sd[0] : 1'b0, 1'b0}),
.spi_host_sck_o (spi_host_sck),
.spi_host_sck_en_o (spi_host_sck_en),
.spi_host_csb_o (spi_host_csb),
.spi_host_csb_en_o (spi_host_csb_en),
.spi_host_sd_o (spi_host_sd_output),
.spi_host_sd_en_o (spi_host_sd_en_output),
// Legacy SPI present in SD cards does not allow bi-directional wires.
// Work in standard mode where sd_o[0]=COPI and sd_i[1]=CIPO.
.spi_host_sd_i ({2'b0, spi_host_input, 1'b0}), // SPI CIPO = QSPI DQ1

.entropy_src_rng_enable_o (rng_enable),
.entropy_src_rng_valid_i (rng_valid),
Expand All @@ -108,8 +111,7 @@ module top_chip_verilator (
);

// No support for dual or quad SPI in loopback mode right now.
logic unused_spi_host = (|spi_host_sd[3:2]) | spi_host_sd[0] |
(|spi_host_sd_en[3:2]) | spi_host_sd_en[0];
logic unused_spi_host = |{spi_host_sd_output[3:1], spi_host_sd_en_output[3:1]};

// Virtual GPIO
gpiodpi #(
Expand Down Expand Up @@ -161,8 +163,25 @@ module top_chip_verilator (
.spi_device_sck_o (spi_device_sck),
.spi_device_csb_o (spi_device_csb),
.spi_device_sdi_o (spi_device_sdi),
.spi_device_sdo_i (qspi_device_sdo[1]), // SPI MISO = QSPI DQ1
.spi_device_sdo_en_i(qspi_device_sdo_en[1]) // SPI MISO = QSPI DQ1
.spi_device_sdo_i (qspi_device_sdo[1]), // SPI CIPO = QSPI DQ1
.spi_device_sdo_en_i(qspi_device_sdo_en[1]) // SPI CIPO = QSPI DQ1
);

// Virtual SPI Device - model an SD card (in a limited way)
spidevicedpi #(
.ID ("microsd"),
.NDevices (1),
.DataW (1),
.OOB_InW (1),
.OOB_OutW (1)
) u_spidevicedpi_microsd (
.rst_ni,
.sck (spi_host_sck_en ? spi_host_sck : 1'b0),
.cs (spi_host_csb_en ? spi_host_csb : 1'b0),
.copi (spi_host_sd_en_output[0] ? spi_host_sd_output[0] : 1'b0), // SPI COPI = QSPI DQ0
.cipo (spi_host_input),
.oob_in ( ), // not used
.oob_out(microsd_det)
);

`define DUT u_top_chip_system
Expand Down
95 changes: 70 additions & 25 deletions hw/top_chip/rtl/chip_mocha_genesys2.sv
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Expand Up @@ -14,9 +14,9 @@ module chip_mocha_genesys2 #(
input logic ext_rst_ni,
input logic ftdi_rst_ni,

// GPIO - enough for the user switches and LEDs as a starting point
input logic [8:0] gpio_i,
output logic [7:0] gpio_o,
// GPIO
input logic [9:0] gpio_i,
output logic [8:0] gpio_o,

// UART
input logic uart_rx_i,
Expand All @@ -26,13 +26,24 @@ module chip_mocha_genesys2 #(
inout logic i2c_scl_io,
inout logic i2c_sda_io,

// SPI
// SPI Device
input logic spi_device_sck_i,
input logic spi_device_csb_i,
input logic spi_device_sd_i,
output logic spi_device_sd_o,
output logic spien,

// SPI Host
output logic spi_host_sck_o,
output logic spi_host_csb_o,
input logic spi_host_sd_i,
output logic spi_host_sd_o,
// SPI Host signal copies for external logic analyser on PMOD "JB"
output logic spi_host_sck_o_dbg_o,
output logic spi_host_csb_o_dbg_o,
output logic spi_host_sd_i_dbg_o,
output logic spi_host_sd_o_dbg_o,

// DDR3
inout wire [31:0] ddr3_dq,
inout wire [ 3:0] ddr3_dqs_n,
Expand Down Expand Up @@ -116,9 +127,10 @@ module chip_mocha_genesys2 #(
logic i2c_scl_en_output, i2c_sda_en_output;
logic [3:0] qspi_device_sdo;
logic [3:0] qspi_device_sdo_en;

logic [3:0] spi_host_sd;
logic [3:0] spi_host_sd_en;
logic spi_host_sck_output, spi_host_csb_output;
logic spi_host_sck_en_output, spi_host_csb_en_output;
logic [3:0] spi_host_sd_output;
logic [3:0] spi_host_sd_en_output;

// Noise source signals
logic rng_enable;
Expand Down Expand Up @@ -218,7 +230,7 @@ module chip_mocha_genesys2 #(
.rst_ni (rst_n_sync_50m),

// GPIO
.gpio_i ({23'd0, gpio_i}),
.gpio_i (32'(gpio_i)),
.gpio_o (gpio_outputs),
.gpio_en_o (gpio_en_outputs),

Expand All @@ -244,21 +256,17 @@ module chip_mocha_genesys2 #(
.spi_device_csb_i (spi_device_csb_i),
.spi_device_sd_o (qspi_device_sdo),
.spi_device_sd_en_o (qspi_device_sdo_en),
.spi_device_sd_i ({3'h0, spi_device_sd_i}), // SPI MOSI = QSPI DQ0
.spi_device_sd_i ({3'h0, spi_device_sd_i}), // SPI COPI = QSPI DQ0
.spi_device_tpm_csb_i ('0),

// SPI host
.spi_host_sck_o ( ),
.spi_host_sck_en_o ( ),
.spi_host_csb_o ( ),
.spi_host_csb_en_o ( ),
.spi_host_sd_o (spi_host_sd),
.spi_host_sd_en_o (spi_host_sd_en),
// Mapping output 0 to input 1 because legacy SPI does not allow
// bi-directional wires.
// This only works in standard mode where sd_o[0]=COPI and
// sd_i[1]=CIPO.
.spi_host_sd_i ({2'b0, spi_host_sd_en[0] ? spi_host_sd[0] : 1'b0, 1'b0}),
.spi_host_sck_o (spi_host_sck_output),
.spi_host_sck_en_o (spi_host_sck_output_en),
.spi_host_csb_o (spi_host_csb_output),
.spi_host_csb_en_o (spi_host_csb_output_en),
.spi_host_sd_o (spi_host_sd_output),
.spi_host_sd_en_o (spi_host_sd_en_output),
.spi_host_sd_i ({2'b00, spi_host_sd_i, 1'b0}), // SPI CIPO = QSPI DQ1

// Entropy source
.entropy_src_rng_enable_o (rng_enable),
Expand All @@ -279,7 +287,7 @@ module chip_mocha_genesys2 #(

// GPIO tri-state output drivers
// Instantiate for only the outputs connected to an FPGA pin
for (genvar ii = 0; ii < 8; ii++) begin : gen_gpio_o
for (genvar ii = 0; ii < $bits(gpio_o); ii++) begin : gen_gpio_o
OBUFT obuft (
.I(gpio_outputs[ii]),
.T(~gpio_en_outputs[ii]),
Expand All @@ -301,13 +309,50 @@ module chip_mocha_genesys2 #(
.O (i2c_sda_input)
);

// SPI tri-state output driver
OBUFT spi_obuft (
.I(qspi_device_sdo[1]), // SPI MISO = QSPI DQ1
.T(~qspi_device_sdo_en[1]), // SPI MISO = QSPI DQ1
// SPI device tri-state output driver
OBUFT spi_device_obuft (
.I(qspi_device_sdo[1]), // SPI CIPO = QSPI DQ1
.T(~qspi_device_sdo_en[1]), // SPI CIPO = QSPI DQ1
.O(spi_device_sd_o)
);

// SPI host tri-state output drivers
OBUFT spi_host_sck_obuft (
.I(spi_host_sck_output),
.T(~spi_host_sck_output_en),
.O(spi_host_sck_o)
);
OBUFT spi_host_csb_obuft (
.I(spi_host_csb_output),
.T(~spi_host_csb_output_en),
.O(spi_host_csb_o)
);
// Legacy SPI present in SD cards does not allow bi-directional wires.
// Work in standard mode where sd_o[0]=COPI and sd_i[1]=CIPO.
// Other data outputs are unused.
OBUFT spi_host_sd_obuft (
.I(spi_host_sd_output[0]), // SPI COPI = QSPI DQ0
.T(~spi_host_sd_en_output[0]), // SPI COPI = QSPI DQ0
.O(spi_host_sd_o)
);
// SPI Host signal copies for external logic analyser on PMOD "JB"
assign spi_host_sd_i_dbg_o = spi_host_sd_i;
OBUFT spi_host_sck_obuft_dbg (
.I(spi_host_sck_output),
.T(~spi_host_sck_output_en),
.O(spi_host_sck_o_dbg_o)
);
OBUFT spi_host_csb_obuft_dbg (
.I(spi_host_csb_output),
.T(~spi_host_csb_output_en),
.O(spi_host_csb_o_dbg_o)
);
OBUFT spi_host_sd_obuft_dbg (
.I(spi_host_sd_output[0]), // SPI COPI = QSPI DQ0
.T(~spi_host_sd_en_output[0]), // SPI COPI = QSPI DQ0
.O(spi_host_sd_o_dbg_o)
);

// Noise source
rng u_rng(
.clk_i (u_top_chip_system.clkmgr_clocks.clk_io_infra),
Expand Down
18 changes: 17 additions & 1 deletion sw/device/lib/builtin.h
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Expand Up @@ -4,14 +4,30 @@

#pragma once

#include <stdint.h>

/* array length macro */
#define ARRAY_LEN(array) (sizeof(array) / sizeof((array)[0]))

/* inline assembly */
#define asm __asm__

/* count trailing zeroes */
#define ctz(x) (__builtin_ctz((x)))
#define ctz(x) (__builtin_ctz((x)))
#define ctzll(x) (__builtin_ctzll((x)))
/* count leading zeroes */
#define clz(x) (__builtin_clz((x)))
#define clzll(x) (__builtin_clzll((x)))

/* floor log2 */
static inline uint32_t ilog2(uint32_t x)
{
return (x) == 0u ? 0u : (32u - clz(x) - 1u);
}
static inline uint32_t ilog2ll(uint64_t x)
{
return (x) == 0ull ? 0u : (64u - clzll(x) - 1u);
}

/* checked arithmetic intrinsics
* these return true if x op y causes overflow */
Expand Down
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