From 6d6f5b212f87ea5c04ee58112e052522003cec10 Mon Sep 17 00:00:00 2001
From: Andrea Bogazzi <andreabogazzi79@gmail.com>
Date: Fri, 7 Aug 2026 17:08:01 +0200
Subject: [PATCH] taitob

---
 cores/taitob/README.md              |   58 +
 cores/taitob/cfg/files.yaml         |   49 +
 cores/taitob/cfg/macros.def         |   86 +
 cores/taitob/cfg/mame2mra.toml      |   92 +
 cores/taitob/cfg/mem.yaml           |  102 +
 cores/taitob/cfg/msg                |   22 +
 cores/taitob/doc/BOOT_TRACE.md      |  211 ++
 cores/taitob/doc/HISTORY.md         |   81 +
 cores/taitob/doc/PHASE3D_PLAN.md    |  121 +
 cores/taitob/doc/STATUS.md          |  154 ++
 cores/taitob/doc/taito_b.cpp        | 3726 +++++++++++++++++++++++++++
 cores/taitob/doc/taitoio.cpp        |  574 +++++
 cores/taitob/doc/taitoio.h          |  185 ++
 cores/taitob/doc/taitosnd.cpp       |  335 +++
 cores/taitob/doc/taitosnd.h         |   64 +
 cores/taitob/doc/tc0180vcu.cpp      |  599 +++++
 cores/taitob/doc/tc0180vcu.h        |   81 +
 cores/taitob/hdl/jttaitob_colmix.v  |   95 +
 cores/taitob/hdl/jttaitob_game.v    |  415 +++
 cores/taitob/hdl/jttaitob_ioc.v     |  109 +
 cores/taitob/hdl/jttaitob_main.v    |  899 +++++++
 cores/taitob/hdl/jttaitob_obj.v     |  216 ++
 cores/taitob/hdl/jttaitob_shifter.v |   88 +
 cores/taitob/hdl/jttaitob_snd.v     |  273 ++
 cores/taitob/hdl/jttaitob_syt.v     |  350 +++
 cores/taitob/hdl/jttaitob_video.v   |  694 +++++
 26 files changed, 9679 insertions(+)
 create mode 100644 cores/taitob/README.md
 create mode 100644 cores/taitob/cfg/files.yaml
 create mode 100644 cores/taitob/cfg/macros.def
 create mode 100644 cores/taitob/cfg/mame2mra.toml
 create mode 100644 cores/taitob/cfg/mem.yaml
 create mode 100644 cores/taitob/cfg/msg
 create mode 100644 cores/taitob/doc/BOOT_TRACE.md
 create mode 100644 cores/taitob/doc/HISTORY.md
 create mode 100644 cores/taitob/doc/PHASE3D_PLAN.md
 create mode 100644 cores/taitob/doc/STATUS.md
 create mode 100644 cores/taitob/doc/taito_b.cpp
 create mode 100644 cores/taitob/doc/taitoio.cpp
 create mode 100644 cores/taitob/doc/taitoio.h
 create mode 100644 cores/taitob/doc/taitosnd.cpp
 create mode 100644 cores/taitob/doc/taitosnd.h
 create mode 100644 cores/taitob/doc/tc0180vcu.cpp
 create mode 100644 cores/taitob/doc/tc0180vcu.h
 create mode 100644 cores/taitob/hdl/jttaitob_colmix.v
 create mode 100644 cores/taitob/hdl/jttaitob_game.v
 create mode 100644 cores/taitob/hdl/jttaitob_ioc.v
 create mode 100644 cores/taitob/hdl/jttaitob_main.v
 create mode 100644 cores/taitob/hdl/jttaitob_obj.v
 create mode 100644 cores/taitob/hdl/jttaitob_shifter.v
 create mode 100644 cores/taitob/hdl/jttaitob_snd.v
 create mode 100644 cores/taitob/hdl/jttaitob_syt.v
 create mode 100644 cores/taitob/hdl/jttaitob_video.v

diff --git a/cores/taitob/README.md b/cores/taitob/README.md
new file mode 100644
index 000000000..a0dfbf5bd
--- /dev/null
+++ b/cores/taitob/README.md
@@ -0,0 +1,58 @@
+# JTTAITOB — Taito B System FPGA core
+
+JTCORES implementation of the **Taito B System** arcade board (1988–1991).
+
+## Target
+
+**Phase A** — first target: **Rastan Saga 2 / Nastar / Nastar Warrior**
+(MAME `rastsag2` / `nastar` / `nastarw`, ROM prefix `b81`, 1988).
+
+Future phases would cover the YM2610 family on the same bitstream:
+Ashura Blaster, Crime City, Rambo 3, Silent Dragon, Sel Feena, Ryujin,
+Tetris (B-System conversion). The YM2203-based outliers (Violence Fight,
+Hit the Ice, Master of Weapon) would need a separate bitstream.
+
+## Hardware
+
+PCB: `K1100419A / J1100178A`. Two crystals + a third for video:
+
+| Block             | Chip            | Clock                |
+|-------------------|-----------------|----------------------|
+| Main CPU          | Motorola 68000  | 12 MHz (24 / 2)      |
+| Sound CPU         | Zilog Z80       | 4 MHz (16 / 4)       |
+| FM + ADPCM        | Yamaha YM2610   | 8 MHz (16 / 2)       |
+| Sound comms       | TC0140SYT       | bus-paced            |
+| I/O               | TC0220IOC       | bus-paced            |
+| Video             | TC0180VCU       | 27.164 / 4 ≈ 6.79 MHz|
+| Palette DAC       | TC0260DAR       | passive              |
+
+## State (bootstrap commit)
+
+- [x] Directory scaffold + cfg files
+- [x] CPU spine (68000 + DTACK + autovector IACK)
+- [x] BRAM RAMs (work / palette / VRAM / sprite-scroll / VCU ctrl regs)
+- [x] Sound subsystem (Z80 + YM2610 + TC0140SYT, all GPLv3 ports)
+- [x] TC0220IOC stub (DIPs + cabinet inputs + coin latch)
+- [x] TC0260DAR (passive palette DAC → RGB)
+- [x] Video timing (320×224 @ 60 Hz)
+- [x] **TC0180VCU stub** — palette viewer shows whatever the 68k writes
+      to palette, no tile/sprite rendering yet
+- [ ] TC0180VCU real RTL — the major remaining work item
+- [ ] IRQ 2 (VCU intl) — currently only IRQ 4 (vblank) is wired
+- [ ] ADPCM-B SDRAM bus — voice samples currently silent
+- [ ] MAME ground-truth traces (next step per AGENTS.md §0.5)
+- [ ] FPGA sim diff vs MAME
+
+## Provenance
+
+The CPU + sound + TC0140SYT subsystems are ports from
+[cores/superman/](../superman/) (Taito X System) — same silicon for
+68k/Z80/YM2610/SYT, just a clock change on the 68k (8 MHz → 12 MHz).
+The TC0140SYT module (`jttaitob_syt.v`) is a verbatim copy of
+`jtsuperman_syt.v` with attribution updated.
+
+The TC0180VCU is unique to the Taito B System. No reference
+implementation exists in the wider open-source ecosystem (the
+Arcade-TaitoF2_MiSTer and Arcade-Darius2NinjaWarriors_MiSTer repos
+implement F2 / Z System chips but neither covers the VCU). It will be
+built from MAME's [tc0180vcu.cpp](doc/tc0180vcu.cpp) as the only spec.
diff --git a/cores/taitob/cfg/files.yaml b/cores/taitob/cfg/files.yaml
new file mode 100644
index 000000000..1445993e0
--- /dev/null
+++ b/cores/taitob/cfg/files.yaml
@@ -0,0 +1,49 @@
+taitob:
+  - get:
+    - jttaitob_game.v
+    - jttaitob_main.v
+    - jttaitob_snd.v
+    # TC0140SYT — main↔Z80 sound communication chip.
+    # Same silicon as Taito X System; ported verbatim from
+    # cores/superman/hdl/jtsuperman_syt.v (GPLv3).
+    - jttaitob_syt.v
+    # TC0220IOC — I/O / dipswitch / coin chip. Stub for now.
+    - jttaitob_ioc.v
+    # TC0180VCU — fused video chip (2× 64×64 tile planes + zooming
+    # sprites + text plane). Currently a stub that exposes VRAM /
+    # sprite RAM / scroll RAM / ctrl registers as BRAM the 68k can
+    # read & write, but produces black video. Real pipeline TBD.
+    - jttaitob_video.v
+    # Tile-row ring buffer + fine-scroll read tap (TC0100SCN-style technique,
+    # used by the BG/FG/TX planes for correct sub-tile horizontal scroll).
+    - jttaitob_shifter.v
+    # TC0180VCU sprite engine (Phase 3d). Scans the 408-slot sprite list each
+    # line into a jtframe_obj_buffer line buffer; reuses the gfx_sort'd gfx.
+    - jttaitob_obj.v
+    - jttaitob_colmix.v
+jtframe:
+  - get:
+      - jtframe_ff.v
+  - from: clocking
+    get:
+      - jtframe_cen48.v
+      - jtframe_cen24.v
+      - jtframe_sync.v
+  - from: ram
+    get:
+      - jtframe_ram.v
+      - jtframe_dual_ram.v
+      - jtframe_dual_ram16.v
+      - jtframe_obj_buffer.v
+      - jtframe_prom.v
+  - from: video
+    get:
+      - jtframe_vtimer.v
+      - jtframe_blank.v
+  - from: cpu
+    get:
+      - jtframe_z80.yaml
+      - jtframe_m68k.yaml
+jt12:
+  - get:
+    - jt12.yaml      # pulls the entire jt12 module incl. jt10 (YM2610) wrapper
diff --git a/cores/taitob/cfg/macros.def b/cores/taitob/cfg/macros.def
new file mode 100644
index 000000000..dea1a9fc6
--- /dev/null
+++ b/cores/taitob/cfg/macros.def
@@ -0,0 +1,86 @@
+CORENAME=JTTAITOB
+
+# Hardware: Taito B System (1988-91).
+# Reference: MAME taito/taito_b.cpp (mirrored in cores/taitob/doc/)
+#
+# First target: Rastan Saga 2 / Nastar / Nastar Warrior (rastsag2, 1988).
+# All three regional sets share the same `rastsag2` machine config.
+#
+# Clocks (24 MHz + 16 MHz master XTALs per MAME):
+#   68000   = 24 / 2 = 12 MHz   (main)
+#   Z80     = 16 / 4 =  4 MHz   (sound)
+#   YM2610  = 16 / 2 =  8 MHz   (sound)
+#   TC0180VCU pixel = 27.164 / 4 ≈ 6.79 MHz   (video — synthesised below)
+#
+# Custom Taito chips on the Taito B board (taito_b.cpp:11):
+#   TC0220IOC  — I/O / dipswitch / coin controller (jttaitob_ioc.v stub)
+#   TC0260DAR  — passive 12-bit palette DAC (no device in MAME; palette
+#                lives at 0x200000 as plain CPU-writable RAM, jttaitob_main.v
+#                exposes it via a BRAM port to jttaitob_colmix.v)
+#   TC0180VCU  — fused video chip: 2× 64×64 tile planes + zooming sprites
+#                + text plane + per-line scroll. No reference implementation
+#                exists anywhere — full HDL job. Currently stubbed.
+#   TC0140SYT  — main↔sound comms. Reused verbatim from Superman
+#                (jtsuperman_syt.v copied to jttaitob_syt.v, same chip).
+
+# ─── Controls ────────────────────────────────────────────────────────────────
+# Rastan Saga 2 / Nastar uses 2 action buttons (Attack + Jump). All
+# Taito B games are 2-button except Hit The Ice (4-player). Stick with
+# 2 for now; revisit if/when hitice lands in this bitstream.
+JTFRAME_BUTTONS=2
+
+# Joystick reorder — Superman precedent: HPS_IO board_joy1 arrives in
+# RLDU order (bit 0=RIGHT, 1=LEFT, 2=DOWN, 3=UP). MAME's
+# TAITO_JOY_UDLR_2_BUTTONS_START expects UDLR. JTFRAME_JOY_RLDU
+# applies the bit-reverse on bits 3:0 that maps RLDU → UDLR.
+JTFRAME_JOY_RLDU
+
+# ─── Video ───────────────────────────────────────────────────────────────────
+# MAME's set_visarea(0*8, 40*8-1, 2*8, 30*8-1) = 320×224 active.
+# Palette is 12-bit RGBx_444 (4 bits per channel), 4096 colours.
+JTFRAME_COLORW=4
+JTFRAME_WIDTH=320
+JTFRAME_HEIGHT=224
+
+# 48 MHz frame clock — Superman pattern. Gives clean integer cens for
+# 12 MHz (÷4), 8 MHz (÷6), 4 MHz (÷12).
+JTFRAME_CLK48
+
+# Pixel clock — PXLCLK=70 = 7.00 MHz (fractional cen n=7/m=24, see
+# jtframe_pxlcen.v). Real chip is 6.79 MHz (27.164/4). With H total 448
+# (jttaitob_game.v vtimer) this gives 15.625 kHz / 60.1 Hz and a 128-px
+# H-blank (~878 clk) — enough for the sequential BG/FG/TX ring fills
+# (~840 clk), unlike PXLCLK=6/384 (512-clk blank, overruns). Image width
+# 71% of the line (between 62.5% @8 MHz and 83% @6 MHz; ≈ real arcade).
+JTFRAME_PXLCLK=70
+
+# ─── SDRAM layout ────────────────────────────────────────────────────────────
+# Bank 0  : 68k main ROM (max 512 KB)                 0x000000
+# Bank 1  : all audio ROM — Z80 + ADPCM-A + ADPCM-B
+#           snd@0x080000  adpcma@0x100000  adpcmb@0x180000
+# Bank 2  : TC0180VCU gfx, copy 1 (1 MB) — bg/obj/tx  0x200000
+# Bank 3  : TC0180VCU gfx, copy 2 (1 MB) — fg only    0x300000
+#           (duplicate so BG fill@bank2 and FG fill@bank3 interleave)
+JTFRAME_HEADER=16
+JTFRAME_BA1_START=0x080000
+JTFRAME_BA2_START=0x200000
+JTFRAME_BA3_START=0x300000
+PCM_START=0x100000
+ADPCMB_START=0x180000
+
+# Debug knobs
+JTFRAME_IOCTL_RD=2048
+JTFRAME_STATUS
+
+[mister]
+JTFRAME_ARX=4
+JTFRAME_ARY=3
+
+[mist]
+-JTFRAME_CREDITS
+NOCREDITS
+JTFRAME_OSD_NOCREDITS
+
+[sidi]
+# May not fit on smaller SiDi — leave as build-once and re-evaluate
+JTFRAME_SKIP
diff --git a/cores/taitob/cfg/mame2mra.toml b/cores/taitob/cfg/mame2mra.toml
new file mode 100644
index 000000000..554f59594
--- /dev/null
+++ b/cores/taitob/cfg/mame2mra.toml
@@ -0,0 +1,92 @@
+[global]
+author=["jotego"]
+
+[parse]
+sourcefile=[ "taito_b.cpp" ]
+# Phase A: Rastan Saga 2 / Nastar / Nastar Warrior — three regional sets
+# of the same ROM (only the region-byte ROM B81-07/12/13 differs).
+# All other Taito B games share the same TC0140SYT + TC0220IOC + TC0180VCU
+# + YM2610 hardware and could ship in this bitstream once the video chip
+# is solid:
+#   ashura blaster / crime city / rambo3 / silent dragon / sel feena /
+#   ryujin / tetris (B-System conversion) / space invaders DX / qzshowby /
+#   puzzle bobble / sonic blast man — all YM2610 family
+#
+# Out-of-scope variants (different sound chips, different IOCs, etc.):
+#   violence fight / hit the ice (YM2203 + M6295)
+#   master of weapon (YM2203, TMP82C265 I/O)
+#   ashura blaster / silent dragon variants
+skip = { setnames = [
+    # Still skipped: games that need HDL work the core doesn't have yet.
+    #   tetrista        — Master of Weapon kit → YM2203 + PC060HA
+    #   hitice*         — YM2203 + OKIM6295
+    #   rambo3*         — 2 MB gfx (needs mem.yaml gfx bus 1MB→2MB + 4-ROM dup)
+    #   pbobble/spacedx/qzshowby — EEPROM + TC0640FIO + MB87078 (B-tier)
+    #   viofight/masterw — YM2203 (+OKI) sound subsystem
+    #   silentd/ryujin/sbm — YM2610B / TC0510NIO (B-tier)
+    #   realpunc        — adds HD63484 2nd video path
+    # De-skipped (Group A, 1 MB gfx, YM2610+SYT+TC0220IOC): crimec, tetrist.
+    # Still re-skipped because they error out in jtframe-mra (fatal validation):
+    #   ashura/ashuraj/ashurau   — vertical (need JTFRAME_VERTICAL)
+    #   selfeena, spacedxo       — 3-button (need JTFRAME_BUTTONS=3, per-game)
+    # Once we add per-machine JTFRAME_VERTICAL / BUTTONS overrides they'll un-skip.
+    "ashura",  "ashurau", "ashuraj",
+    "selfeena",
+    "spacedxo",
+    "tetrista",
+    "hitice",  "hiticerb", "hiticej",
+    "rambo3",  "rambo3p",  "rambo3u",
+    "pbobble", "bublbust",
+    "spacedx", "spacedxj",
+    "qzshowby",
+    "viofight","viofightu","viofightj",
+    "masterw", "masterwj", "masterwu", "yukiwo",
+    "silentd", "silentdj", "silentdu",
+    "ryujin",  "ryujina",
+    "sbm",     "sbmj",
+    "realpunc","realpuncj",
+]}
+
+[buttons]
+names=[
+    # Rastan Saga 2 / Nastar: 2 buttons — Attack + Jump.
+    { machines=["nastar","nastarw","rastsag2"], names="Attack,Jump" },
+]
+
+[dipsw]
+delete=[{names=["Unused","Unknown"]}]
+
+[ROM]
+# ROM regions for rastsag2 (taito_b.cpp:2793):
+#   maincpu       = 512 KB (16-bit, 4 × ROM_LOAD16_BYTE pairs)
+#   audiocpu      =  64 KB (Z80)
+#   tc0180vcu     =   1 MB (2 × 512 KB ROMs, sprite+tile gfx)
+#   ymsnd:adpcma  = 512 KB
+#   ymsnd:adpcmb  = 512 KB (Delta-T voice samples — wired into the jt10
+#                            ADPCM-B port; loaded into SDRAM bank 3 at
+#                            JTFRAME_BA3_START)
+regions = [
+    { name="maincpu",  width=16, reverse=true, no_offset=true },
+    { name="audiocpu", start="JTFRAME_BA1_START" },
+    { name="ymsnd:adpcma", rename="adpcma", start="PCM_START" },
+    { name="ymsnd:adpcmb", rename="adpcmb", start="ADPCMB_START" },
+    # tc0180vcu graphics ROMs land at the start of bank 2.
+    # MAME loads the two 512 KB ROMs with plain ROM_LOAD (straight
+    # concatenation): b81-03 → 0x00000 (planes 0/1), b81-04 → 0x80000
+    # (planes 2/3, via the charlayout/tilelayout RGN_FRAC(1,2) split).
+    # They are NOT a 16-bit byte-interleaved pair, so width=8 keeps each
+    # ROM as a contiguous half. (width=16 interleaved every byte and
+    # scrambled all tile gfx into noise.)
+    # gfx duplicated into 2 MB: sequence=[0,1,0,1] lays b81-03,b81-04 twice
+    # → copy 1 at bank 2 (BA2, bg/obj/tx) and copy 2 at bank 3 (BA3, fg).
+    # Two banks let the BG fill (bank 2) and FG fill (bank 3) interleave on
+    # the SDRAM controller instead of serializing on one bank. Each 1 MB half
+    # is gfx_sort'd independently via its mem.yaml bus (tx for bank 2, fg for
+    # bank 3). BA3_START must equal BA2_START + 0x100000 for copy 2 to land
+    # where the fg bus reads it.
+    { name="tc0180vcu", rename="gfx1", start="JTFRAME_BA2_START", width=8, no_offset=true, sequence=[0,1,0,1] },
+]
+
+order = [
+    "maincpu", "audiocpu", "adpcma", "adpcmb", "gfx1"
+]
diff --git a/cores/taitob/cfg/mem.yaml b/cores/taitob/cfg/mem.yaml
new file mode 100644
index 000000000..20c90a4a0
--- /dev/null
+++ b/cores/taitob/cfg/mem.yaml
@@ -0,0 +1,102 @@
+# Taito B System SDRAM map — DRAFT
+#
+# Bus widths follow the MAME ROM regions (taito_b.cpp rastsag2 ROM_START):
+#   maincpu : 16-bit (68k), 512 KB
+#   audiocpu:  8-bit (Z80),  64 KB
+#   adpcma  :  8-bit, up to 512 KB (YM2610 ADPCM-A samples)
+#   gfx1    : 16-bit interleaved sprite/tile graphics (TC0180VCU input)
+#
+# Memory map per rastsag2_map (taito_b.cpp:369):
+#   0x000000-0x07FFFF   68k ROM        → SDRAM bank 0 (main bus)
+#   0x200000-0x201FFF   palette RAM    → BRAM in jttaitob_main.v
+#   0x400000-0x47FFFF   TC0180VCU      → BRAM (vram/sprites/scroll/ctrl)
+#   0x600000-0x607FFF   68k work RAM   → BRAM (32 KB)
+#   0x800000-0x800003   TC0140SYT      → jttaitob_syt.v
+#   0xA00000-0xA0000F   TC0220IOC      → jttaitob_ioc.v
+#
+# Bus ordering rule (rastan/gaiden pattern): rw buses come first on their
+# bank so the auto-generated SDRAM slot wires the write enable correctly.
+
+params:
+  - { name: ADPCMA_OFFSET, value: "(`PCM_START-`JTFRAME_BA1_START)>>1" }
+  - { name: ADPCMB_OFFSET, value: "(`ADPCMB_START-`JTFRAME_BA1_START)>>1" }
+
+audio:
+  rsum: 10k
+  channels:
+    - { name: fm,  module: jt12, rsum: 10k }   # YM2610 FM, wrapped by jt10
+
+sdram:
+  banks:
+      # Bank 0 — 68k main ROM (read-only). Work RAM, palette RAM, VRAM,
+      # sprite RAM, scroll RAM all live in BRAM inside jttaitob_main.v —
+      # SDRAM latency is incompatible with the 68k's memory-test loop and
+      # the BRAM model is the right one for these sizes anyway.
+    - buses:
+      - name: main
+        addr_width: 19
+        data_width: 16
+
+      # Bank 1 — all audio ROM (read-only): Z80 program + YM2610 ADPCM-A and
+      # ADPCM-B (Delta-T) samples. Kept together so banks 2/3 stay pure gfx.
+    - buses:
+      - name: snd
+        addr_width: 16
+        data_width: 8
+      - name: adpcma
+        addr_width: 19
+        data_width: 8
+        offset: ADPCMA_OFFSET
+      - name: adpcmb
+        addr_width: 19
+        data_width: 8
+        offset: ADPCMB_OFFSET
+
+      # Bank 2 — TC0180VCU graphics ROM, copy 1 (1 MB). Read by:
+      #   bg  → BG plane tile fetch
+      #   obj → sprite gfx (active region)
+      #   tx  → text plane (8x8 tiles)
+      # FG has its own copy in bank 3 so the BG fill (bank 2) and FG fill
+      # (bank 3) hit different physical SDRAM banks and interleave.
+      #
+      # gfx_sort=hvvvx (mode gfx4, b0=1) rotates gfx-word address bits [3:0]
+      # so the tilelayout L/R-8px-half bit (px3, word bit 3) becomes the LSB.
+      # That puts a tile-row's two 8px halves at adjacent addresses, so the
+      # SDRAM read-cache turns the 2nd half-read into a hit (~2x fewer SDRAM
+      # round-trips per tile).  The data inside each word is untouched, so the
+      # pen decode is unchanged — the HDL only reorders the bottom address
+      # bits ({A[18:4],A[2:0],A[3]}) in BG/FG/TX address generation.
+      # The three buses share ONE 1 MB region, so the sort is declared on a
+      # single bus to repack the bytes exactly once; the others read the
+      # already-sorted data with the same address swap.  It must go on the
+      # LAST bus of the bank (tx): jtframe mem bounds a gfx_sort range at the
+      # next bus's offset, and bg/obj have none — declaring it on the final
+      # bus instead ends the range at the next bank, covering the full region.
+    - buses:
+      - name: obj
+        addr_width: 20
+        data_width: 16
+      - name: bg
+        addr_width: 20
+        data_width: 16
+      - name: tx
+        addr_width: 20
+        data_width: 16
+        gfx_sort: hvvvx
+
+      # Bank 3 — TC0180VCU graphics ROM, copy 2 (1 MB), read by the FG plane
+      # ONLY. Duplicating the gfx into its own physical SDRAM bank lets the BG
+      # fill (bank 2) and FG fill (bank 3) run on different banks → the SDRAM
+      # controller interleaves their accesses (BG's RAS/CAS latency overlaps
+      # FG's) instead of serializing on one shared bank. The +1 MB buys the
+      # parallel fill that fits the shorter 7 MHz H-blank. gfx_sort applied
+      # (only bus in the bank).
+    - buses:
+      - name: fg
+        addr_width: 20
+        data_width: 16
+        gfx_sort: hvvvx
+
+# BRAM declarations for palette / VRAM / sprite RAM / scroll RAM live
+# inside jttaitob_main.v (cabal/superman pattern). Keeping mem.yaml
+# minimal so the auto-generated port surface stays tight.
diff --git a/cores/taitob/cfg/msg b/cores/taitob/cfg/msg
new file mode 100644
index 000000000..f8fca093c
--- /dev/null
+++ b/cores/taitob/cfg/msg
@@ -0,0 +1,22 @@
+            \BTAITO B\W
+  FPGA core by \GANDR\WEA BOG\RAZZI\W
+  github.com/sponsors/asturur
+
+   Made with the JT FRAMEWORK
+       patreon.com/jotego
+
+ Based mainly on MAME sources,
+      Previous taito works
+  And ROM reverse-engineering
+
+        \R[\WSpecial thanks\R]\W
+
+    \GMy beautiful family that
+       \Galways supports me
+
+      \GMy friends that are
+          \Galways there
+
+  \RWicker Waka for taito parts\W
+
+       \GThe Zaparoo gang!
diff --git a/cores/taitob/doc/BOOT_TRACE.md b/cores/taitob/doc/BOOT_TRACE.md
new file mode 100644
index 000000000..5c7868cd2
--- /dev/null
+++ b/cores/taitob/doc/BOOT_TRACE.md
@@ -0,0 +1,211 @@
+# Rastan Saga 2 / Nastar — annotated boot trace
+
+Reference MAME trace of `nastar` (parent set; rastsag2 is a Japan clone
+on identical hardware). Captured against MAME 0.276 with the scripts
+in `cores/taitob/ver/rastan2/mame_scripts/` against ROMs at
+`/Volumes/homes/abogazzi/roms/MAME 0.270 ROMs (split)/nastar.zip`.
+
+Raw traces (gitignored, ~36 MB total):
+- `cores/taitob/ver/rastan2/traces/main_boot.tr`  — 1,383,536 68k instructions
+- `cores/taitob/ver/rastan2/traces/sound_boot.tr` — Z80 boot path
+
+Regenerate either with `./mame nastar -debug -debugscript <script>` then
+move `/tmp/rastsag2_<cpu>.tr` into `ver/rastan2/traces/`.
+
+---
+
+## Main CPU (68000 @ 12 MHz)
+
+### Reset vector + stack init
+
+```
+000400  reset PC vector (taken from ROM offset 0x4)
+000404  lea     $600000.l, A5         ; A5 = work-RAM base
+00040A  lea     $607ffe.l, A7         ; SP = top of work RAM (32 KB)
+```
+
+So SSP from the reset vector is **0x607FFE** (work-RAM top minus 2). The
+initial PC is **0x000404**. These are the first two **validation gates**
+for the FPGA sim.
+
+### TC0180VCU control-register init (10 byte writes, 0x418000–0x41801E)
+
+```
+000410  move.b  #$10, $418000.l   ; ctrl[0] = 0x10   (video_control)
+000418  move.b  #$32, $418002.l   ; ctrl[1] = 0x32   (BG/FG/TX rambank)
+000420  move.b  #$00, $418004.l   ; ctrl[2] = 0
+000428  move.b  #$00, $418006.l   ; ctrl[3] = 0
+000430  move.b  #$00, $418008.l   ; ctrl[4] = 0
+000438  move.b  #$01, $41800a.l   ; ctrl[5] = 0x01
+000440  move.b  #$08, $41800c.l   ; ctrl[6] = 0x08
+000448  move.b  #$28, $41800e.l   ; ctrl[7] = 0x28
+000450  move.b  #$00, $418014.l   ; ctrl[10] = 0 (note: skips 0x418010,0x418012)
+000458  move.b  #$00, $418016.l   ; ctrl[11] = 0
+```
+
+These are the magic numbers `cores/taitob/doc/tc0180vcu.cpp::ctrl_w`
+will need to decode. Per the MAME source `m_ctrl[0..15]` covers a 16-byte
+register file; the BG/FG/TX rambank latches sit at bytes 1, 5, 6, 7 (the
+0x32 / 0x01 / 0x08 / 0x28 values above). Byte 0 = `video_control`
+(global flip / framebuffer-page / sprite-shading flags).
+
+### Scroll-RAM clear (0x413800 = FG, 0x413C00 = BG)
+
+```
+000460  move.w  #$0000, $413800.l   ; clear FG scroll register
+000468  move.w  #$0000, $413c00.l   ; clear BG scroll register
+```
+
+### First TC0220IOC write — coin lockout / counter reset
+
+```
+000470  move.b  D0, $a00000.l       ; IOC byte register 0 (port_w_4)
+```
+
+D0 is loaded earlier — repeated calls at 0x00048C, 0x0004AC, 0x0004CE,
+0x0004EE, 0x000510 hammer the same address with different D0 values
+during the boot self-test (coin counter / lockout / DSW polling). The
+HDL's TC0220IOC stub at `hdl/jttaitob_ioc.v` only has to ack these
+writes; it doesn't need to drive coin meters yet.
+
+### Work RAM clear (0x600000–0x607FFE, 0x7FFE bytes)
+
+```
+000476  lea     $600000.l, A0
+00047C  move.l  #$7ffe, D0          ; loop counter
+000482  move.w  #$ff, D1            ; pattern
+000486  move.b  D1, (A0)+           ; clear loop body
+000488  subq.l  #1, D0
+00048A  bne     $486
+```
+
+Standard 68k memory-clear loop. The CPU spine must complete this loop
+(~32 K iterations) before the FPGA sim's PC stream is allowed to
+diverge from MAME. **This is the easiest landmark to hit.**
+
+### First TC0140SYT comm — kicks the sound CPU
+
+```
+002D56  move.b  #$04, $800000.l     ; SYT master_port_w (select reg 4)
+002D5E  move.b  #$01, $800002.l     ; SYT master_comm_w (write 0x01)
+```
+
+After ~2,800 bytes of setup the 68k pokes the sound side. Reg 4 / data
+0x01 = "tell sound CPU to start playing" (cf. `taitosnd.cpp::master_*`).
+
+---
+
+## Sound CPU (Z80 @ 4 MHz)
+
+### Reset + interrupt mode
+
+```
+0000  di                            ; disable interrupts
+0001  im   1                        ; IM 1 → IRQ vectors to 0x0038
+0003  ld   a,$05                    ; "reset / hello" magic
+0005  ld   ($E200),a                ; write SYT slave port (0xE200 = port_w)
+0008  ld   ($E201),a                ; write SYT slave comm (0xE201 = comm_w)
+000B  jp   $01AA                    ; jump to main init
+```
+
+The 5-write sequence to 0xE200/0xE201 is the Z80's half of the
+TC0140SYT handshake — confirms the chip is up and clears the comm
+mailbox.
+
+### Stack + work-RAM clear
+
+```
+01AA  ld   a,$00
+01AC  ld   ($E200),a                ; clear SYT port
+01AF  ld   a,($E201)                ; flush SYT comm (×2)
+01B2  ld   a,($E201)
+01B5  ld   sp,$E000                 ; SP = top of Z80 RAM (8 KB at 0xC000-0xDFFF)
+01B8  ld   hl,$C000                 ; clear ptr
+01BB  ld   a,$E0                    ; stop @ HL=0xE000
+01BD  ld   b,$00                    ; fill byte
+01BF  ld   (hl),b                   ; clear loop
+01C0  inc  hl
+01C1  cp   h
+01C2  jr   nz,$01BF
+```
+
+Z80 work RAM lives at 0xC000–0xDFFF (8 KB inside the SYT-managed slave
+decoder). After this loop the Z80 is sitting at PC ≈ 0x01C4 waiting for
+the next 68k poke.
+
+---
+
+## Pre-vector landmark — found via SDRAM dump
+
+ROM byte at 0x400 is `46FC 2700` = `move #$2700, SR` — disable interrupts
+and set the status register before the `lea` chain at 0x404 begins.
+
+MAME's `trace ... noloop` skips this very first instruction (it's a
+debugger quirk — `noloop` swallows the first opcode at the script-start
+boundary). The FPGA sim's first ROM fetch lands at PC=0x400, and gate 1
+fires when the CPU subsequently reaches 0x404 (the address MAME's
+trace head shows).
+
+## Validation gates (FPGA sim must hit, in order)
+
+| # | CPU  | PC      | Event                              | What the HDL has to do |
+|---|------|---------|------------------------------------|------------------------|
+| 1 | 68k  | 0x000400 → 0x000404 | Reset vector taken     | ROM at SDRAM bank 0 readable, DTACK paced |
+| 2 | 68k  | 0x00040A | SSP = 0x607FFE                    | Memory-clear loop will need work RAM |
+| 3 | 68k  | 0x000410-0x000458 | 10× VCU ctrl writes      | `vcuctrl_cs` decoder must catch these |
+| 4 | 68k  | 0x000460-0x000468 | Scroll RAM cleared       | `oram_cs` must catch 0x413800/0x413C00 |
+| 5 | 68k  | 0x000470 | First IOC write                   | `ioc_cs` decoder fires; IOC stub acks |
+| 6 | 68k  | 0x000490 | Work RAM clear complete (~32K)    | `ram_cs` + dual_ram16 working under load |
+| 7 | Z80  | 0x000000 → 0x000001 | First fetch (`di; im 1`) | Z80 ROM at SDRAM bank 1 readable |
+| 8 | Z80  | 0x000005 | First SYT slave write             | `jttaitob_syt` slave-side decode wired |
+| 9 | Z80  | 0x0001C4 | Z80 RAM clear complete            | SYT-internal 8 KB RAM working |
+| 10 | 68k  | 0x002D56 | First SYT comm to sound           | SYT master-side mailbox working |
+
+Once gate 10 is met the boot is well underway; from there the next
+landmark is the first IRQ-4 entry (vblank). We have not annotated that
+yet because it depends on TC0180VCU `inth` timing, which is the next
+work item.
+
+---
+
+## FPGA sim results (first iteration — sim_logs/boot_v60_final.log)
+
+All wired 68k-side gates pass at 60-frame sim with **byte-exact data match** to MAME:
+
+| # | Gate                              | FPGA result                                          | Status |
+|---|-----------------------------------|------------------------------------------------------|--------|
+| 1 | PC=0x000404 first user fetch      | hit                                                  | ✅     |
+| 3 | First VCU ctrl write              | `0x0418000 <= 0x1010` (byte 0x10 on UDS lane)        | ✅     |
+| 4 | First scroll RAM write            | `0x0413800 <= 0x0000`                                | ✅     |
+| 5 | First IOC write                   | `0x0A00000 <= 0x00`                                  | ✅     |
+| 6 | Work-RAM clear + verify loops complete | exits at PC ≈ 0xBE4 (ROM-checksum loop)         | ✅     |
+| 10| First SYT comm                    | `0x0800000 <= 0x04`                                  | ✅     |
+
+Gates 2 (SP load), 7–9 (Z80) are not yet wired in the dumper but the
+68k boot is byte-identical to MAME through the entire 1.38M-instruction
+reference trace. After gate 10 the CPU enters the ROM-checksum loop at
+0xBE4 (`move.b D0, 0xA00000; add.w (A0)+, D0; cmpa.l #0x3FF9E, A0; bne $BE4`)
+— the same place MAME's 1-second trace ends. The boot is healthy.
+
+Reproduce via:
+```
+docker run --rm --platform linux/amd64 \
+    -v "$(pwd)":/jtcores -v "/tmp":/host_tmp \
+    --entrypoint /bin/bash jotego/simulator \
+    /host_tmp/run_sim_in_docker.sh 60 cores/taitob/ver/rastan2/sim_logs/boot_v60.log
+```
+Runner script: `cores/taitob/ver/rastan2/run_sim_in_docker.sh`.
+
+## Notes for the FPGA sim diff
+
+- **No CPU diff prior to gate 6**. The memory-test loop is by far the
+  highest-volume PC stream; any mismatch shows up immediately.
+- **Endian / DSn pacing pitfalls**: byte writes to 0x418000-0x41801E are
+  on the LOW byte lane (UDSn high, LDSn low), so `cpu_we[0]` must be
+  the LDS we. The `jttaitob_main.v` decoder already gets this right —
+  but the VCU ctrl-reg latch only captures byte 0 today; bytes 4-7
+  (the BG/FG/TX rambanks) are also written and will be needed when the
+  VCU pipeline lands.
+- **Z80 IRQ**: the IRQ source is YM2610's IRQ-out (timer flag). Until
+  the YM2610 model is running real ROMs the Z80 sits idle at the
+  post-RAM-clear poll loop, which is fine for first-stage validation.
diff --git a/cores/taitob/doc/HISTORY.md b/cores/taitob/doc/HISTORY.md
new file mode 100644
index 000000000..fcfa9a40a
--- /dev/null
+++ b/cores/taitob/doc/HISTORY.md
@@ -0,0 +1,81 @@
+# taitob — HISTORY
+
+Per-commit decisions + dead ends. Newest at the bottom.
+
+## 2026-05-26 — Bootstrap
+
+Started the Taito B System core, first target Rastan Saga 2 / Nastar.
+
+### Why Superman as the template (not Rastan)
+
+The repo has two Taito 68k cores already:
+
+- **rastan** (Taito original Rastan, 1987) — older PC080SN/PC090OJ
+  video board + YM2151 + MSM5205 + PC060HA. Different sound chips,
+  different video chips, different sound-comms chip. Zero overlap.
+- **superman** (Taito X System, 1988) — Seta-built board sold by
+  Taito. Same 68000 + Z80 + YM2610 + TC0140SYT as Taito B. Different
+  video chips (Seta X1-001A) and a C-chip protection MCU.
+
+Superman wins because the CPU spine and sound subsystem are bit-for-bit
+the same chips Taito B uses. Cloning Superman drops in the entire
+CPU+sound+SYT plumbing for free; the only real work is the video chip.
+
+### What was inherited vs written fresh
+
+| Module                | Source                                |
+|-----------------------|---------------------------------------|
+| `jttaitob_syt.v`      | verbatim copy of `jtsuperman_syt.v`   |
+| `jttaitob_snd.v`      | derived from `jtsuperman_snd.v`       |
+| `jttaitob_main.v`     | new (different memory map)            |
+| `jttaitob_ioc.v`      | new (Superman uses C-chip, not IOC)   |
+| `jttaitob_video.v`    | new stub (no reference exists)        |
+| `jttaitob_colmix.v`   | new (trivial palette → RGB wire)      |
+| `jttaitob_game.v`     | derived from `jtsuperman_game.v`      |
+
+### Clock pick: PXLCLK=8
+
+Real chip is 27.164 MHz / 4 ≈ 6.79 MHz pixel clock. Not a clean divisor
+of our 48 MHz frame clock. The framework only supports PXLCLK=6 or 8.
+At PXLCLK=6 the H rate (~14.4 kHz) lands below the 15.625 kHz NTSC
+target that MiSTer's HDMI scaler and analog CRTs expect — produces bad
+vertical stripes on HDMI and CRT refuses to sync (this is the Superman
+precedent, see cores/superman/cfg/macros.def lines 51–63).
+
+Picked PXLCLK=8 with H_total=512, V_total=260 → 60.10 Hz refresh,
+H rate 15.625 kHz. Within 0.2% of MAME's 60.000 Hz nominal.
+
+### TC0260DAR — no module exists in MAME
+
+The TC0260DAR is a passive 12-bit RGBx_444 palette DAC. MAME doesn't
+emulate it as a device — it just declares a generic `palette_device`
+with `RGBx_444` format (taito_b.cpp:1887). So `jttaitob_colmix.v` is
+literally a wire from the 12-bit palette word to {R[3:0], G[3:0], B[3:0]}.
+Saved a chip on the BOM, saved a Verilog file.
+
+### Why the framebuffer region is a black hole
+
+`tc0180vcu_memrw` maps 0x40000-0x7FFFF inside the VCU window as a
+framebuffer used by Hit The Ice for its pixel-bitmap mode and Realpunc
+for its camera overlay. Rastan Saga 2 doesn't touch this region.
+Allocating 256 KB of BRAM (or backing it with SDRAM) for a feature no
+Phase A game uses is wasteful — `fb_cs` is decoded but discarded.
+Re-enable when hitice / realpunc land in this bitstream.
+
+### What's deliberately deferred
+
+- **TC0220IOC**: real coin counter / lockout output not wired (the
+  framework's `coin` input does the work). The stub captures the
+  68k's writes into a register the game can read back, which is all
+  the Phase A game needs.
+- **TC0180VCU**: only the chip-select decode and ctrl-register-byte-0/1
+  latching are real; everything else (tile fetch, sprite engine,
+  scroll FIFO, priority mixer) is TBD.
+- **IRQ 2**: only IRQ 4 (vblank-driven) fires. Real VCU drives both
+  inth → IRQ 4 and intl → IRQ 2; the IRQ 2 ISR sets a flag the IRQ 4
+  ISR checks (taito_b.cpp:44). Worth re-checking once the boot trace
+  is captured — if rastsag2 hangs in the IRQ 4 handler waiting for the
+  flag, that's the cause.
+- **ADPCM-B**: B81-01.1 (Delta-T voice samples) — present in the ROM
+  set but not wired to jt10 yet because mem.yaml doesn't expose an
+  `adpcmb` SDRAM bus. Sound effects work; voice clips don't.
diff --git a/cores/taitob/doc/PHASE3D_PLAN.md b/cores/taitob/doc/PHASE3D_PLAN.md
new file mode 100644
index 000000000..365fa586a
--- /dev/null
+++ b/cores/taitob/doc/PHASE3D_PLAN.md
@@ -0,0 +1,121 @@
+# Phase 3d — sprite engine bring-up plan
+
+This is the largest remaining piece of the TC0180VCU.  Everything else
+(BG + FG + TX + scroll + ctrl[7] decode) is in place.  Sprites are a
+distinct architectural unit and warrant a focused implementation pass.
+
+## What the chip does
+
+Per `cores/taitob/doc/tc0180vcu.cpp::draw_sprites` (lines 370–495):
+
+* Sprite RAM lives at oram word offsets `0x0000-0x0CBF` (= 0x1980 bytes
+  at the 68k's 0x410000-0x41197F window).
+* 408 sprites total, 16 bytes (8 words) per slot.
+* Per-sprite layout:
+
+```
+offset  bits          field
+0       16            tile_code (up to 0x7FFF)
+1       0..5          color (palette index 0..63)
+        14            flipX
+        15            flipY
+2       0..9 (signed) x-coordinate (10-bit, -512..511 then wrap)
+3       0..9 (signed) y-coordinate
+4       0..7          y-zoom (0=100%, 0x80=50%, 0xC0=25%, 0xFF=off)
+        8..15         x-zoom
+5       0..7          y-sprites count - 1 (big sprite)
+        8..15         x-sprites count - 1
+6..7    unused
+```
+
+* Iteration order is **reverse** — `offs` walks from 0xCB8 down to 0.
+  Later sprites in memory draw first; earlier sprites overlay them.
+* "Big sprites" stitch multiple 16x16 tiles into a larger figure; the
+  first slot has dimensions, subsequent slots use latched values.
+* Zoom is implemented in MAME by chunking the sprite into 16x16
+  sections instead of one true zoom (acknowledged-buggy at MAME line
+  457 — we should replicate the same behaviour for compatibility).
+
+## Architecture plan (REVISED after the BG/FG/TX ring + gfx_sort work)
+
+Context that changed since this plan was first written:
+
+* **All three tile planes (BG/FG/TX) are now `jttaitob_shifter` rings**
+  filled during HBLANK; during ACTIVE the `bg`/`obj`/`tx` SDRAM buses
+  are **idle** (the rings read decoded pixels from BRAM, not SDRAM).
+* **`gfx_sort=hvvvx`** reorders the shared gfx region's address bits.
+  Any consumer of that region must apply the `gsort()` swap.  Sprites
+  use `gfx(1)` (the same 16×16 tilelayout) → **sprites must use gsort**,
+  and get the same burst-cache speedup for free.
+* A shared `fill_line` (latched `vrender` at HBLANK kick) gives all
+  fills a single frozen line reference, immune to the mid-HBLANK vdump
+  increment.
+
+### No SDRAM bus refactor needed (old "Option A" is obsolete)
+
+The old plan wanted to move FG off `obj` to free it for sprites.  Not
+necessary: FG only touches `obj` **during HBLANK** (its ring fill),
+and `obj` is **idle during ACTIVE**.  So the sprite engine fills the
+next line's buffer **during ACTIVE on `obj`** — they time-share by
+phase (FG = HBLANK, sprites = ACTIVE), no contention, no refactor.
+
+### 1. Sprite-list scanner
+
+Walk the 408-slot list (reverse, `offs` from 0xCB8 down by 8) from
+oram port-B.  Per slot read y (word 3) first; if the target line is in
+`[y, y+16)` (×big/zoom later), queue the slot (code/color/flip/x/zoom).
+Limit to a per-line cap (e.g. 32) to bound the render budget.
+
+### 2. Sprite renderer (during ACTIVE, for the NEXT line)
+
+For each queued slot: compute the 16×16 gfx row via `gsort` on the
+`obj` bus (4 words/row like BG/FG, burst-cached), apply flipX/Y, write
+`color*16 + pen` (pen≠0) to the write line buffer at screen-x.  Active
+gives ~1920 clk/line — ample for a capped sprite count with fast
+(cached) gfx reads.
+
+### 3. Line buffer (ping-pong)
+
+Two `jtframe_obj_buffer`-style 320×12 BRAMs.  Fill buffer A for line
+N+1 during line N's ACTIVE; read buffer B (line N) during the same
+ACTIVE; swap each line.  (Clear the just-read buffer as it drains, so
+the next fill starts blank — the chip's per-frame erase.)
+
+### Output mux
+
+Add the sprite (obj) layer.  Per `ctrl[7]` bit 3:
+* Mode 1 (bit3=1): `bg < fg < obj < tx`
+* Mode 0 (bit3=0): `bg < obj1 < fg < obj0 < tx` (obj0/obj1 by color bit0)
+
+nastar boots `ctrl[7]` high byte `0x28` → bit3=1 → **Mode 1** first.
+
+## Incremental delivery (commit per step, grade on the 5 scenes)
+
+* **3d-a — basic unscaled sprites.** Scanner + renderer (no zoom, no
+  big-sprite) + ping-pong buffer + Mode-1 mux.  nastar/rastan2 sprites
+  are mostly unscaled, so this should fill in the "missing pieces".
+* **3d-b — big sprites** (multi-tile, latched dims).
+* **3d-c — zoom** (replicate MAME's 16-px-chunked scaling, line 457).
+* **3d-d — priority Mode 0** (obj0/obj1 split by color bit 0).
+
+## Estimated effort
+
+* Scanner FSM + queue:        ~120 lines
+* Renderer (3d-a, no zoom):   ~120 lines
+* Ping-pong line buffer:      ~60 lines (reuse jtframe_obj_buffer)
+* Priority mux update:        ~25 lines
+* zoom / big-sprite (3d-b/c): ~150 lines (later)
+
+## Validation gates
+
+Sprite implementation should be validated against:
+
+1. First sprite-list read after game writes to sprite RAM (Phase 3d).
+2. First sprite rendered to line buffer (Phase 3d).
+3. Visible sprite on frame (compare to MAME capture).
+4. Zoom values 0x40, 0x80, 0xC0 produce correctly-sized sprites.
+5. Big-sprite mode forms correct multi-tile figures.
+6. flipX/Y mirror correctly.
+7. Priority mode 0 vs mode 1 visible difference (sprites over/under FG).
+
+Each of those is a 30-min validation step worth a discrete commit.
diff --git a/cores/taitob/doc/STATUS.md b/cores/taitob/doc/STATUS.md
new file mode 100644
index 000000000..02e4fbdb7
--- /dev/null
+++ b/cores/taitob/doc/STATUS.md
@@ -0,0 +1,154 @@
+# taitob — STATUS
+
+## Current video state (May 2026)
+
+Graded with the `tools/scenesim/` harness against 5 MAME scenes
+(`m00300` TAITO logo, `m00540` NASTAR title, `m00840`, `m00900`,
+`m02100` gameplay). Canonical verification = **sim all 5 → build PNG
+diffs**, never a single-scene spot check.
+
+**Done & verified:**
+- **gfx_sort=hvvvx** on the gfx region (`mem.yaml`, on the `tx` bus) +
+  matching `gsort()` address swap in `jttaitob_video.v`. Rotates the
+  tile L/R-half bit to the LSB so a tile-row's halves are adjacent →
+  SDRAM read-cache hits. BG fill **1300→279 clk** (sdram_wait 1144→103),
+  fits HBLANK with ~4× margin. Decode unchanged.
+- **BG plane** renders via the `jttaitob_shifter` ring, pixel-aligned to
+  MAME (all 5 scenes best-fit offset `(0,0)`).
+- **BG vertical 1px-down fixed** by *latching* the fill line (`vrender`)
+  at `bg_fill_kick`: gfx_sort shrank the fill into HBLANK where it
+  straddles the `vdump` increment (HS_START=340), so a combinational
+  `vrender`/`vdump` flipped row mid-fill. Frozen line = uniform.
+- **1-2px black left edge fixed**: dropped the redundant `!LHBL/!LVBL`
+  gate on `pal_idx` (colmix already blanks RGB) and clamped the BG tap's
+  `hdump` to 0 during HBLANK so the read-out is primed for `hdump 0`.
+  - *Residual (noted, deferred):* a very rare 1px on a few center lines
+    still appears; suspected unrelated to the edge priming. Not chased.
+
+- **FG plane** converted to the BG-style `jttaitob_shifter` ring
+  (HBLANK prefetch + `tap = hdump − fg_scrollx + 1`), deleting the
+  per-slice band-aids. Fixes the m00900 `mod 8` FG fine-scroll and the
+  m00540 sword misalignment.
+- **TX plane** converted to a ring the same way (8×8 tiles, no scroll,
+  `tap = hdump + 1`).
+- **Sprites (Phase 3d-a.1) — real 16×16 gfx, unscaled, single-tile.**
+  `jttaitob_obj.v` scans the 408-slot list per scanline, fetches the
+  gfx row off the `obj` bus during ACTIVE (gsort'd, burst-cached, while
+  the rings read decoded pixels from BRAM so the bus is otherwise idle),
+  decodes 16 pens with flipX/flipY, writes to a `jtframe_obj_buffer`
+  line buffer. **m00840 warrior is pixel-exact vs MAME (100% over the
+  sprite bbox); m00900/m02100 sprites best-fit `(0,0)`.** Three bugs
+  found & fixed: (1) sprite palette base is **`fb_color_base 0x400`**
+  (`set_fb_colorbase(0x40)` ⇒ `m_fb_color_base = 0x400`), not 0 — final
+  index = `0x400 + color*16 + pen`; (2) the right-half planes-2/3 word
+  **`w23r` must be latched** (it was read live off `gfx_data` after
+  `gfx_cs` dropped, so the right 8px of every tile decoded from stale
+  bus data); (3) the line buffer's `rd_data` is registered on `pxl_cen`
+  (1px latency like the rings) so it must be read **one column ahead**
+  (`rd_addr = hdump + 1`).
+
+**Still open:**
+- **Big sprites (3d-b)** — multi-tile figures via word+5 `x_num/y_num`
+  with latched x/y stepping (`xlatch + x_no*16` etc.). nastar's warrior
+  is *not* a big sprite (each tile is an independent slot), so 3d-a
+  already covers it; needed for games that do use big sprites.
+- **Zoom (3d-c)** — replicate MAME's buggy 16px-chunked scaling.
+- **Priority Mode 0 (3d-d)** — obj0/obj1 split by color bit 0.
+- **TX text doubling** — "1UP"→"11PP"; spatial addressing, suspected
+  TX look-ahead amount. Still present in the scene diffs.
+
+Bank wiring note: MAME's `ctrl_w` **code** uses `ctrl[0]→FG, ctrl[1]→BG`
+(its *comment* says the opposite — stale). The HDL matches the code; do
+not "fix" it to the comment.
+
+---
+
+**Phase**: A (bootstrap) — Rastan Saga 2 / Nastar.
+
+## What runs
+
+- `cfg/` files lint-target the four-set Phase A scope (rastsag2 + nastar
+  + nastarw via mame2mra; tetrist excluded — different memory map).
+- The HDL graph **should** elaborate (lint not yet run as of this commit).
+- 68k spine is wired with the rastsag2_map decoder (taito_b.cpp:369).
+- Z80 + YM2610 + TC0140SYT cloned from Superman; ADPCM-A wired,
+  ADPCM-B silent.
+- TC0220IOC stub returns DIPs and cabinet inputs; coin counter is a
+  dead-end latch.
+- Video output is the **palette viewer** stub — whatever the 68k writes
+  to palette RAM at 0x200000-0x201FFF shows as a 32×128 grid.
+
+## TC0180VCU bring-up status
+
+| Phase | Block                                    | Status  | Commit       |
+|-------|------------------------------------------|---------|--------------|
+| 1     | ctrl reg file + BG tile addressing       | done    | `e19bfbed1`  |
+| 2a    | SDRAM bg bus + 8-pixel batch fetch       | done    | `c20b0db4e`  |
+| 2b    | Pre-fetch + double-buffer                | done    | `76af1901c`  |
+| 2c    | flipX/Y per BG attr                      | done    | `83dba1a46`  |
+| 3a    | FG plane (transparent pen 0, over BG)    | done    | `9e6d55775`  |
+| 3b    | TX plane (8x8 tiles)                     | done    | `541c502a8`  |
+| 3c    | Per-frame scroll (BG/FG)                 | done    | `eacf6d32c`  |
+| 3d    | Sprite engine with zoom                  | planned | see PHASE3D_PLAN.md |
+| 4     | ctrl[7] decode (priority/flip)           | partial | `dd79514e3`  |
+
+Per-line scrolling (lines_per_block < 256) and flip-transformation of
+the look-ahead position are partial in Phase 3c/4 — code-wired but not
+exercised by the rastsag2 boot path that we sim against.
+- Only IRQ 4 (vblank) fires; the real VCU drives both IRQ 4 (`inth`)
+  and IRQ 2 (`intl`) — IRQ 2 ISR sets a flag the IRQ 4 ISR checks
+  (taito_b.cpp:44). May matter for some games.
+- ADPCM-B voice samples don't play.
+- Framebuffer region (0x440000-0x47FFFF, used by Hit The Ice and
+  Realpunc) is a black hole — fine for Rastan 2, not for hitice.
+
+## Per-file source-of-truth pointers
+
+| File                       | MAME ref                                            |
+|----------------------------|-----------------------------------------------------|
+| `hdl/jttaitob_main.v`      | taito_b.cpp:369 `rastsag2_map`                      |
+| `hdl/jttaitob_snd.v`       | taito_b.cpp:1859 `rastsag2()` machine_config        |
+| `hdl/jttaitob_syt.v`       | shared/taitosnd.cpp (TC0140SYT device)              |
+| `hdl/jttaitob_ioc.v`       | taito/taitoio.cpp:200 (tc0220ioc_device)            |
+| `hdl/jttaitob_video.v`     | taito/tc0180vcu.cpp (stub only)                     |
+| `hdl/jttaitob_colmix.v`    | taito_b.cpp:1887 `PALETTE(..., RGBx_444, 4096)`     |
+
+## Next steps (in order)
+
+1. ~~**Lint pass**~~ — done; clean against `jotego/linter`.
+2. ~~**MAME ground-truth capture**~~ — done. See
+   [doc/BOOT_TRACE.md](BOOT_TRACE.md) for annotated landmarks of the
+   first ~30 68k and ~20 Z80 instructions, plus 10 numbered
+   validation gates the FPGA sim must hit in order. Raw traces are
+   under `ver/rastan2/traces/` (gitignored).
+3. ~~**CPU spine sim**~~ — **done first try.** 60-frame sim hits all
+   six wired 68k-side gates (1, 3, 4, 5, 6, 10) with byte-exact data
+   match to MAME. After gate 10 the CPU settles into the ROM-checksum
+   loop at 0xBE4 — same place MAME's 1-second reference trace ends.
+   See [BOOT_TRACE.md §FPGA sim results](BOOT_TRACE.md). Gates 2
+   (SP load) and 7-9 (Z80 side) not wired yet but the 68k boot is
+   demonstrably correct through the entire 1.38M-instruction trace.
+4. **TC0180VCU bring-up — Phase 1 done.**
+   - Full 8×16-bit ctrl-reg file decoded in main.v.
+   - BG bank registers extracted (codes page from `ctrl[1][10:8]`,
+     attr page from `ctrl[1][14:12]`).
+   - VRAM port-B addressing in video.v: `tile_idx = {tile_y, tile_x}`
+     concatenated with `bg_bank`.
+   - Two-phase fetch alternates between tile-code and tile-attr reads.
+   - Attribute palette field (bits 5:0) feeds palette lookup.
+   - **Phase 1 finding**: MAME's first 5 seconds of sim show zero
+     VRAM/palette writes — the game stays in self-test (PC settles
+     into a `jsr/rts/bra` waiting loop at 0x59E). Natural-boot
+     visual verification requires either (a) IRQ-2 (`intl`) wiring
+     so the game's vblank handler can proceed, or (b) a scene-file
+     loader that pre-populates VRAM/palette state at sim start.
+     Phase 2 will pick one.
+
+   **Phase 2 (next)**: gfx ROM fetch from SDRAM bank 2 + 4-bpp
+   plane decode. Either fix the IRQ-2 wiring to let the game draw,
+   or capture a scene from MAME's later state.
+
+   **Phase 3+**: FG plane, text plane, sprite engine with zoom,
+   per-line scroll, screen flip, priority mixer, framebuffer.
+5. **MRA generation** — `jtframe mra --reduce` against the refreshed
+   `doc/mame.xml`; deploy `.rbf` + `.mra` to the MiSTer.
diff --git a/cores/taitob/doc/taito_b.cpp b/cores/taitob/doc/taito_b.cpp
new file mode 100644
index 000000000..2788dbaff
--- /dev/null
+++ b/cores/taitob/doc/taito_b.cpp
@@ -0,0 +1,3726 @@
+// license:GPL-2.0+
+// copyright-holders:Jarek Burczynski
+/***************************************************************************
+
+Taito B System
+
+driver by Jarek Burczynski, with help from:
+Nicola Salmoria, Brian A. Troha, stephh, Gerardo Oporto Jorrin, David Graves
+heavily based on Taito F2 System driver by Brad Oliver, Andrew Prime
+
+The board uses TC0220IOC, TC0260DAR, TC0180VCU, and TC0140SYT.
+Sonic Blast Man uses TC0510NIO instead of TC0220IOC.
+
+The palette resolution is 12 bits in some games and 15 bits in others.
+
+TODO:
+- hitice: ice trails are incorrect.
+- hitice: the pixel bitmap is not cleared on startup nor during attract mode. There's a
+  kludge to fix it in the first case.
+- rambo3u: has a lot of unmapped writes in the VCU area (log up to end of
+  round 2) [viofight also does a few]
+- The eprom games could have a single io handler if it's confirmed all
+  3 use a special 4 player I/O chip. Puzzle Bobble and qzshowby use TC0640FIO, as do the
+  more common sets of Space Invaders DX (i.e. not spacedxo).
+- can the text layer scroll? (hitice: glass walls at beginning of match, also check when the
+  screen wiggles after the puck hits the wall shortly into the first round of attract mode)
+- sprites are not in perfect sync with the background. Check ashura, they are almost
+  tight during gameplay but completely off in attract mode.
+- realpunc: missing camera emulation.
+
+The Taito B system is a fairly flexible hardware platform. It supports 4
+separate layers of graphics - one 64x64 tiled scrolling background plane
+of 16x16 tiles, a similar foreground plane, a sprite plane capable of sprite
+zooming and 'pageable' text plane of 8x8 tiles.
+
+Sound is handled by a Z80 with a YM2610 or YM2610B or YM2203's connected
+to it. Different sound chips - depending on game.
+
+The memory map for each of the games is similar but not identical.
+
+
+Memory map for Rastan Saga 2 / Nastar / Nastar Warrior :
+
+CPU 1 : 68000, uses irqs 2 & 4. One of the IRQs just sets a flag which is
+checked in the other IRQ routine. Could be timed to vblank...
+
+  0x000000 - 0x07ffff : ROM
+  0x200000 - 0x201fff : palette RAM, 4096 total colors (0x1000 words)
+  0x400000 - 0x403fff : 64x64 foreground layer (offsets 0x0000-0x1fff tile codes; offsets 0x2000-0x3fff tile attributes)
+  0x404000 - 0x407fff : 64x64 background layer (offsets 0x0000-0x1fff tile codes; offsets 0x2000-0x3fff tile attributes)
+  0x408000 - 0x408fff : 64x64 text layer
+  0x410000 - 0x41197f : ??k of sprite RAM (this is the range that Rastan Saga II tests at startup time)
+  0x413800 - 0x413bff : foreground (line/screen) scroll RAM
+  0x413c00 - 0x413fff : background (line/screen) scroll RAM
+
+  0x600000 - 0x607fff : 32k of CPU RAM
+  0x800000 - 0x800003 : communication with sound CPU via TC0140SYT
+  0xa00000 - 0xa0000f : input ports and dipswitches
+
+
+Notes:
+ Master of Weapon has secret command to select level:
+ (sequence is the same as in Metal Black):
+ - boot machine with service switch pressed
+ - message appears: "SERVICE SWITCH ERROR"
+ - press 1p start, 1p start, 1p start, service switch, 1p start
+ - message appears: "SELECT BY DOWN SW"
+ - select level with joy down/up
+ - press 1p start button
+
+Other games that have this feature:
+ Rastan Saga 2
+ Crime City
+ Violence Fight
+ Rambo 3
+
+
+
+List of known B-System games:
+
+    Rastan Saga II                  (YM2610 sound)
+    Ashura Blaster                  (YM2610 sound)
+    Crime City                      (YM2610 sound)
+    Rambo 3 (two different versions)(YM2610 sound)
+    Tetris                          (YM2610 sound)
+    Space Invaders DX               (YM2610 sound, MB87078 - electronic volume control)
+    Silent Dragon                   (YM2610 sound)
+    Sel Feena                       (YM2610 sound)
+    Ryujin                          (YM2610 sound)
+
+    Violence Fight                  (YM2203 sound, 1xMSM6295 )
+    Hit The Ice                     (YM2203 sound, 1xMSM6295 )
+    Master of Weapon                (YM2203 sound)
+
+    Quiz Sekai wa SHOW by shobai    (YM2610-B sound, MB87078 - electronic volume control)
+    Puzzle Bobble                   (YM2610-B sound, MB87078 - electronic volume control)
+    Sonic Blast Man                 (YM2610-B sound)
+
+Nastar
+Taito, 1988
+
+PCB Layout
+----------
+
+K1100419A  J1100178A
+|---------------------------------------|
+|68000  B81-13.31  B81-08.50  DSWA  DSWB|
+|       B81-09.30  B81-10.49  TC0220IOC |
+|24MHz B81-05.21 6264  6264             |
+|      B81-06.22 6264  6264             |
+|                           27.164MHz   |
+|B81-04.15                             J|
+|B81-03.14                             A|
+|             TC0180VCU     6264       M|
+|62256 62256                           M|
+|                           TC0260DAR  A|
+|62256 62256                            |
+|                              MB3735   |
+|62256 62256                 6264       |
+|             TC0140SYT      B81-11.37  |
+|62256 62256                 Z80A       |
+|                       16MHz           |
+|B81-02.2                               |
+|B81-01.1     YM2610 YM3016  TL074 TL074|
+|---------------------------------------|
+
+Notes:
+      68000 clock: 12.000MHz (24 / 2)
+        Z80 clock: 4.000MHz  (16 / 4)
+     YM2610 clock: 8.000MHz  (16 / 2)
+            Vsync: 60Hz
+
+
+
+Violence Fight
+Taito, 1989
+
+PCB Layout
+----------
+
+K1100511A  J1100213A
+|---------------------------------------|
+|C16-01.1   6264     6264     DSWA DSWB |
+|C16-02.2 C16-06.22 C16-07.41 TC0220IOC |
+|C16-03.3 C16-14.23 C16-11.42           |
+|C16-04.4      68000        6116        |
+|               / C16-08                |
+|           PALS\ C16-09    TC0260DAR  J|
+|   TC0180VCU                          A|
+|                                      M|
+|        27.164MHz               TL074 M|
+|                                      A|
+|        24MHz                          |
+|                               YM3014B |
+|            PC060HA      YM2203        |
+| 62256 62256            C16-05.47      |
+| 62256 62256 Z80B                MB3735|
+| 62256 62256 C16-12.32                 |
+| 62256 62256 6264        M6295  TL074  |
+|                  4.224MHz             |
+|---------------------------------------|
+
+Notes:
+      68000 clock: 12.000MHz (24 / 2)
+        Z80 clock: 6.000MHz  (24 / 4)
+     YM2203 clock: 3.000MHz  (24 / 8)
+      M6295 clock: 1.056MHz  (4.224 / 4), sample rate = 1056000 / 132
+            Vsync: 60Hz
+
+
+***************************************************************************
+
+Master of Weapon, Taito 1989
+Hardware info by Guru
+
+PCB Layout
+----------
+
+B SYSTEM
+K1100424A
+J1100181A
+K1100426A MAST OF WEAPON (sticker)
+|------------------------------------------------------------------|
+|VOL 4556  Y3014    YM2203       PC060HA       CXK58257  CXK58257  |
+|  MB3735           Z80                B72-10.IC32                 |
+|                   2018         B72_07.IC30                       |
+|                                              CXK58257  CXK58257  |
+|      62064  |-----|            TMM2063                           |
+|             |TC0260                                              |
+|J            |DAR  |            27.164MHz     CXK58257  CXK58257  |
+|A            |-----|                                              |
+|M                              |--------|                         |
+|M                              |TAITO   |     CXK58257  CXK58257  |
+|A                              |TC0180  |                         |
+|    48CR-1                     |VCU     |                         |
+|    48CR-1                     |--------|              B72-02.IC6 |
+|    48CR-1                                                        |
+|    48CR-1         TMM2063      TMM2063                B72-01.IC5 |
+|            MB3771                                                |
+| 48CR-1            B72_04.IC34  B72_03.IC25 B72-09.IC23 B72-08.IC3|
+|       TC0040IOC                                            24MHz |
+|   SW2   SW1       B72_06.IC33  B72_12.IC24          68000        |
+|------------------------------------------------------------------|
+Notes:
+      68000 - Motorola MC68000P12 CPU. Clock input 12.000MHz [24/2]
+        Z80 - Zilog Z0840006PSC CPU. Clock input 6.000MHz [24/4]
+     YM2203 - Yamaha YM2203 FM Operator Type-N sound chip. Clock input 3.000MHz [24/8]
+      Y3014 - Yamaha YM3014B Serial Input Floating D/A Converter. Clock input 1.0000MHz [24/24] on pin 5
+    PC060HA - Taito PC060HA CIU custom IC (68K<>Z80 communication)
+  TC0260DAR - Taito TC0260DAR custom IC (palette and RGB output)
+  TC0180VCU - Taito TC0180VCU custom IC (tilemap)
+  TC0040IOC - Taito TC0040IOC custom IC (controls, coin lockout, coin meter, DIP switch management and master reset/watchdog)
+   CXK58257 - Sony CXK58257 32kBx8-bit SRAM (video RAM)
+       2018 - Motorola MCM2018 2kBx8-bit SRAM (palette RAM)
+    TMM2063 - Toshiba TMM2063 8kBx8-bit SRAM (program RAM for 68000 & Z80)
+      62064 - Toshiba TD62064 4-Channel Darlington Sink Driver
+     MB3771 - Fujitsu MB3771 Master Reset IC
+      SW1/2 - 8-position DIP switch
+     48CR-1 - Custom resistor array
+       4556 - NEC uPC4556 Dual Operational Amplifier
+    MBB3735 - Fujitsu MB3735 Audio Power Amplifier
+B72_04.IC34 \
+B72_03.IC25  \ M5M27C101 128kBx8-bit EPROM (main program)
+B72_06.IC33  /
+B72_12.IC24 /
+B72_07.IC30 - 27C512 64kBx8-bit EPROM (sound program)
+ B72-02.IC6 \ 234000 512kBx8-bit mask ROM (equivalent to AM27C400, graphics)
+ B72-01.IC5 /
+B72-09.IC23 - MMI PAL16L8 (PCB marked 'INT')
+ B72-08.IC3 - MMI PAL16L8 (PCB marked 'DEC')
+B72-10.IC32 - MMI PAL16L8
+      HSync - 15.1782kHz \
+      VSync - 60.00000Hz / <-- actual measurements on PCB
+
+***************************************************************************/
+
+#include "emu.h"
+#include "taito_b.h"
+#include "taitoipt.h"
+#include "taitosnd.h"
+
+#include "cpu/m68000/m68000.h"
+#include "cpu/z80/z80.h"
+#include "machine/eepromser.h"
+#include "sound/okim6295.h"
+#include "sound/ymopn.h"
+#include "speaker.h"
+
+
+void taitob_state::bankswitch_w(uint8_t data)
+{
+	m_audiobank->set_entry(data & 3);
+}
+
+template<int Player>
+uint16_t rambo3_state::tracky_hi_r()
+{
+	return m_trackx_io[Player]->read();
+}
+
+template<int Player>
+uint16_t rambo3_state::tracky_lo_r()
+{
+	return (m_trackx_io[Player]->read() & 0xff) << 8;
+}
+
+template<int Player>
+uint16_t rambo3_state::trackx_hi_r()
+{
+	return m_tracky_io[Player]->read();
+}
+
+template<int Player>
+uint16_t rambo3_state::trackx_lo_r()
+{
+	return (m_tracky_io[Player]->read() & 0xff) << 8;
+}
+
+INPUT_CHANGED_MEMBER(taitob_c_state::realpunc_sensor)
+{
+	m_maincpu->set_input_line(4, HOLD_LINE);
+}
+
+/***************************************************************************
+
+  Puzzle Bobble, Qzshowby, Space DX   EEPROM
+
+***************************************************************************/
+
+uint16_t taitob_state::eep_latch_r()
+{
+	return m_eep_latch;
+}
+
+void taitob_state::eeprom_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	COMBINE_DATA(&m_eep_latch);
+
+	if (ACCESSING_BITS_8_15)
+	{
+		data >>= 8; /*M68k byte write*/
+
+		/* bit 0 - Unused */
+		/* bit 1 - Unused */
+		/* bit 2 - Eeprom data  */
+		/* bit 3 - Eeprom clock */
+		/* bit 4 - Eeprom reset (active low) */
+		/* bit 5 - Unused */
+		/* bit 6 - Unused */
+		/* bit 7 - set all the time (Chip Select?) */
+
+		/* EEPROM */
+		m_eepromout_io->write(data, 0xff);
+	}
+}
+
+/*************************************************************************
+   The input area for the three eprom games ($500000-2f) may well be
+   addressing a single i/o chip with 4 player and coin inputs as
+   standard. It's confirmed that all of these use TC0640FIO.
+*************************************************************************/
+
+
+void taitob_state::player_12_coin_ctrl_w(uint8_t data)
+{
+	machine().bookkeeping().coin_lockout_w(0, BIT(~data, 0));
+	machine().bookkeeping().coin_lockout_w(1, BIT(~data, 1));
+	machine().bookkeeping().coin_counter_w(0, BIT( data, 2));
+	machine().bookkeeping().coin_counter_w(1, BIT( data, 3));
+}
+
+uint16_t taitob_state::player_34_coin_ctrl_r()
+{
+	return m_coin_word;
+}
+
+void taitob_state::player_34_coin_ctrl_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	COMBINE_DATA(&m_coin_word);
+
+	/* coin counters and lockout */
+	machine().bookkeeping().coin_lockout_w(2, BIT(~data, 8));
+	machine().bookkeeping().coin_lockout_w(3, BIT(~data, 9));
+	machine().bookkeeping().coin_counter_w(2, BIT( data, 10));
+	machine().bookkeeping().coin_counter_w(3, BIT( data, 11));
+}
+
+void taitob_state::spacedxo_tc0220ioc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	if (ACCESSING_BITS_0_7)
+		m_tc0220ioc->write(offset, data & 0xff);
+	else
+	{
+		/* spacedxo also writes here - bug? */
+		m_tc0220ioc->write(offset, (data >> 8) & 0xff);
+	}
+}
+
+void taitob_c_state::output_w(uint16_t data)
+{
+/*
+   15 = Camera Enable?
+   14 = Lamp 2?
+   13 = Lamp 1?
+*/
+}
+
+
+void taitob_state::rastsag2_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x200000, 0x201fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x607fff).ram(); /* Main RAM */ /*ashura up to 603fff only*/
+	map(0x800000, 0x800001).nopr();
+	map(0x800000, 0x800000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x800002, 0x800002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0xa00000, 0xa0000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0xff00);
+}
+
+
+void taitob_state::crimec_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x200000, 0x20000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0xff00);
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x600001).nopr();
+	map(0x600000, 0x600000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x600002, 0x600002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0x800000, 0x801fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0xa00000, 0xa0ffff).ram(); /* Main RAM */
+}
+
+
+void taitob_state::tetrist_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x200000, 0x200001).nopr();
+	map(0x200000, 0x200000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x200002, 0x200002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x60000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0xff00);
+	map(0x800000, 0x807fff).ram(); /* Main RAM */
+	map(0xa00000, 0xa01fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+}
+
+void taitob_state::tetrista_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x200000, 0x201fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x600003).rw("tc0040ioc", FUNC(tc0040ioc_device::read), FUNC(tc0040ioc_device::write)).umask16(0xff00);
+	map(0x800000, 0x803fff).ram(); /* Main RAM */
+	map(0xa00000, 0xa00001).nopr();
+	map(0xa00000, 0xa00000).w("ciu", FUNC(pc060ha_device::master_port_w));
+	map(0xa00002, 0xa00002).rw("ciu", FUNC(pc060ha_device::master_comm_r), FUNC(pc060ha_device::master_comm_w));
+}
+
+
+void hitice_state::main_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x60000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0xff00);
+	map(0x610000, 0x610001).portr("P3_P4");
+	map(0x700000, 0x700001).nopr();
+	map(0x700000, 0x700000).w("ciu", FUNC(pc060ha_device::master_port_w));
+	map(0x700002, 0x700002).rw("ciu", FUNC(pc060ha_device::master_comm_r), FUNC(pc060ha_device::master_comm_w));
+	map(0x800000, 0x803fff).ram(); /* Main RAM */
+	map(0xa00000, 0xa01fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0xb00000, 0xb7ffff).ram().w(FUNC(hitice_state::pixelram_w)).share("pixelram");
+	map(0xbffff0, 0xbffff5).w(FUNC(hitice_state::pixel_scroll_w));
+//  { 0xbffffa, 0xbffffb, ???
+}
+
+
+void rambo3_state::main_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x200000, 0x200001).nopr();
+	map(0x200000, 0x200000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x200002, 0x200002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x60000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0xff00);
+	map(0x600010, 0x600011).r(FUNC(rambo3_state::tracky_lo_r<0>)); /*player 1*/
+	map(0x600012, 0x600013).r(FUNC(rambo3_state::tracky_hi_r<0>));
+	map(0x600014, 0x600015).r(FUNC(rambo3_state::trackx_lo_r<0>));
+	map(0x600016, 0x600017).r(FUNC(rambo3_state::trackx_hi_r<0>));
+	map(0x600018, 0x600019).r(FUNC(rambo3_state::tracky_lo_r<1>)); /*player 2*/
+	map(0x60001a, 0x60001b).r(FUNC(rambo3_state::tracky_hi_r<1>));
+	map(0x60001c, 0x60001d).r(FUNC(rambo3_state::trackx_lo_r<1>));
+	map(0x60001e, 0x60001f).r(FUNC(rambo3_state::trackx_hi_r<1>));
+	map(0x800000, 0x803fff).ram(); /* Main RAM */
+	map(0xa00000, 0xa01fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+}
+
+
+void taitob_state::pbobble_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x500000, 0x50000f).rw(m_tc0640fio, FUNC(tc0640fio_device::halfword_byteswap_r), FUNC(tc0640fio_device::halfword_byteswap_w));
+	map(0x500024, 0x500025).portr("P3_P4_A");        /* shown in service mode, game omits to read it */
+	map(0x500026, 0x500027).rw(FUNC(taitob_state::eep_latch_r), FUNC(taitob_state::eeprom_w));
+	map(0x500028, 0x500029).w(FUNC(taitob_state::player_34_coin_ctrl_w));    /* simply locks coins 3&4 out */
+	map(0x50002e, 0x50002f).portr("P3_P4_B");        /* shown in service mode, game omits to read it */
+	map(0x600000, 0x600003).w("mb87078", FUNC(mb87078_device::data_w)).umask16(0xff00);
+	map(0x700000, 0x700001).nopr();
+	map(0x700000, 0x700000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x700002, 0x700002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0x800000, 0x801fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x900000, 0x90ffff).ram(); /* Main RAM */
+}
+
+/* identical to pbobble, above??? */
+void taitob_state::spacedx_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x500000, 0x50000f).rw(m_tc0640fio, FUNC(tc0640fio_device::halfword_byteswap_r), FUNC(tc0640fio_device::halfword_byteswap_w));
+	map(0x500024, 0x500025).portr("P3_P4_A");
+	map(0x500026, 0x500027).rw(FUNC(taitob_state::eep_latch_r), FUNC(taitob_state::eeprom_w));
+	map(0x500028, 0x500029).w(FUNC(taitob_state::player_34_coin_ctrl_w));    /* simply locks coins 3&4 out */
+	map(0x50002e, 0x50002f).portr("P3_P4_B");
+	map(0x600000, 0x600003).w("mb87078", FUNC(mb87078_device::data_w)).umask16(0xff00);
+	map(0x700000, 0x700001).nopr();
+	map(0x700000, 0x700000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x700002, 0x700002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0x800000, 0x801fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x900000, 0x90ffff).ram(); /* Main RAM */
+}
+
+void taitob_state::spacedxo_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x100000, 0x100001).nopr();
+	map(0x100000, 0x100000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x100002, 0x100002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0x200000, 0x20000f).r(m_tc0220ioc, FUNC(tc0220ioc_device::read)).umask16(0x00ff);
+	map(0x200000, 0x20000f).w(FUNC(taitob_state::spacedxo_tc0220ioc_w));
+	map(0x210000, 0x210001).portr("IN3");
+	map(0x220000, 0x220001).portr("IN4");
+	map(0x230000, 0x230001).portr("IN5");
+	map(0x300000, 0x301fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x302000, 0x303fff).readonly();
+	map(0x400000, 0x40ffff).ram(); /* Main RAM */
+	map(0x500000, 0x57ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+}
+
+
+void taitob_state::qzshowby_map(address_map &map)
+{
+	map(0x000000, 0x0fffff).rom();
+	map(0x200000, 0x20000f).rw(m_tc0640fio, FUNC(tc0640fio_device::halfword_byteswap_r), FUNC(tc0640fio_device::halfword_byteswap_w));
+	map(0x200024, 0x200025).portr("P3_P4_A");    /* player 3,4 start */
+	map(0x200026, 0x200027).w(FUNC(taitob_state::eeprom_w));
+	map(0x200028, 0x200029).rw(FUNC(taitob_state::player_34_coin_ctrl_r), FUNC(taitob_state::player_34_coin_ctrl_w));
+	map(0x20002e, 0x20002f).portr("P3_P4_B");    /* player 3,4 buttons */
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x600001).nopr();
+	map(0x600000, 0x600000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x600002, 0x600002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0x700000, 0x700003).w("mb87078", FUNC(mb87078_device::data_w)).umask16(0xff00);
+	map(0x800000, 0x801fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x900000, 0x90ffff).ram(); /* Main RAM */
+}
+
+
+void taitob_state::viofight_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x200000, 0x200001).nopr();
+	map(0x200000, 0x200000).w("ciu", FUNC(pc060ha_device::master_port_w));
+	map(0x200002, 0x200002).rw("ciu", FUNC(pc060ha_device::master_comm_r), FUNC(pc060ha_device::master_comm_w));
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x601fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x800000, 0x80000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0xff00);
+	map(0xa00000, 0xa03fff).ram(); /* Main RAM */
+}
+
+
+void taitob_state::masterw_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x200000, 0x203fff).ram(); /* Main RAM */
+	map(0x400000, 0x47ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x600000, 0x601fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x800000, 0x800003).rw("tc0040ioc", FUNC(tc0040ioc_device::read), FUNC(tc0040ioc_device::write)).umask16(0xff00);
+	map(0xa00000, 0xa00001).nopr();
+	map(0xa00000, 0xa00000).w("ciu", FUNC(pc060ha_device::master_port_w));
+	map(0xa00002, 0xa00002).rw("ciu", FUNC(pc060ha_device::master_comm_r), FUNC(pc060ha_device::master_comm_w));
+}
+
+
+void taitob_state::silentd_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x100000, 0x100001).nopr();
+	map(0x100000, 0x100000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x100002, 0x100002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+//  map(0x10001a, 0x10001b).nopr(); // ??? read at $1e344
+//  map(0x10001c, 0x10001d).nopr(); // ??? read at $1e356
+	map(0x200000, 0x20000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0x00ff);
+	map(0x210000, 0x210001).portr("IN3");
+	map(0x220000, 0x220001).portr("IN4");
+	map(0x230000, 0x230001).portr("IN5");
+	map(0x240000, 0x240001).nopw(); // ???
+//  map(0x240000, 0x240001).nopr(); /* read 4 times at init */
+	map(0x300000, 0x301fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x400000, 0x403fff).ram(); /* Main RAM */
+	map(0x500000, 0x57ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+}
+
+
+void taitob_state::selfeena_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x100000, 0x103fff).ram(); /* Main RAM */
+	map(0x200000, 0x27ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x300000, 0x301fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x400000, 0x40000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0xff00);
+	map(0x410000, 0x41000f).rw(m_tc0220ioc, FUNC(tc0220ioc_device::read), FUNC(tc0220ioc_device::write)).umask16(0xff00); /* mirror address - seems to be only used for coin control */
+	map(0x500000, 0x500001).nopr();
+	map(0x500000, 0x500000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x500002, 0x500002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+}
+
+
+void taitob_state::sbm_map(address_map &map)
+{
+	map(0x000000, 0x07ffff).rom();
+	map(0x100000, 0x10ffff).ram(); /* Main RAM */
+	map(0x200000, 0x201fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x300000, 0x30000f).rw(m_tc0510nio, FUNC(tc0510nio_device::halfword_wordswap_r), FUNC(tc0510nio_device::halfword_wordswap_w));
+	map(0x320000, 0x320001).nopr();
+	map(0x320000, 0x320000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x320002, 0x320002).rw("tc0140syt", FUNC(tc0140syt_device::master_comm_r), FUNC(tc0140syt_device::master_comm_w));
+	map(0x900000, 0x97ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+}
+
+void taitob_c_state::main_map(address_map &map)
+{
+	map(0x000000, 0x0fffff).rom();
+	map(0x100000, 0x10ffff).ram();
+	map(0x110000, 0x12ffff).ram();
+	map(0x130000, 0x13ffff).ram(); // Check me
+	map(0x180000, 0x18000f).rw(m_tc0510nio, FUNC(tc0510nio_device::halfword_wordswap_r), FUNC(tc0510nio_device::halfword_wordswap_w));
+	map(0x184000, 0x184001).w(FUNC(taitob_c_state::video_ctrl_w));
+	map(0x188000, 0x188001).nopr();
+	map(0x188000, 0x188000).w("tc0140syt", FUNC(tc0140syt_device::master_port_w));
+	map(0x188002, 0x188003).nopr();
+	map(0x188002, 0x188002).w("tc0140syt", FUNC(tc0140syt_device::master_comm_w));
+	map(0x18c000, 0x18c001).w(FUNC(taitob_c_state::output_w));
+	map(0x200000, 0x27ffff).m(m_tc0180vcu, FUNC(tc0180vcu_device::tc0180vcu_memrw));
+	map(0x280000, 0x281fff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0x300000, 0x300003).rw(m_hd63484, FUNC(hd63484_device::read16), FUNC(hd63484_device::write16));
+//  map(0x320000, 0x320001).nop(); // ?
+	map(0x320002, 0x320003).nopr();
+	map(0x320002, 0x320002).w("tc0140syt", FUNC(tc0140syt_device::master_comm_w));
+}
+
+void taitob_c_state::hd63484_map(address_map &map)
+{
+	map(0x00000, 0x7ffff).ram();
+}
+
+void taitob_state::masterw_sound_map(address_map &map)
+{
+	map(0x0000, 0x3fff).rom();
+	map(0x4000, 0x7fff).bankr(m_audiobank);
+	map(0x8000, 0x8fff).ram();
+	map(0x9000, 0x9001).rw("ymsnd", FUNC(ym2203_device::read), FUNC(ym2203_device::write));
+	map(0xa000, 0xa000).w("ciu", FUNC(pc060ha_device::slave_port_w));
+	map(0xa001, 0xa001).rw("ciu", FUNC(pc060ha_device::slave_comm_r), FUNC(pc060ha_device::slave_comm_w));
+}
+
+void taitob_state::sound_map(address_map &map)
+{
+	map(0x0000, 0x3fff).rom();
+	map(0x4000, 0x7fff).bankr(m_audiobank);
+	map(0xc000, 0xdfff).ram();
+	map(0xe000, 0xe003).rw("ymsnd", FUNC(ym_generic_device::read), FUNC(ym_generic_device::write));
+	map(0xe200, 0xe200).nopr().w("tc0140syt", FUNC(tc0140syt_device::slave_port_w));
+	map(0xe201, 0xe201).rw("tc0140syt", FUNC(tc0140syt_device::slave_comm_r), FUNC(tc0140syt_device::slave_comm_w));
+	map(0xe400, 0xe403).nopw(); /* pan */
+	map(0xe600, 0xe600).nopw(); /* ? */
+	map(0xea00, 0xea00).nopr();
+	map(0xee00, 0xee00).nopw(); /* ? */
+	map(0xf000, 0xf000).nopw(); /* ? */
+	map(0xf200, 0xf200).w(FUNC(taitob_state::bankswitch_w));
+}
+
+void taitob_state::viofight_sound_map(address_map &map)
+{
+	masterw_sound_map(map);
+	map(0xb000, 0xb001).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write));       /* yes, both addresses for the same chip */
+}
+
+
+/***********************************************************
+             INPUT PORTS, DIPs
+***********************************************************/
+
+#define TAITO_B_SYSTEM_INPUT \
+	PORT_START("IN2") \
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT ) \
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 ) \
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2) \
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2) \
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) \
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START1 ) \
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START2 )
+
+
+static INPUT_PORTS_START( rastsag2 ) /* Japanese version */
+	PORT_START("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)  // all 2 "unused" in manual
+	TAITO_COINAGE_JAPAN_OLD_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )   PORT_DIPLOCATION("SW2:3,4")
+	PORT_DIPSETTING(    0x0c, "100k only" )
+	PORT_DIPSETTING(    0x08, "150k only" )
+	PORT_DIPSETTING(    0x04, "200k only" )
+	PORT_DIPSETTING(    0x00, "250k only" )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )        PORT_DIPLOCATION("SW2:5,6")
+	PORT_DIPSETTING(    0x20, "1" )
+	PORT_DIPSETTING(    0x10, "2" )
+	PORT_DIPSETTING(    0x30, "3" )
+	PORT_DIPSETTING(    0x00, "5" )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Allow_Continue ) )   PORT_DIPLOCATION("SW2:7")
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x40, DEF_STR( On ) )
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" )        /* Listed as "Unused" */
+
+	PORT_START("IN0")
+	TAITO_JOY_UDLR_2_BUTTONS( 1 )
+
+	PORT_START("IN1")
+	TAITO_JOY_UDLR_2_BUTTONS( 2 )
+
+	TAITO_B_SYSTEM_INPUT
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( nastar ) /* World version */
+	PORT_INCLUDE(rastsag2)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_WORLD_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( nastarw ) /* USA version */
+	PORT_INCLUDE(rastsag2)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_US_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( masterw )
+	PORT_START("DSWA")
+	TAITO_MACHINE_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_WORLD_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )   PORT_DIPLOCATION("SW2:3,4")
+	PORT_DIPSETTING(    0x08, "500k, 1000k and 1500k" )
+	PORT_DIPSETTING(    0x0c, "500k and 1000k" )
+	PORT_DIPSETTING(    0x04, "500k only" )
+	PORT_DIPSETTING(    0x00, DEF_STR( None ) )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )        PORT_DIPLOCATION("SW2:5,6")
+	PORT_DIPSETTING(    0x30, "3" )
+	PORT_DIPSETTING(    0x20, "4" )
+	PORT_DIPSETTING(    0x10, "5" )
+	PORT_DIPSETTING(    0x00, "6" )
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:7" )        /* Listed as "Unused" */
+	PORT_DIPNAME( 0x80, 0x80, "Ship Type" )         PORT_DIPLOCATION("SW2:8")
+	PORT_DIPSETTING(    0x80, "Space Ship" )
+	PORT_DIPSETTING(    0x00, "Hover Cycle" )
+
+	PORT_START("IN0")
+	TAITO_JOY_UDLR_2_BUTTONS( 1 )
+
+	PORT_START("IN1")
+	TAITO_JOY_UDLR_2_BUTTONS( 2 )
+
+	TAITO_B_SYSTEM_INPUT
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( masterwj )
+	PORT_INCLUDE(masterw)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_JAPAN_OLD_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( masterwu )
+	PORT_INCLUDE(masterw)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_US_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( yukiwo )
+	PORT_INCLUDE(masterw)
+
+	PORT_MODIFY("DSWB")
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" )        /* This prototype doesn't seem to have the "Space Ship" option */
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( crimec )
+	PORT_START("DSWA")
+	PORT_DIPNAME( 0x01, 0x01, "Hi Score" )          PORT_DIPLOCATION("SW1:1")
+	PORT_DIPSETTING(    0x01, "Scribble" )
+	PORT_DIPSETTING(    0x00, "3 Characters" )
+	TAITO_DSWA_BITS_1_TO_3_LOC(SW1)
+	TAITO_COINAGE_WORLD_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )   PORT_DIPLOCATION("SW2:3,4")
+	PORT_DIPSETTING(    0x08, "every 80k" )
+	PORT_DIPSETTING(    0x0c, "80k only" )
+	PORT_DIPSETTING(    0x04, "160k only" )
+	PORT_DIPSETTING(    0x00, DEF_STR( None ) )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )        PORT_DIPLOCATION("SW2:5,6")
+	PORT_DIPSETTING(    0x10, "1" )
+	PORT_DIPSETTING(    0x20, "2" )
+	PORT_DIPSETTING(    0x30, "3" )
+	PORT_DIPSETTING(    0x00, "4" )
+	PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Allow_Continue ) )   PORT_DIPLOCATION("SW2:7,8")
+	PORT_DIPSETTING( 0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING( 0x40, "5 Times" )
+	PORT_DIPSETTING( 0x80, "8 Times" )
+	PORT_DIPSETTING( 0xc0, DEF_STR( On ) )
+
+	PORT_START("IN0")
+	TAITO_JOY_UDLR_2_BUTTONS( 1 )
+
+	PORT_START("IN1")
+	TAITO_JOY_UDLR_2_BUTTONS( 2 )
+
+	TAITO_B_SYSTEM_INPUT
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( crimecj )
+	PORT_INCLUDE(crimec)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_JAPAN_OLD_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( crimecu )
+	PORT_INCLUDE(crimec)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_US_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( tetrist )
+	PORT_START("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_JAPAN_OLD_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW2:3" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW2:4" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW2:5" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW2:6" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:7" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" )        /* Listed as "Unused" */
+
+	PORT_START("IN0")
+	TAITO_JOY_UDLR_2_BUTTONS( 1 )
+
+	PORT_START("IN1")
+	TAITO_JOY_UDLR_2_BUTTONS( 2 )
+
+	TAITO_B_SYSTEM_INPUT
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( ashura )
+	PORT_START("DSWA")
+	TAITO_MACHINE_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_WORLD_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )   PORT_DIPLOCATION("SW2:3,4")
+	PORT_DIPSETTING(    0x08, "every 100k" )
+	PORT_DIPSETTING(    0x0c, "every 150k" )
+	PORT_DIPSETTING(    0x04, "every 200k" )
+	PORT_DIPSETTING(    0x00, "every 250k" )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )        PORT_DIPLOCATION("SW2:5,6")
+	PORT_DIPSETTING(    0x00, "1" )
+	PORT_DIPSETTING(    0x10, "2" )
+	PORT_DIPSETTING(    0x30, "3" )
+	PORT_DIPSETTING(    0x20, "4" )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Allow_Continue ) )   PORT_DIPLOCATION("SW2:7") /* Listed as Unused in the manual */
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x40, DEF_STR( On ) )
+	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )      PORT_DIPLOCATION("SW2:8") /* Listed as Unused in the manual */
+	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+
+	PORT_START("IN0")
+	TAITO_JOY_UDLR_2_BUTTONS( 1 )
+
+	PORT_START("IN1")
+	TAITO_JOY_UDLR_2_BUTTONS( 2 )
+
+	TAITO_B_SYSTEM_INPUT
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( ashuraj )
+	PORT_INCLUDE(ashura)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_JAPAN_OLD_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( ashurau )
+	PORT_INCLUDE(ashura)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_US_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( hitice )
+	PORT_START("DSWA")
+	PORT_DIPNAME( 0x01, 0x01, "Cabinet Style" )     PORT_DIPLOCATION("SW1:1")
+	PORT_DIPSETTING(    0x01, "4 Players")
+	PORT_DIPSETTING(    0x00, "2 Players")
+	PORT_DIPUNUSED_DIPLOC( 0x02, 0x02, "SW1:2" )        /* Listed as "Unused" */
+	PORT_SERVICE_DIPLOC(  0x04, IP_ACTIVE_LOW, "SW1:3" )
+	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )  PORT_DIPLOCATION("SW1:4")
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x08, DEF_STR( On ) )
+	PORT_DIPNAME( 0x70, 0x70, DEF_STR( Coinage ) )      PORT_DIPLOCATION("SW1:5,6,7")
+	PORT_DIPSETTING(    0x50, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x60, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x70, DEF_STR( 1C_1C ) )
+	PORT_DIPSETTING(    0x30, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(    0x40, DEF_STR( 1C_3C ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( 1C_4C ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( 1C_5C ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( 1C_6C ) )
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW1:8" )        /* Listed as "Unused" */
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, "Timer count" )       PORT_DIPLOCATION("SW2:3,4")
+	PORT_DIPSETTING(    0x0c, "1 sec = 58/60" )
+	PORT_DIPSETTING(    0x04, "1 sec = 56/60" )
+	PORT_DIPSETTING(    0x08, "1 sec = 62/60" )
+	PORT_DIPSETTING(    0x00, "1 sec = 45/60" )
+	PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW2:5" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW2:6" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:7" )        /* Listed as "Unused" */
+	PORT_DIPNAME( 0x80, 0x80, "Maximum credits" )       PORT_DIPLOCATION("SW2:8")
+	PORT_DIPSETTING(    0x00, "99" )
+	PORT_DIPSETTING(    0x80, "9"  )
+
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
+
+	PORT_START("P3_P4")
+	PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x0010, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
+	PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
+	PORT_BIT( 0x0040, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
+	PORT_BIT( 0x0080, IP_ACTIVE_LOW, IPT_START3 )
+	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
+	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
+	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
+	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_START4 )
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( hiticej )
+	PORT_INCLUDE(hitice)
+
+	PORT_MODIFY("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_JAPAN_NEW_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( rambo3 )
+	PORT_START("DSWA")  /* DSW A */
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_WORLD_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW2:3" )        /* Listed as "Unused" */
+	PORT_DIPNAME( 0x08, 0x08, "Control" )           PORT_DIPLOCATION("SW2:4")
+	PORT_DIPSETTING(    0x08, "8 way Joystick" )
+	PORT_DIPSETTING(    0x00, DEF_STR( Trackball ) )
+	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Allow_Continue ) )   PORT_DIPLOCATION("SW2:5")
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( On ) )
+	PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW2:6" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:7" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" )        /* Listed as "Unused" */
+
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_COIN1 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_COIN2 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
+
+	PORT_START("TRACKX1")
+	PORT_BIT( 0xffff, 0x0000, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(70) PORT_KEYDELTA(30) PORT_REVERSE PORT_PLAYER(1)
+
+	PORT_START("TRACKY1")
+	PORT_BIT( 0xffff, 0x0000, IPT_TRACKBALL_X ) PORT_SENSITIVITY(70) PORT_KEYDELTA(30) PORT_PLAYER(1)
+
+	PORT_START("TRACKX2")
+	PORT_BIT( 0xffff, 0x0000, IPT_TRACKBALL_Y ) PORT_SENSITIVITY(70) PORT_KEYDELTA(30) PORT_REVERSE PORT_PLAYER(2)
+
+	PORT_START("TRACKY2")
+	PORT_BIT( 0xffff, 0x0000, IPT_TRACKBALL_X ) PORT_SENSITIVITY(70) PORT_KEYDELTA(30) PORT_PLAYER(2)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( rambo3u )
+	PORT_INCLUDE(rambo3)
+
+	PORT_MODIFY("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_US_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( rambo3p )
+	PORT_START("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)  // all 5 "unused" in manual
+	TAITO_COINAGE_WORLD_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW2:3" )        /* Listed as "Unused" */
+	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )      PORT_DIPLOCATION("SW2:4")
+	PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Allow_Continue ) )   PORT_DIPLOCATION("SW2:5")
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( On ) )
+	PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW2:6" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:7" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" )        /* Listed as "Unused" */
+
+	PORT_START("IN0")
+	TAITO_JOY_UDLR_2_BUTTONS( 1 )
+
+	PORT_START("IN1")
+	TAITO_JOY_UDLR_2_BUTTONS( 2 )
+
+	TAITO_B_SYSTEM_INPUT
+
+	PORT_START("TRACKX1")
+	PORT_BIT( 0xffff, IP_ACTIVE_HIGH, IPT_UNKNOWN )
+
+	PORT_START("TRACKY1")
+	PORT_BIT( 0xffff, IP_ACTIVE_HIGH, IPT_UNKNOWN )
+
+	PORT_START("TRACKX2")
+	PORT_BIT( 0xffff, IP_ACTIVE_HIGH, IPT_UNKNOWN )
+
+	PORT_START("TRACKY2")
+	PORT_BIT( 0xffff, IP_ACTIVE_HIGH, IPT_UNKNOWN )
+INPUT_PORTS_END
+
+
+/* Helps document the input ports. */
+
+static INPUT_PORTS_START( pbobble ) /* Missing P3&4 controls ! */
+	PORT_START("SERVICE")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW ) /*ok*/
+
+	PORT_START("COIN")
+	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", FUNC(eeprom_serial_93cxx_device::do_read))
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2) /*ok*/
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2) /*ok*/
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2) /*ok*/
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_IMPULSE(2) /*ok*/
+
+	PORT_START("START")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE2 )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE3 )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START3 )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
+
+	PORT_START("P1_P2_A")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+
+	PORT_START("P1_P2_B")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
+
+	PORT_START("P3_P4_A")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+
+	PORT_START("P3_P4_B")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
+
+	PORT_START( "EEPROMOUT" )
+	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", FUNC(eeprom_serial_93cxx_device::di_write))
+	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", FUNC(eeprom_serial_93cxx_device::clk_write))
+	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", FUNC(eeprom_serial_93cxx_device::cs_write))
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( spacedxo )
+	PORT_START("DSWA")
+	TAITO_MACHINE_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_JAPAN_NEW_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, "Match Point" )       PORT_DIPLOCATION("SW2:3,4")
+	PORT_DIPSETTING(    0x08, "4" )
+	PORT_DIPSETTING(    0x0c, "3" )
+	PORT_DIPSETTING(    0x04, "5" )
+	PORT_DIPSETTING(    0x00, "2" )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )        PORT_DIPLOCATION("SW2:5,6")
+	PORT_DIPSETTING(    0x30, "3" )
+	PORT_DIPSETTING(    0x20, "4" )
+	PORT_DIPSETTING(    0x10, "5" )
+	PORT_DIPSETTING(    0x00, "6" )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Bonus_Life ) )   PORT_DIPLOCATION("SW2:7")
+	PORT_DIPSETTING(    0x40, "1500 Points" )
+	PORT_DIPSETTING(    0x00, "1000 Points" )
+	PORT_DIPNAME( 0x80, 0x80, "Game Type" )         PORT_DIPLOCATION("SW2:8")
+	PORT_DIPSETTING(    0x80, "Double Company" )
+	PORT_DIPSETTING(    0x00, "Single Company" )
+
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
+
+	PORT_START("IN3")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START3 )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
+
+	PORT_START("IN4")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START4 )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
+
+	PORT_START("IN5")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE2 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE3 )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( qzshowby )
+	PORT_START("SERVICE")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN ) /*unused in test mode*/
+	PORT_SERVICE_NO_TOGGLE( 0x80, IP_ACTIVE_LOW ) /*ok*/
+
+	PORT_START("COIN")
+	PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_CUSTOM ) PORT_READ_LINE_DEVICE_MEMBER("eeprom", FUNC(eeprom_serial_93cxx_device::do_read))
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2) /*ok*/
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2) /*ok*/
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2) /*ok*/
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_IMPULSE(2) /*ok*/
+
+	PORT_START("START")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_SERVICE2 )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE3 )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_START3 )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_START4 )
+
+	PORT_START("P1_P2_A")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* IPT_START1 in test mode */
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* IPT_START2 in test mode */
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("P1_P2_B")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
+
+	PORT_START("P3_P4_A")
+	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_UNKNOWN  ) /* IPT_START3 in test mode */
+	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_UNKNOWN  ) /* IPT_START4 in test mode */
+	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("P3_P4_B")
+	PORT_BIT( 0x0100, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
+	PORT_BIT( 0x0200, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
+	PORT_BIT( 0x0400, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(3)
+	PORT_BIT( 0x0800, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
+	PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
+	PORT_BIT( 0x2000, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
+	PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(4)
+	PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
+
+	PORT_START( "EEPROMOUT" )
+	PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", FUNC(eeprom_serial_93cxx_device::di_write))
+	PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", FUNC(eeprom_serial_93cxx_device::clk_write))
+	PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_OUTPUT ) PORT_WRITE_LINE_DEVICE_MEMBER("eeprom", FUNC(eeprom_serial_93cxx_device::cs_write))
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( viofight )
+	PORT_START("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)  // all 7 "unused" in manual
+	TAITO_COINAGE_WORLD_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPUNUSED_DIPLOC( 0x04, 0x04, "SW2:3" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x08, 0x08, "SW2:4" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW2:5" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW2:6" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:7" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" )        /* Listed as "Unused" */
+
+	PORT_START("IN0")
+	TAITO_JOY_UDLR_3_BUTTONS( 1 )
+
+	PORT_START("IN1")
+	TAITO_JOY_UDLR_3_BUTTONS( 2 )
+
+	TAITO_B_SYSTEM_INPUT
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( viofightj )
+	PORT_INCLUDE(viofight)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_JAPAN_OLD_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( viofightu )
+	PORT_INCLUDE(viofight)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_US_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( silentd ) /* World Version */
+	PORT_START("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)          /* Listed as "NOT USED" in the manual and only shown as "OFF" */
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) )      PORT_DIPLOCATION("SW1:5,6")
+	PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW1:7" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW1:8" )        /* Listed as "Unused" */
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x04, 0x04, "Friendly Fire" )   PORT_DIPLOCATION("SW2:3") // "hit of players" or "invincible player mode"
+	PORT_DIPSETTING(    0x04, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x08, 0x08, "Power-Up at Stage Clear" )   PORT_DIPLOCATION("SW2:4") // "clear stage power-up"
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x08, DEF_STR( On ) )
+	PORT_DIPNAME( 0x10, 0x10, "Regain Power buy-in" )      PORT_DIPLOCATION("SW2:5") // If enabled player can use a credit to refill his HP and get a "rage" mode for few seconds
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( On ) )
+
+/*  Manual Shows "1 Coin Slot (Shared)" and "4 Coin Slot (1 Per Player)"
+
+    You can play the game with 2, 3, or 4 players and the last option is a linked 4 players.
+    Using bit6 and bit7&8 you end up with 1, 2 or 4 separate "Credits" on the demo screens.
+    Using bits7&8 you can have 2-4 players as shown at the top of the game screens.
+
+*/
+
+	PORT_DIPNAME( 0x20, 0x20, "Credits" )           PORT_DIPLOCATION("SW2:6") /* Only shows 4 separate credits with 4p/1m below */
+	PORT_DIPSETTING(    0x20, "Combined" )
+	PORT_DIPSETTING(    0x00, "Separate" )          /* When multiple credits show, Coin B will affect p2 credits */
+	PORT_DIPNAME( 0xc0, 0x80, "Cabinet Style" )     PORT_DIPLOCATION("SW2:7,8")
+	PORT_DIPSETTING(    0xc0, "3 Players" )
+	PORT_DIPSETTING(    0x80, "2 Players" )
+	PORT_DIPSETTING(    0x40, "4 Players/1 Machine" )   /* with bit6, shows 4 separate credits */
+	PORT_DIPSETTING(    0x00, "4 Players/2 Machines" )  /* with bit6 shows 2 separate credits */
+
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
+
+	PORT_START("IN3")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START3 )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(3)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(3)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(3)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(3)
+
+	PORT_START("IN4")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START4 )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(4)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(4)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(4)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(4)
+
+	PORT_START("IN5")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_COIN3 ) PORT_IMPULSE(2) PORT_NAME ("Coin 3 2nd input")/*not sure if this is legal under MAME*/
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN4 ) PORT_IMPULSE(2) PORT_NAME ("Coin 4 2nd input")/*not sure if this is legal under MAME*/
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( silentdj )
+	PORT_INCLUDE(silentd)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_JAPAN_OLD_LOC(SW1)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( silentdu )
+	PORT_INCLUDE(silentd)
+
+	PORT_MODIFY("DSWA")
+	TAITO_COINAGE_US_LOC(SW1)
+INPUT_PORTS_END
+
+
+static INPUT_PORTS_START( selfeena )
+	PORT_START("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_JAPAN_NEW_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Bonus_Life ) )   PORT_DIPLOCATION("SW2:3,4")
+	PORT_DIPSETTING(    0x0c, "100k only" )
+	PORT_DIPSETTING(    0x08, "200k only" )
+	PORT_DIPSETTING(    0x04, "300k only" )
+	PORT_DIPSETTING(    0x00, "400k only" )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Lives ) )        PORT_DIPLOCATION("SW2:5,6")
+	PORT_DIPSETTING(    0x00, "1" )
+	PORT_DIPSETTING(    0x10, "2" )
+	PORT_DIPSETTING(    0x30, "3" )
+	PORT_DIPSETTING(    0x20, "4" )
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:7" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" )        /* Listed as "Unused" */
+
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( ryujin )
+	PORT_START("DSWA")
+	TAITO_MACHINE_NO_COCKTAIL_LOC(SW1)
+	TAITO_COINAGE_JAPAN_NEW_LOC(SW1)
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Lives ) )        PORT_DIPLOCATION("SW2:3,4")
+	PORT_DIPSETTING(    0x00, "1" )
+	PORT_DIPSETTING(    0x04, "2" )
+	PORT_DIPSETTING(    0x0c, "3" )
+	PORT_DIPSETTING(    0x08, "4" )
+	PORT_DIPUNUSED_DIPLOC( 0x10, 0x10, "SW2:5" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x20, 0x20, "SW2:6" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x40, 0x40, "SW2:7" )        /* Listed as "Unused" */
+	PORT_DIPUNUSED_DIPLOC( 0x80, 0x80, "SW2:8" )        /* Listed as "Unused" */
+
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(2)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON3 ) PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)
+
+	PORT_START("IN3")
+	PORT_BIT(  0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN4")
+	PORT_BIT(  0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN5")
+	PORT_BIT(  0xff, IP_ACTIVE_LOW, IPT_UNKNOWN )
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( sbm )
+	PORT_START("DSWA")
+	PORT_DIPNAME( 0x01, 0x01, "Tickets" )                   PORT_DIPLOCATION("SW1:1")
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x01, DEF_STR( On ) )
+	PORT_DIPNAME( 0x02, 0x02, "Win Bonus Tickets" )         PORT_DIPLOCATION("SW1:2")
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x02, DEF_STR( On ) )
+	PORT_SERVICE_DIPLOC(  0x04, IP_ACTIVE_LOW, "SW1:3" )
+	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Demo_Sounds ) )      PORT_DIPLOCATION("SW1:4")
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x08, DEF_STR( On ) )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coinage ) )          PORT_DIPLOCATION("SW1:5,6")
+	PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )          PORT_DIPLOCATION("SW1:7")
+	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )          PORT_DIPLOCATION("SW1:8")
+	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+
+	PORT_START("DSWB")
+	TAITO_DIFFICULTY_LOC(SW2)
+	PORT_DIPNAME( 0x0c, 0x0c, "Punch Power" )               PORT_DIPLOCATION("SW2:3,4")
+	/* Modifies the power of the player's punch by a set amount. Table is at 0x0A614:
+	    DIP 00: 0000 ;+00
+	    DIP 01: FFFB ;-05
+	    DIP 10: 0005 :+05
+	    DIP 11: 000A :+10
+	    For example, if the player had an initial power of 200t and Dip Switches 2-3 and 2-4 were both set, the power would be increased to 210t.
+	    This bonus (or penalty) is applied before the game floors the punch power at 1t and before it caps the punch power at 300t. So, if in MAME, you hold Pad Photosensors 1 and 2 and then immediately hit Pad Photosensor 3, you'll still get a punch power of 300t even if Dip Switch 2-3 was set and Dip Switch 2-4 wasn't.
+	    Just for reference, the initial power of the player's punch is calculated by taking 24000 and dividing it by the timer at 105048 in RAM. This is performed in the subroutine at 0x0A5B0 in the main CPU.
+	*/
+	PORT_DIPSETTING(    0x08, "Lower" )
+	PORT_DIPSETTING(    0x0c, DEF_STR( Medium ) )
+	PORT_DIPSETTING(    0x04, DEF_STR( Higher ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( Highest ) )
+	PORT_DIPNAME( 0x30, 0x30, "Tickets Payout" )            PORT_DIPLOCATION("SW2:5,6")
+	/* Controls the power divider. The game calculates the base ticket total by taking the total power of the player's three punches and then dividing it by one of four values in the table at 0x7FFC0:
+	    DIP 00: 50
+	    DIP 01: 40
+	    DIP 10: 80
+	    DIP 11: 120
+	    For example, if the player got a combined total of 640t power and dip switch 2-6 was set but 2-5 was not, they'll have a base of 8 tickets.
+	*/
+	PORT_DIPSETTING(    0x00, "Total Power / 120" )
+	PORT_DIPSETTING(    0x10, "Total Power / 80" )
+	PORT_DIPSETTING(    0x30, "Total Power / 50" )
+	PORT_DIPSETTING(    0x20, "Total Power / 40" )
+	PORT_DIPNAME( 0xc0, 0xc0, "Win Bonus Tickets Payout" )  PORT_DIPLOCATION("SW2:7,8")
+	/* Controls the value of the round completion ticket bonus. Each round has its own ticket table: The first value is for 00, the second is for 01, third for 10, fourth for 11:
+	    7FFC8: 0001 0002 0003 0002 #ROUND 1 BONUS TABLE - 01 / 02 / 03 / 02
+	    7FFD0: 0002 0004 0004 0004 #ROUND 2 BONUS TABLE - 02 / 04 / 04 / 04
+	    7FFD8: 0003 0006 0005 0008 #ROUND 3 BONUS TABLE - 03 / 06 / 05 / 08
+	    7FFE0: 0004 0008 0006 0010 #ROUND 4 BONUS TABLE - 04 / 08 / 06 / 16
+	    7FFE8: 0005 000A 0007 0020 #ROUND 5 BONUS TABLE - 05 / 10 / 07 / 32
+	    For example, if the player beat round 4 and dip switch 2-7 was set but 2-8 was not, they'd have a bonus of 8 tickets.
+	*/
+	PORT_DIPSETTING(    0xc0, "1, 2, 3, 4, 5" )
+	PORT_DIPSETTING(    0x80, "2, 4, 6, 8, 10" )
+	PORT_DIPSETTING(    0x40, "3, 4, 5, 6, 7" )
+	PORT_DIPSETTING(    0x00, "2, 4, 8, 16, 32" )
+
+	PORT_START("JOY")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(1)//sound select UP
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(1)//sound select DOWN
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(1)//ok (object test)
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(1)//ok (object test)
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_PLAYER(2)//-- unused in test modes
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_PLAYER(2)//-- unused in test modes
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_PLAYER(2)//BEN IN (ticket dispenser)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_PLAYER(2)//LADY ????
+
+	PORT_START("START")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME("Select")//select; ok (1P in object test)
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 ) PORT_NAME("Start")//start ; ok (2P in object test)
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("PHOTOSENSOR")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_TILT )       //ok
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_SERVICE1 )   //ok
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)   //ok
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)   //ok
+	/* BUTTON1 ACTIVE LOW, - game thinks that punching pad has already been raised */
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_PLAYER(1) PORT_NAME("Pad Photosensor 1")//PHOTO 1 (punching pad photosensor 1)
+	PORT_BIT( 0x20, IP_ACTIVE_HIGH,IPT_BUTTON2 ) PORT_PLAYER(1) PORT_NAME("Pad Photosensor 2")//PHOTO 2 (punching pad photosensor 2)
+	PORT_BIT( 0x40, IP_ACTIVE_HIGH,IPT_BUTTON3 ) PORT_PLAYER(1) PORT_NAME("Pad Photosensor 3")//PHOTO 3 (punching pad photosensor 3)
+	/*To simulate a punch:
+	    - wait for "READY GO!" message,
+	    - press button1 + button 2 (LCTRL + ALT) (you'll hear a "punching" sound),
+	    - THEN  press button 3 (SPACE)
+	    The time passed between the presses will be used to calculate the power of your punch.
+	    The longer the time - the less power.
+	*/
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_BUTTON4 ) PORT_PLAYER(1) PORT_NAME("Pad Photosensor 4")//PHOTO 4  ??? ACTIVE_LOW  ??? (punching pad photosensor 4)
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( sbmj )
+	PORT_INCLUDE(sbm)
+
+	PORT_MODIFY("DSWA")
+	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Unknown ) )  PORT_DIPLOCATION("SW1:1")
+	PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )  PORT_DIPLOCATION("SW1:2")
+	PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_A ) )   PORT_DIPLOCATION("SW1:5,6")
+	PORT_DIPSETTING(    0x00, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
+	PORT_DIPNAME( 0xc0, 0xc0, DEF_STR( Coin_B ) )   PORT_DIPLOCATION("SW1:7,8")
+	PORT_DIPSETTING(    0x00, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x40, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x80, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(    0xc0, DEF_STR( 1C_1C ) )
+
+	PORT_MODIFY("DSWB")
+	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )  PORT_DIPLOCATION("SW2:5")
+	PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )  PORT_DIPLOCATION("SW2:6")
+	PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )  PORT_DIPLOCATION("SW2:7")
+	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )  PORT_DIPLOCATION("SW2:8")
+	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+INPUT_PORTS_END
+
+static INPUT_PORTS_START( realpunc )
+	PORT_START("DSWA")
+	PORT_DIPNAME( 0x01, 0x01, DEF_STR( Demo_Sounds ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x01, DEF_STR( On ) )
+	PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) )
+	PORT_DIPSETTING(    0x02, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x0c, 0x0c, DEF_STR( Coin_A ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(    0x04, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x08, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x0c, DEF_STR( 1C_1C ) )
+	PORT_DIPNAME( 0x30, 0x30, DEF_STR( Coin_B ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x30, DEF_STR( 1C_1C ) )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) )
+	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
+	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+
+	PORT_START("DSWB")
+	PORT_DIPNAME( 0x01, 0x01, "Difficulty 1" )
+	PORT_DIPSETTING(    0x01, DEF_STR( Off ))
+	PORT_DIPSETTING(    0x00, DEF_STR( On ))
+	PORT_DIPNAME( 0x02, 0x02, "Difficulty 2" )
+	PORT_DIPSETTING(    0x02, DEF_STR( Off ))
+	PORT_DIPSETTING(    0x00, DEF_STR( On ))
+	PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) )
+	PORT_DIPSETTING(    0x04, DEF_STR( Off ))
+	PORT_DIPSETTING(    0x00, DEF_STR( On ))
+	PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) )
+	PORT_DIPSETTING(    0x08, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x40, 0x40, "Difficulty 3" )
+	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) )
+	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_SERVICE )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_TILT )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_IMPULSE(2)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_IMPULSE(2)
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW,IPT_BUTTON1 ) PORT_NAME("Safety switch")
+	PORT_BIT( 0x02, IP_ACTIVE_LOW,IPT_UNKNOWN )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW,IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW,IPT_UNKNOWN )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW,IPT_BUTTON2 ) PORT_NAME("Pad Photosensor 1 (N)") PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(taitob_c_state::realpunc_sensor), 0)
+	PORT_BIT( 0x20, IP_ACTIVE_LOW,IPT_BUTTON3 ) PORT_NAME("Pad Photosensor 2 (U)") PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(taitob_c_state::realpunc_sensor), 0)
+	PORT_BIT( 0x40, IP_ACTIVE_LOW,IPT_BUTTON4 ) PORT_NAME("Pad Photosensor 3 (D)") PORT_CHANGED_MEMBER(DEVICE_SELF, FUNC(taitob_c_state::realpunc_sensor), 0)
+	PORT_BIT( 0x80, IP_ACTIVE_LOW,IPT_UNKNOWN )
+INPUT_PORTS_END
+
+
+/*
+    Games that use the mb87078 are: pbobble, spacedx and qzshowby
+    schems are not available, but from the writes I guess that
+    they only use channel 1
+    The sound chips' volume altered with the mb87078 are:
+    ym2610 in spacedx,
+    ym2610b in pbobble,qzshowby,
+
+    Both ym2610 and ym2610b generate 3 (PSG like) + 2 (fm left,right) channels.
+    I use mixer_set_volume() to emulate the effect.
+*/
+void taitob_state::mb87078_gain_changed(offs_t offset, uint8_t data)
+{
+	if (offset == 1)
+	{
+		device_sound_interface *sound;
+		m_ym->interface(sound);
+		sound->set_output_gain(0, data / 100.0);
+		sound->set_output_gain(1, data / 100.0);
+		sound->set_output_gain(2, data / 100.0);
+		//popmessage("MB87078 gain ch#%i percent=%i", offset, data);
+	}
+}
+
+
+void taitob_state::machine_start()
+{
+	m_audiobank->configure_entries(0, 4, memregion("audiocpu")->base(), 0x4000);
+
+	save_item(NAME(m_eep_latch));
+	save_item(NAME(m_coin_word));
+}
+
+void taitob_state::machine_reset()
+{
+	m_eep_latch = 0;
+	m_coin_word = 0;
+}
+
+
+void taitob_state::rastsag2(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::rastsag2_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x40);
+	m_tc0180vcu->set_bg_colorbase(0xc0);
+	m_tc0180vcu->set_fg_colorbase(0x80);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_2, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610_device &ymsnd(YM2610(config, m_ym, 16_MHz_XTAL / 2));  /* 8 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::masterw(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::masterw_map);
+
+	Z80(config, m_audiocpu, 24_MHz_XTAL / 4);  /* 6 MHz Z80B */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::masterw_sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	tc0040ioc_device &tc0040ioc(TC0040IOC(config, "tc0040ioc", 0));
+	tc0040ioc.read_0_callback().set_ioport("DSWA");
+	tc0040ioc.read_1_callback().set_ioport("DSWB");
+	tc0040ioc.read_2_callback().set_ioport("IN0");
+	tc0040ioc.read_3_callback().set_ioport("IN1");
+	tc0040ioc.write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	tc0040ioc.read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x10);
+	m_tc0180vcu->set_bg_colorbase(0x30);
+	m_tc0180vcu->set_fg_colorbase(0x20);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_5, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2203_device &ymsnd(YM2203(config, m_ym, 24_MHz_XTAL / 8));  /* 3 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.port_a_write_callback().set_membank(m_audiobank).mask(0x03);
+	ymsnd.add_route(0, "mono", 0.25);
+	ymsnd.add_route(1, "mono", 0.25);
+	ymsnd.add_route(2, "mono", 0.25);
+	ymsnd.add_route(3, "mono", 0.80);
+
+	pc060ha_device &ciu(PC060HA(config, "ciu", 0));
+	ciu.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	ciu.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::tetrist(machine_config &config) /* Nastar conversion kit with slightly different memory map */
+{
+	rastsag2(config);
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::tetrist_map);
+	m_palette->set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+}
+
+
+void taitob_state::tetrista(machine_config &config) /* Master of Weapon conversion kit with slightly different memory map */
+{
+	masterw(config);
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::tetrista_map);
+	m_palette->set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+}
+
+
+void taitob_state::ashura(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::rastsag2_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x40);
+	m_tc0180vcu->set_bg_colorbase(0xc0);
+	m_tc0180vcu->set_fg_colorbase(0x80);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_2, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610_device &ymsnd(YM2610(config, m_ym, 16_MHz_XTAL / 2));  /* 8 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::crimec(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::crimec_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x80);
+	m_tc0180vcu->set_bg_colorbase(0x00);
+	m_tc0180vcu->set_fg_colorbase(0x40);
+	m_tc0180vcu->set_tx_colorbase(0xc0);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_5, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_3, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610_device &ymsnd(YM2610(config, m_ym, 16_MHz_XTAL / 2));  /* 8 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void hitice_state::hitice(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &hitice_state::main_map);
+
+	Z80(config, m_audiocpu, 24_MHz_XTAL / 4);  /* 6 MHz Z80B */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &hitice_state::viofight_sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(hitice_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(hitice_state::screen_update_hitice));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4); // nominally "6.6 MHZ"
+	m_tc0180vcu->set_fb_colorbase(0x40);
+	m_tc0180vcu->set_bg_colorbase(0xc0);
+	m_tc0180vcu->set_fg_colorbase(0x80);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_6, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2203_device &ymsnd(YM2203(config, m_ym, 24_MHz_XTAL / 8));  /* 3 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.port_a_write_callback().set_membank(m_audiobank).mask(0x03);
+	ymsnd.add_route(0, "mono", 0.25);
+	ymsnd.add_route(1, "mono", 0.25);
+	ymsnd.add_route(2, "mono", 0.25);
+	ymsnd.add_route(3, "mono", 0.80);
+
+	okim6295_device &oki(OKIM6295(config, "oki", 1056000, okim6295_device::PIN7_HIGH)); // clock frequency & pin 7 not verified
+	oki.add_route(ALL_OUTPUTS, "mono", 0.50);
+
+	pc060ha_device &ciu(PC060HA(config, "ciu", 0));
+	ciu.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	ciu.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void rambo3_state::rambo3p(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* verified on pcb */
+	m_maincpu->set_addrmap(AS_PROGRAM, &rambo3_state::main_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4); /* verified on pcb */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &rambo3_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(rambo3_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(rambo3_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x40);
+	m_tc0180vcu->set_bg_colorbase(0xc0);
+	m_tc0180vcu->set_fg_colorbase(0x80);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_6, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_1, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610_device &ymsnd(YM2610(config, "ymsnd", 16_MHz_XTAL / 2));   /* verified on pcb */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void rambo3_state::rambo3(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12MHz verified on pcb */
+	m_maincpu->set_addrmap(AS_PROGRAM, &rambo3_state::main_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4); /* 4MHz verified on pcb */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &rambo3_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(rambo3_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(rambo3_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x10);
+	m_tc0180vcu->set_bg_colorbase(0x30);
+	m_tc0180vcu->set_fg_colorbase(0x20);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_6, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_1, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610_device &ymsnd(YM2610(config, "ymsnd", 16_MHz_XTAL / 2));  /* 8 MHz verified on pcb */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::pbobble(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::pbobble_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 2);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	EEPROM_93C46_16BIT(config, "eeprom");
+
+	TC0640FIO(config, m_tc0640fio, 0);
+	m_tc0640fio->read_0_callback().set_ioport("SERVICE");
+	m_tc0640fio->read_1_callback().set_ioport("COIN");
+	m_tc0640fio->read_2_callback().set_ioport("START");
+	m_tc0640fio->read_3_callback().set_ioport("P1_P2_A");
+	m_tc0640fio->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0640fio->read_7_callback().set_ioport("P1_P2_B");
+
+	MB87078(config, m_mb87078);
+	m_mb87078->gain_changed().set(FUNC(taitob_state::mb87078_gain_changed));
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x80);
+	m_tc0180vcu->set_bg_colorbase(0x00);
+	m_tc0180vcu->set_fg_colorbase(0x40);
+	m_tc0180vcu->set_tx_colorbase(0xc0);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_3, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_5, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610b_device &ymsnd(YM2610B(config, "ymsnd", 16_MHz_XTAL / 2));  /* 8 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::spacedx(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::spacedx_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	EEPROM_93C46_16BIT(config, "eeprom");
+
+	TC0640FIO(config, m_tc0640fio, 0);
+	m_tc0640fio->read_0_callback().set_ioport("SERVICE");
+	m_tc0640fio->read_1_callback().set_ioport("COIN");
+	m_tc0640fio->read_2_callback().set_ioport("START");
+	m_tc0640fio->read_3_callback().set_ioport("P1_P2_A");
+	m_tc0640fio->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0640fio->read_7_callback().set_ioport("P1_P2_B");
+
+	MB87078(config, m_mb87078);
+	m_mb87078->gain_changed().set(FUNC(taitob_state::mb87078_gain_changed));
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x80);
+	m_tc0180vcu->set_bg_colorbase(0x00);
+	m_tc0180vcu->set_fg_colorbase(0x40);
+	m_tc0180vcu->set_tx_colorbase(0xc0);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_3, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_5, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610_device &ymsnd(YM2610(config, "ymsnd", 16_MHz_XTAL / 2));  /* 8 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::spacedxo(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::spacedxo_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x10);
+	m_tc0180vcu->set_bg_colorbase(0x30);
+	m_tc0180vcu->set_fg_colorbase(0x20);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_6, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610_device &ymsnd(YM2610(config, "ymsnd", 16_MHz_XTAL / 2));  /* 8 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::qzshowby(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 16000000);   /* 16 MHz according to the readme*/
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::qzshowby_map);
+
+	Z80(config, m_audiocpu, 4000000);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	EEPROM_93C46_16BIT(config, "eeprom");
+
+	TC0640FIO(config, m_tc0640fio, 0);
+	m_tc0640fio->read_0_callback().set_ioport("SERVICE");
+	m_tc0640fio->read_1_callback().set_ioport("COIN");
+	m_tc0640fio->read_2_callback().set_ioport("START");
+	m_tc0640fio->read_3_callback().set_ioport("P1_P2_A");
+	m_tc0640fio->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0640fio->read_7_callback().set_ioport("P1_P2_B");
+
+	MB87078(config, m_mb87078);
+	m_mb87078->gain_changed().set(FUNC(taitob_state::mb87078_gain_changed));
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x80);
+	m_tc0180vcu->set_bg_colorbase(0x00);
+	m_tc0180vcu->set_fg_colorbase(0x40);
+	m_tc0180vcu->set_tx_colorbase(0xc0);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_3, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_5, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610b_device &ymsnd(YM2610B(config, "ymsnd", 8000000));
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::viofight(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::viofight_map);
+
+	Z80(config, m_audiocpu, 24_MHz_XTAL / 4);  /* 6 MHz verified */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::viofight_sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x10);
+	m_tc0180vcu->set_bg_colorbase(0x30);
+	m_tc0180vcu->set_fg_colorbase(0x20);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_1, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2203_device &ymsnd(YM2203(config, m_ym, 24_MHz_XTAL / 8));  /* 3 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.port_a_write_callback().set_membank(m_audiobank).mask(0x03);
+	ymsnd.add_route(0, "mono", 0.25);
+	ymsnd.add_route(1, "mono", 0.25);
+	ymsnd.add_route(2, "mono", 0.25);
+	ymsnd.add_route(3, "mono", 0.80);
+
+	okim6295_device &oki(OKIM6295(config, "oki", 4.224_MHz_XTAL / 4, okim6295_device::PIN7_HIGH)); // 1.056MHz clock frequency, but pin 7 not verified
+	oki.add_route(ALL_OUTPUTS, "mono", 0.50);
+
+	pc060ha_device &ciu(PC060HA(config, "ciu", 0));
+	ciu.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	ciu.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::silentd(machine_config &config) /* ET910000B PCB */
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::silentd_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x10);
+	m_tc0180vcu->set_bg_colorbase(0x30);
+	m_tc0180vcu->set_fg_colorbase(0x20);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_6, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610b_device &ymsnd(YM2610B(config, "ymsnd", 16_MHz_XTAL / 2));  /* 8 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_state::selfeena(machine_config &config) /* ET910000A PCB */
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::selfeena_map);
+
+	Z80(config, m_audiocpu, 16_MHz_XTAL / 4);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0220IOC(config, m_tc0220ioc, 0);
+	m_tc0220ioc->read_0_callback().set_ioport("DSWA");
+	m_tc0220ioc->read_1_callback().set_ioport("DSWB");
+	m_tc0220ioc->read_2_callback().set_ioport("IN0");
+	m_tc0220ioc->read_3_callback().set_ioport("IN1");
+	m_tc0220ioc->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0220ioc->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x10);
+	m_tc0180vcu->set_bg_colorbase(0x30);
+	m_tc0180vcu->set_fg_colorbase(0x20);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_6, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610_device &ymsnd(YM2610(config, "ymsnd", 16_MHz_XTAL / 2));  /* 8 MHz */
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+#if 0
+void taitob_state::ryujin_patch(void)
+{
+	uint16_t *rom = (uint16_t*)memregion("maincpu")->base();
+	rom[ 0x62/2 ] = 1;
+	//0 (already in rom) - Taito Corporation 1993
+	//1 - Taito America corp with blue FBI logo
+}
+#endif
+
+
+#if 0
+void taitob_state::sbm_patch(void)
+{
+	uint16_t *rom = (uint16_t*)memregion("maincpu")->base();
+	rom[ 0x7ffff/2 ] = 2; //US version
+}
+#endif
+
+void taitob_state::sbm(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 12000000);   /* 12 MHz */
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_state::sbm_map);
+
+	Z80(config, m_audiocpu, 4000000);  /* 4 MHz */
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0510NIO(config, m_tc0510nio, 0);
+	m_tc0510nio->read_0_callback().set_ioport("DSWA");
+	m_tc0510nio->read_1_callback().set_ioport("DSWB");
+	m_tc0510nio->read_2_callback().set_ioport("JOY");
+	m_tc0510nio->read_3_callback().set_ioport("START");
+	m_tc0510nio->write_4_callback().set(FUNC(taitob_state::player_12_coin_ctrl_w));
+	m_tc0510nio->read_7_callback().set_ioport("PHOTOSENSOR");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RGBx_444, 4096);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x40);
+	m_tc0180vcu->set_bg_colorbase(0xc0);
+	m_tc0180vcu->set_fg_colorbase(0x80);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_4, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_5, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610b_device &ymsnd(YM2610B(config, "ymsnd", 8000000));
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+
+void taitob_c_state::realpunc(machine_config &config)
+{
+	/* basic machine hardware */
+	M68000(config, m_maincpu, 12000000);
+	m_maincpu->set_addrmap(AS_PROGRAM, &taitob_c_state::main_map);
+
+	Z80(config, m_audiocpu, 6000000);
+	m_audiocpu->set_addrmap(AS_PROGRAM, &taitob_c_state::sound_map);
+
+	config.set_maximum_quantum(attotime::from_hz(600));
+
+	TC0510NIO(config, m_tc0510nio, 0);
+	m_tc0510nio->read_0_callback().set_ioport("DSWA");
+	m_tc0510nio->read_1_callback().set_ioport("DSWB");
+	m_tc0510nio->read_2_callback().set_ioport("IN0");
+	m_tc0510nio->read_3_callback().set_ioport("IN1");
+	m_tc0510nio->write_4_callback().set(FUNC(taitob_c_state::player_12_coin_ctrl_w));
+	m_tc0510nio->read_7_callback().set_ioport("IN2");
+
+	/* video hardware */
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(64*8, 32*8);
+	m_screen->set_visarea(0*8, 40*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(taitob_c_state::screen_update));
+	m_screen->set_palette(m_palette);
+
+	PALETTE(config, m_palette).set_format(palette_device::RRRRGGGGBBBBRGBx, 4096);
+
+	HD63484(config, m_hd63484, 0);
+	m_hd63484->set_addrmap(0, &taitob_c_state::hd63484_map);
+	m_hd63484->set_auto_configure_screen(false);
+
+	TC0180VCU(config, m_tc0180vcu, 27.164_MHz_XTAL / 4);
+	m_tc0180vcu->set_fb_colorbase(0x40);
+	m_tc0180vcu->set_bg_colorbase(0xc0);
+	m_tc0180vcu->set_fg_colorbase(0x80);
+	m_tc0180vcu->set_tx_colorbase(0x00);
+	m_tc0180vcu->set_palette(m_palette);
+	m_tc0180vcu->inth_callback().set_inputline(m_maincpu, M68K_IRQ_2, HOLD_LINE);
+	m_tc0180vcu->intl_callback().set_inputline(m_maincpu, M68K_IRQ_3, HOLD_LINE);
+
+	/* sound hardware */
+	SPEAKER(config, "mono").front_center();
+
+	ym2610b_device &ymsnd(YM2610B(config, "ymsnd", 8000000));
+	ymsnd.irq_handler().set_inputline(m_audiocpu, 0);
+	ymsnd.add_route(0, "mono", 0.75);
+	ymsnd.add_route(1, "mono", 1.0);
+	ymsnd.add_route(2, "mono", 1.0);
+
+	tc0140syt_device &tc0140syt(TC0140SYT(config, "tc0140syt", 0));
+	tc0140syt.nmi_callback().set_inputline(m_audiocpu, INPUT_LINE_NMI);
+	tc0140syt.reset_callback().set_inputline(m_audiocpu, INPUT_LINE_RESET);
+}
+
+/***************************************************************************
+
+  Game driver(s)
+
+***************************************************************************/
+
+ROM_START( rastsag2 )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b81-08.50", 0x00000, 0x20000, CRC(d6da9169) SHA1(33d74315754576e6f879059de033f96f9003f819) )
+	ROM_LOAD16_BYTE( "b81-07.31", 0x00001, 0x20000, CRC(8edf17d7) SHA1(b0c03002ed520abffefd55d4969d0ed4fcf3a3a4) )
+	ROM_LOAD16_BYTE( "b81-10.49", 0x40000, 0x20000, CRC(53f34344) SHA1(9930c3fd9c17f7d9b654221da3896d0ff5778c97) )
+	ROM_LOAD16_BYTE( "b81-09.30", 0x40001, 0x20000, CRC(630d34af) SHA1(42452111b10f1d543e03661012dda879218dea62) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b81-11.37", 0x00000, 0x10000, CRC(3704bf09) SHA1(a0a37b23e3df482c5f5aa43825345ea8affbba34) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b81-03.14", 0x000000, 0x080000, CRC(551b75e6) SHA1(5b8388ee2c6262f359c9e6d04c951ea8dc3901c9) )
+	ROM_LOAD( "b81-04.15", 0x080000, 0x080000, CRC(cf734e12) SHA1(4201a74468058761454515738fbf3a7b22a66e00) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "b81-02.2", 0x00000, 0x80000, CRC(20ec3b86) SHA1(fcdcc7f0a09feb824d8d73b1af0aae7ec30fd1ed) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcmb", 0 )
+	ROM_LOAD( "b81-01.1", 0x00000, 0x80000, CRC(b33f796b) SHA1(6cdb32f56283acdf20eb46a1e658e3bd7c97978c) )
+ROM_END
+
+ROM_START( nastarw )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b81-08.50", 0x00000, 0x20000, CRC(d6da9169) SHA1(33d74315754576e6f879059de033f96f9003f819) )
+	ROM_LOAD16_BYTE( "b81-12.31", 0x00001, 0x20000, CRC(f9d82741) SHA1(f5f3a1101d92b6c241e819dcdcdcdc4b125140f7) )
+	ROM_LOAD16_BYTE( "b81-10.49", 0x40000, 0x20000, CRC(53f34344) SHA1(9930c3fd9c17f7d9b654221da3896d0ff5778c97) )
+	ROM_LOAD16_BYTE( "b81-09.30", 0x40001, 0x20000, CRC(630d34af) SHA1(42452111b10f1d543e03661012dda879218dea62) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b81-11.37", 0x00000, 0x10000, CRC(3704bf09) SHA1(a0a37b23e3df482c5f5aa43825345ea8affbba34) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b81-03.14", 0x000000, 0x080000, CRC(551b75e6) SHA1(5b8388ee2c6262f359c9e6d04c951ea8dc3901c9) )
+	ROM_LOAD( "b81-04.15", 0x080000, 0x080000, CRC(cf734e12) SHA1(4201a74468058761454515738fbf3a7b22a66e00) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "b81-02.2", 0x00000, 0x80000, CRC(20ec3b86) SHA1(fcdcc7f0a09feb824d8d73b1af0aae7ec30fd1ed) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcmb", 0 )
+	ROM_LOAD( "b81-01.1", 0x00000, 0x80000, CRC(b33f796b) SHA1(6cdb32f56283acdf20eb46a1e658e3bd7c97978c) )
+ROM_END
+
+ROM_START( nastar )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b81-08.50", 0x00000, 0x20000, CRC(d6da9169) SHA1(33d74315754576e6f879059de033f96f9003f819) )
+	ROM_LOAD16_BYTE( "b81-13.31", 0x00001, 0x20000, CRC(60d176fb) SHA1(fbe3a0603bcd23e565b0d474a63742d20a3ce8cc) )
+	ROM_LOAD16_BYTE( "b81-10.49", 0x40000, 0x20000, CRC(53f34344) SHA1(9930c3fd9c17f7d9b654221da3896d0ff5778c97) )
+	ROM_LOAD16_BYTE( "b81-09.30", 0x40001, 0x20000, CRC(630d34af) SHA1(42452111b10f1d543e03661012dda879218dea62) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b81-11.37", 0x00000, 0x10000, CRC(3704bf09) SHA1(a0a37b23e3df482c5f5aa43825345ea8affbba34) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b81-03.14", 0x000000, 0x080000, CRC(551b75e6) SHA1(5b8388ee2c6262f359c9e6d04c951ea8dc3901c9) )
+	ROM_LOAD( "b81-04.15", 0x080000, 0x080000, CRC(cf734e12) SHA1(4201a74468058761454515738fbf3a7b22a66e00) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "b81-02.2", 0x00000, 0x80000, CRC(20ec3b86) SHA1(fcdcc7f0a09feb824d8d73b1af0aae7ec30fd1ed) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcmb", 0 )
+	ROM_LOAD( "b81-01.1", 0x00000, 0x80000, CRC(b33f796b) SHA1(6cdb32f56283acdf20eb46a1e658e3bd7c97978c) )
+
+	ROM_REGION( 0x0400, "plds", 0 )
+	ROM_LOAD( "ampal16l8-b81-05.21",  0x0000, 0x0104, CRC(922fd368) SHA1(6258c64a16c64de5c9c29e325a5e1f9695698b1f) )
+	ROM_LOAD( "ampal16l8-b81-06a.22", 0x0200, 0x0104, CRC(bb1cec84) SHA1(fc7a8286687508b4e62b9754dba95f33336b8214) )
+ROM_END
+
+ROM_START( crimec )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b99-07.40", 0x00000, 0x20000, CRC(26e886e6) SHA1(b7d0024a084216c1139eb6705f1b8143902cbed3) )
+	ROM_LOAD16_BYTE( "b99-05.29", 0x00001, 0x20000, CRC(ff7f9a9d) SHA1(c1897a141eea423879d2792640a9ee85636ed5be) )
+	ROM_LOAD16_BYTE( "b99-06.39", 0x40000, 0x20000, CRC(1f26aa92) SHA1(10ab253812db83204c136d01d865063a2210cb92) )
+	ROM_LOAD16_BYTE( "b99-14.28", 0x40001, 0x20000, CRC(71c8b4d7) SHA1(55068c9cac75200f564b10f98f322e30aaa6849e) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b99-08.45", 0x00000, 0x10000, CRC(26135451) SHA1(651c77285eb12a13a2fe4069031c6f01150ecba4) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b99-02.18", 0x000000, 0x080000, CRC(2a5d4a26) SHA1(94bdfca9365970a80a639027b195b71cebc5ab9c) )
+	ROM_LOAD( "b99-01.19", 0x080000, 0x080000, CRC(a19e373a) SHA1(2208c9142473dc2218fd8b97fd6d0c861aeba011) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "b99-03.37", 0x000000, 0x080000, CRC(dda10df7) SHA1(ffbe1423794035e6f049fddb096b7282610b7cee) )
+ROM_END
+
+ROM_START( crimecu )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b99-07.40", 0x00000, 0x20000, CRC(26e886e6) SHA1(b7d0024a084216c1139eb6705f1b8143902cbed3) )
+	ROM_LOAD16_BYTE( "b99-05.29", 0x00001, 0x20000, CRC(ff7f9a9d) SHA1(c1897a141eea423879d2792640a9ee85636ed5be) )
+	ROM_LOAD16_BYTE( "b99-06.39", 0x40000, 0x20000, CRC(1f26aa92) SHA1(10ab253812db83204c136d01d865063a2210cb92) )
+	ROM_LOAD16_BYTE( "b99-13.28", 0x40001, 0x20000, CRC(06cf8441) SHA1(0395fd1f38366bd56b4b53e435dc7c3676d9e9bf) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b99-08.45", 0x00000, 0x10000, CRC(26135451) SHA1(651c77285eb12a13a2fe4069031c6f01150ecba4) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b99-02.18", 0x000000, 0x080000, CRC(2a5d4a26) SHA1(94bdfca9365970a80a639027b195b71cebc5ab9c) )
+	ROM_LOAD( "b99-01.19", 0x080000, 0x080000, CRC(a19e373a) SHA1(2208c9142473dc2218fd8b97fd6d0c861aeba011) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "b99-03.37", 0x000000, 0x080000, CRC(dda10df7) SHA1(ffbe1423794035e6f049fddb096b7282610b7cee) )
+ROM_END
+
+ROM_START( crimecj )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b99-07.40", 0x00000, 0x20000, CRC(26e886e6) SHA1(b7d0024a084216c1139eb6705f1b8143902cbed3) )
+	ROM_LOAD16_BYTE( "b99-05.29", 0x00001, 0x20000, CRC(ff7f9a9d) SHA1(c1897a141eea423879d2792640a9ee85636ed5be) )
+	ROM_LOAD16_BYTE( "b99-06.39", 0x40000, 0x20000, CRC(1f26aa92) SHA1(10ab253812db83204c136d01d865063a2210cb92) )
+	ROM_LOAD16_BYTE( "b99-15.28", 0x40001, 0x20000, CRC(e8c1e56d) SHA1(ba0dc181db843e26676223f54cb121df738be987) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b99-08.45", 0x00000, 0x10000, CRC(26135451) SHA1(651c77285eb12a13a2fe4069031c6f01150ecba4) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b99-02.18", 0x000000, 0x080000, CRC(2a5d4a26) SHA1(94bdfca9365970a80a639027b195b71cebc5ab9c) )
+	ROM_LOAD( "b99-01.19", 0x080000, 0x080000, CRC(a19e373a) SHA1(2208c9142473dc2218fd8b97fd6d0c861aeba011) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "b99-03.37", 0x000000, 0x080000, CRC(dda10df7) SHA1(ffbe1423794035e6f049fddb096b7282610b7cee) )
+ROM_END
+
+ROM_START( ashura )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "c43-15.50", 0x00000, 0x20000, CRC(5d05d6c6) SHA1(43bcf6dbfa982595154ebb2b478415b63dfcb7aa) )
+	ROM_LOAD16_BYTE( "c43-13.31", 0x00001, 0x20000, CRC(75b7d877) SHA1(54ffb35fdc84c86a3187291e2f1862a1a9152812) )
+	ROM_LOAD16_BYTE( "c43-14.49", 0x40000, 0x20000, CRC(ede7f37d) SHA1(3ed744885f2aaba5c4e6f4d77ed33d12f0290968) )
+	ROM_LOAD16_BYTE( "c43-12.30", 0x40001, 0x20000, CRC(b08a4ba0) SHA1(dad644bcaa240bf0d7393153ab0d0e9bf1d620b2) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c43-16",  0x00000, 0x10000, CRC(cb26fce1) SHA1(7cc60326455c7bb2ca543ddfd4002462cc079837) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "c43-02",  0x00000, 0x80000, CRC(105722ae) SHA1(1de5d396d2a4d5948544082c471a15ca1b8e756c) )
+	ROM_LOAD( "c43-03",  0x80000, 0x80000, CRC(426606ba) SHA1(961ec0a9dc18044adae433337bfa89d951c5207c) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "c43-01",  0x00000, 0x80000, CRC(db953f37) SHA1(252591b676366d4828acb20c77aa9960ad9b367e) )
+ROM_END
+
+ROM_START( ashuraj )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "c43-07-1.50", 0x00000, 0x20000, CRC(d5ceb20f) SHA1(59bc9468d7f43d3b1388c2915fafeba7e2cf13a5) )
+	ROM_LOAD16_BYTE( "c43-05-1.31", 0x00001, 0x20000, CRC(a6f3bb37) SHA1(6959f3bcbcd2d5b13c95dcfd7a536541dcab49f8) )
+	ROM_LOAD16_BYTE( "c43-06-1.49", 0x40000, 0x20000, CRC(0f331802) SHA1(e7ed01b0d664c4db6ea9acc54b57e674e10685aa) )
+	ROM_LOAD16_BYTE( "c43-04-1.30", 0x40001, 0x20000, CRC(e06a2414) SHA1(77ebe1e61b6303f328757de2c90fae6588026414) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c43-16",  0x00000, 0x10000, CRC(cb26fce1) SHA1(7cc60326455c7bb2ca543ddfd4002462cc079837) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "c43-02",  0x00000, 0x80000, CRC(105722ae) SHA1(1de5d396d2a4d5948544082c471a15ca1b8e756c) )
+	ROM_LOAD( "c43-03",  0x80000, 0x80000, CRC(426606ba) SHA1(961ec0a9dc18044adae433337bfa89d951c5207c) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "c43-01",  0x00000, 0x80000, CRC(db953f37) SHA1(252591b676366d4828acb20c77aa9960ad9b367e) )
+ROM_END
+
+ROM_START( ashurau )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "c43-11.50", 0x00000, 0x20000, CRC(d5aefc9b) SHA1(0fdfa166942ea70a77f956d16fd3b31225044c54) )
+	ROM_LOAD16_BYTE( "c43-09.31", 0x00001, 0x20000, CRC(e91d0ab1) SHA1(992f63ebba538e624c695c1a868b14f4baa66ab9) )
+	ROM_LOAD16_BYTE( "c43-10.49", 0x40000, 0x20000, CRC(c218e7ea) SHA1(d9b19ad26206238f8417efe3b80c020fea0dd573) )
+	ROM_LOAD16_BYTE( "c43-08.30", 0x40001, 0x20000, CRC(5ef4f19f) SHA1(864e3a4a4e92adaa63249debad6292c528289fbe) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c43-16",  0x00000, 0x10000, CRC(cb26fce1) SHA1(7cc60326455c7bb2ca543ddfd4002462cc079837) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "c43-02",  0x00000, 0x80000, CRC(105722ae) SHA1(1de5d396d2a4d5948544082c471a15ca1b8e756c) )
+	ROM_LOAD( "c43-03",  0x80000, 0x80000, CRC(426606ba) SHA1(961ec0a9dc18044adae433337bfa89d951c5207c) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "c43-01",  0x00000, 0x80000, CRC(db953f37) SHA1(252591b676366d4828acb20c77aa9960ad9b367e) )
+ROM_END
+
+ROM_START( tetrist ) // Nastar / Nastar Warrior / Rastan Saga 2 conversion with graphics and sound ROMs left in place
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "c12-03.50", 0x000000, 0x020000, CRC(38f1ed41) SHA1(d11194dd6686e6eba8c481bb0f9662041ca396ed) )
+	ROM_LOAD16_BYTE( "c12-02.31", 0x000001, 0x020000, CRC(ed9530bc) SHA1(84c324e4ef0c5c3af04ea000ad3e9c319bd9f2a2) )
+	ROM_LOAD16_BYTE( "c12-05.49", 0x040000, 0x020000, CRC(128e9927) SHA1(227b4a43074b66c9ba6f4497eb329fbcc5e3f52b) )
+	ROM_LOAD16_BYTE( "c12-04.30", 0x040001, 0x020000, CRC(5da7a319) SHA1(0c903b3274f6eafe24c8b5ef476dc5e8e3131b20) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c12-06.37", 0x00000, 0x10000, CRC(f2814b38) SHA1(846d3cc7a6f1cfbfd5661d6942f24330d21f91f0) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", ROMREGION_ERASE00 )
+
+	ROM_REGION( 0x100000, "gfx2", 0 )
+	/* b81-03.14 & b81-04.15 are present on the original board and are actually from Nastar
+	  the game doesn't use any tiles from here but the roms must be present on the board to avoid
+	  tile 0 being solid and obscuring the bitmap (however if we load them in the correct region
+	  unwanted tiles from here are shown after gameover which is wrong) - There is an undumped PAL
+	      C12-01 that controls this effect.
+	 */
+	ROM_LOAD( "b81-03.14", 0x000000, 0x080000, CRC(551b75e6) SHA1(5b8388ee2c6262f359c9e6d04c951ea8dc3901c9) )
+	ROM_LOAD( "b81-04.15", 0x080000, 0x080000, CRC(cf734e12) SHA1(4201a74468058761454515738fbf3a7b22a66e00) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "b81-02.2", 0x00000, 0x80000, CRC(20ec3b86) SHA1(fcdcc7f0a09feb824d8d73b1af0aae7ec30fd1ed) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcmb", 0 )
+	ROM_LOAD( "b81-01.1", 0x00000, 0x80000, CRC(b33f796b) SHA1(6cdb32f56283acdf20eb46a1e658e3bd7c97978c) )
+ROM_END
+
+ROM_START( tetrista ) // Master of Weapon conversion with graphics ROMs left in place
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "c35-04.33", 0x000000, 0x020000, CRC(fa6e42ff) SHA1(1c586243aaf57b46338f22ae0fcdba2897ccb98a) )
+	ROM_LOAD16_BYTE( "c35-03.24", 0x000001, 0x020000, CRC(aebd8539) SHA1(5230c0513581513ba971da55c04da8ba451a16e2) )
+	ROM_LOAD16_BYTE( "c35-02.34", 0x040000, 0x020000, CRC(128e9927) SHA1(227b4a43074b66c9ba6f4497eb329fbcc5e3f52b) ) // ==c12-05
+	ROM_LOAD16_BYTE( "c35-01.25", 0x040001, 0x020000, CRC(5da7a319) SHA1(0c903b3274f6eafe24c8b5ef476dc5e8e3131b20) ) // ==c12-04
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c35-05.30", 0x00000, 0x10000, CRC(785c63fb) SHA1(13db76d8ce52ff21bfda0866c9c6b52147c6fc9d) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", ROMREGION_ERASE00 )
+
+	ROM_REGION( 0x100000, "gfx2", 0 )
+	/* b72-01.5 & b72-02.6 are present on the original board and are actually from Master of Weapon
+	  the game doesn't use any tiles from here but the roms must be present on the board to avoid
+	  tile 0 being solid and obscuring the bitmap (however if we load them in the correct region
+	  unwanted tiles from here are shown after gameover which is wrong) - There is an undumped PAL
+	      C35-06 that controls this effect.
+	 */
+	ROM_LOAD( "b72-02.6", 0x000000, 0x080000, CRC(843444eb) SHA1(2b466045f882996c80e0090009ee957e11d32825) )
+	ROM_LOAD( "b72-01.5", 0x080000, 0x080000, CRC(a24ac26e) SHA1(895715a2bb0cb15334cba2283bd228b4fc08cd0c) )
+ROM_END
+
+ROM_START( hitice ) /* 4 Player version */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "c59-10.42", 0x00000, 0x20000, CRC(e4ffad15) SHA1(87da85e1489fe57bd012177a70434152e5475009) )
+	ROM_LOAD16_BYTE( "c59-12.64", 0x00001, 0x20000, CRC(a080d7af) SHA1(9c68b78fbcc42a2f748d1b7f84f138be79f7c0c9) )
+	ROM_LOAD16_BYTE( "c59-09.41", 0x40000, 0x10000, CRC(e243e3b0) SHA1(a7daf96ef70e9a92bb3ee4a151ce674a187c15a2) )
+	ROM_LOAD16_BYTE( "c59-11.63", 0x40001, 0x10000, CRC(4d4dfa52) SHA1(8ecd62dc2a2f35850340469afa54862b46053ce0) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c59-08.50",  0x00000, 0x10000, CRC(d3cbc10b) SHA1(75305e264300e0ebd15ada45a6d222fee75bd8e4) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "c59-03.12",  0x00000, 0x80000, CRC(9e513048) SHA1(4ffa63c01a25e912dd218b7b2deaf5ad1a53659a) )
+	ROM_LOAD( "c59-02.13",  0x80000, 0x80000, CRC(affb5e07) SHA1(afe92268c78ab5565d2913672e25f3136a15f534) )
+
+	ROM_REGION( 0x80000, "oki", 0 )
+	ROM_LOAD( "c59-01.30",  0x00000, 0x20000, CRC(46ae291d) SHA1(d36ab48cfa393a6a1eae5caa2a397087eb098f7f) )
+
+	ROM_REGION( 0x800, "plds", 0 )
+	ROM_LOAD( "pal20l8b-c59-04.25", 0x000, 0x144, CRC(2ebcf07c) SHA1(b73396fff8cde51e8a429843cd6dc3386f777f3b) )
+	ROM_LOAD( "pal16l8b-c59-05.26", 0x200, 0x104, CRC(37b67c5c) SHA1(a4bf3532774bcd285a6e0e24a9e9a3b28684f724) )
+	ROM_LOAD( "pal20l8b-c59-06.53", 0x400, 0x144, CRC(bf176875) SHA1(d7073ff7bf8f905dc8a6d3cf51543a572fa87f2f) )
+	ROM_LOAD( "pal16r4b-c59-07.61", 0x600, 0x104, CRC(cf64bd95) SHA1(5acada8bd6da40b5342bdd7ec494ee0e615492f0) )
+ROM_END
+
+ROM_START( hiticerb ) /* 4 Player version */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "c59-10.42", 0x00000, 0x20000, CRC(e4ffad15) SHA1(87da85e1489fe57bd012177a70434152e5475009) )
+	ROM_LOAD16_BYTE( "c59-12.64", 0x00001, 0x20000, CRC(a080d7af) SHA1(9c68b78fbcc42a2f748d1b7f84f138be79f7c0c9) )
+	ROM_LOAD16_BYTE( "c59-09.41", 0x40000, 0x10000, CRC(e243e3b0) SHA1(a7daf96ef70e9a92bb3ee4a151ce674a187c15a2) )
+	ROM_LOAD16_BYTE( "c59-11.63", 0x40001, 0x10000, CRC(4d4dfa52) SHA1(8ecd62dc2a2f35850340469afa54862b46053ce0) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c59-08.50",  0x00000, 0x10000, CRC(d3cbc10b) SHA1(75305e264300e0ebd15ada45a6d222fee75bd8e4) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD16_BYTE( "ic5.bin",  0x00000, 0x20000, CRC(55698bbc) SHA1(ba0e0de12e3e52ef026d37d667060e8ba6925340) )
+	ROM_LOAD16_BYTE( "ic1.bin",  0x40000, 0x20000, CRC(fca01c22) SHA1(94d7d521ea6fdab752939c1f2087b16a2b2922a8) )
+	ROM_LOAD16_BYTE( "ic6.bin",  0x00001, 0x20000, CRC(a7cb863f) SHA1(f749d38c2164bb9833e653bc1253a336c0043daa) )
+	ROM_LOAD16_BYTE( "ic2.bin",  0x40001, 0x20000, CRC(f1c09244) SHA1(68d67db5398c92699022f86fa53a1cbda344c375) )
+	ROM_LOAD16_BYTE( "ic8.bin",  0x80000, 0x20000, CRC(7cd3aa29) SHA1(78279db96b4f913b60a866d4fcbde46e5608fe0d) )
+	ROM_LOAD16_BYTE( "ic4.bin",  0xc0000, 0x20000, CRC(d0f2fd35) SHA1(e705e6d889a01bca6a33efcb36ef13a5f43bcd17) )
+	ROM_LOAD16_BYTE( "ic7.bin",  0x80001, 0x20000, CRC(6b2979c7) SHA1(6154cee3796aea637114a771e4c773013b28b362) )
+	ROM_LOAD16_BYTE( "ic3.bin",  0xc0001, 0x20000, CRC(51621004) SHA1(86980acdba4380f8682ace0e0f0543312304d451) )
+
+	ROM_REGION( 0x80000, "oki", 0 )
+	ROM_LOAD( "ic30.bin",  0x00000, 0x20000, CRC(46ae291d) SHA1(d36ab48cfa393a6a1eae5caa2a397087eb098f7f) )
+
+	ROM_REGION( 0x800, "plds", 0 )
+	ROM_LOAD( "pal20l8b-c59-04.25", 0x000, 0x144, CRC(2ebcf07c) SHA1(b73396fff8cde51e8a429843cd6dc3386f777f3b) )
+	ROM_LOAD( "pal16l8b-c59-05.26", 0x200, 0x104, CRC(37b67c5c) SHA1(a4bf3532774bcd285a6e0e24a9e9a3b28684f724) )
+	ROM_LOAD( "pal20l8b-c59-06.53", 0x400, 0x144, CRC(bf176875) SHA1(d7073ff7bf8f905dc8a6d3cf51543a572fa87f2f) )
+	ROM_LOAD( "pal16r4b-c59-07.61", 0x600, 0x104, CRC(cf64bd95) SHA1(5acada8bd6da40b5342bdd7ec494ee0e615492f0) )
+ROM_END
+
+ROM_START( hiticej ) /* 2 Player version */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "c59-23.42", 0x00000, 0x20000, CRC(01958fcc) SHA1(adaf9b0a4658d4d8eb8cdd343b40643b4c05d09e) )
+	ROM_LOAD16_BYTE( "c59-25.64", 0x00001, 0x20000, CRC(71984c76) SHA1(2e8bbfd01b0f229db5f10563a0864e8a2d1a515f) )
+	ROM_LOAD16_BYTE( "c59-22.41", 0x40000, 0x10000, CRC(c2c86140) SHA1(8d285a50786c91d28004a30854bbc40cf7d0de4b) )
+	ROM_LOAD16_BYTE( "c59-24.63", 0x40001, 0x10000, CRC(26c8f409) SHA1(c10f5504e4521c64e2410cef504ff7079c7d4e70) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c59-08.50",  0x00000, 0x10000, CRC(d3cbc10b) SHA1(75305e264300e0ebd15ada45a6d222fee75bd8e4) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "c59-03.12",  0x00000, 0x80000, CRC(9e513048) SHA1(4ffa63c01a25e912dd218b7b2deaf5ad1a53659a) )
+	ROM_LOAD( "c59-02.13",  0x80000, 0x80000, CRC(affb5e07) SHA1(afe92268c78ab5565d2913672e25f3136a15f534) )
+
+	ROM_REGION( 0x80000, "oki", 0 )
+	ROM_LOAD( "c59-01.30",  0x00000, 0x20000, CRC(46ae291d) SHA1(d36ab48cfa393a6a1eae5caa2a397087eb098f7f) )
+
+	ROM_REGION( 0x800, "plds", 0 )
+	ROM_LOAD( "pal20l8b-c59-04.25", 0x000, 0x144, CRC(2ebcf07c) SHA1(b73396fff8cde51e8a429843cd6dc3386f777f3b) )
+	ROM_LOAD( "pal16l8b-c59-05.26", 0x200, 0x104, CRC(37b67c5c) SHA1(a4bf3532774bcd285a6e0e24a9e9a3b28684f724) )
+	ROM_LOAD( "pal20l8b-c59-06.53", 0x400, 0x144, CRC(bf176875) SHA1(d7073ff7bf8f905dc8a6d3cf51543a572fa87f2f) )
+	ROM_LOAD( "pal16r4b-c59-07.61", 0x600, 0x104, CRC(cf64bd95) SHA1(5acada8bd6da40b5342bdd7ec494ee0e615492f0) )
+ROM_END
+
+ROM_START( rambo3 )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b93-11.rom0e.ic9",  0x00000, 0x20000, CRC(1cc42247) SHA1(e5a226a0016ec329fc23046c426c6303e452ef1d) )
+	ROM_LOAD16_BYTE( "b93-14.rom0o.ic23", 0x00001, 0x20000, CRC(7d917c21) SHA1(2850c46d6bdabfb76c40a7dc78ebc14b69ce95c9) )
+	ROM_LOAD16_BYTE( "b93-07.rom1e.ic8",  0x40000, 0x20000, CRC(c973ff6f) SHA1(d11f289f8559602783d97b831182e8c37954980f) )
+	ROM_LOAD16_BYTE( "b93-06-rom1o.ic22", 0x40001, 0x20000, CRC(a83d3fd5) SHA1(4f07d969af3b25e4ab8d0f2c03e0c0c8ada02991) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b93-10.ic36", 0x00000, 0x10000, CRC(b18bc020) SHA1(5f3a108ad1f652103dda14672223529077a0924b) )
+
+	ROM_REGION( 0x200000, "tc0180vcu", 0 )
+	ROM_LOAD( "b93-03.ic3",  0x000000, 0x80000, CRC(f5808c41) SHA1(73e129e87d7e240f96cb06d484fb19cd0ef49721) )
+	ROM_LOAD( "b93-04.ic4",  0x080000, 0x80000, CRC(c57831ce) SHA1(85c203a858df34fe8663b2b16447d328cdb4145e) )
+	ROM_LOAD( "b93-02.ic2",  0x100000, 0x80000, CRC(c55fcf54) SHA1(6a26ed2541be9e3341f20e74cc49b5366ce7d424) )
+	ROM_LOAD( "b93-01.ic1",  0x180000, 0x80000, CRC(9dd014c6) SHA1(0f046d9de57db0272810adde7d49cc348b78f1f7) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "b93-05.roma.ic46", 0x00000, 0x80000, CRC(0179dc40) SHA1(89feb708618ae7fa96883473d5c7a09dcc6f452a) )
+
+	ROM_REGION( 0x400, "plds", ROMREGION_ERASE00 )
+	ROM_LOAD( "b93-08-pal16l8b.ic11", 0x000, 0x104, CRC(6b1e5259) SHA1(47fd718680e7feadb20c45fbad0c3cb572d2937f) )
+	ROM_LOAD( "b93-09-pal16l8b.ic25", 0x200, 0x104, CRC(e63d9041) SHA1(4dcd6949825615b0c1370bea50e709da1b265a6c) )
+ROM_END
+
+ROM_START( rambo3u )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "ramb3-11.bin",  0x00000, 0x20000, CRC(1cc42247) SHA1(e5a226a0016ec329fc23046c426c6303e452ef1d) )
+	ROM_LOAD16_BYTE( "ramb3-13.bin",  0x00001, 0x20000, CRC(0a964cb7) SHA1(332fe23c33b1400c628e0c491f3e00820bde6696) )
+	ROM_LOAD16_BYTE( "ramb3-07.bin",  0x40000, 0x20000, CRC(c973ff6f) SHA1(d11f289f8559602783d97b831182e8c37954980f) )
+	ROM_LOAD16_BYTE( "ramb3-06.bin",  0x40001, 0x20000, CRC(a83d3fd5) SHA1(4f07d969af3b25e4ab8d0f2c03e0c0c8ada02991) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "ramb3-10.bin", 0x00000, 0x10000, CRC(b18bc020) SHA1(5f3a108ad1f652103dda14672223529077a0924b) )
+
+	ROM_REGION( 0x200000, "tc0180vcu", 0 )
+	ROM_LOAD( "ramb3-03.bin",  0x000000, 0x80000, CRC(f5808c41) SHA1(73e129e87d7e240f96cb06d484fb19cd0ef49721) )
+	ROM_LOAD( "ramb3-04.bin",  0x080000, 0x80000, CRC(c57831ce) SHA1(85c203a858df34fe8663b2b16447d328cdb4145e) )
+	ROM_LOAD( "ramb3-01.bin",  0x100000, 0x80000, CRC(c55fcf54) SHA1(6a26ed2541be9e3341f20e74cc49b5366ce7d424) )
+	ROM_LOAD( "ramb3-02.bin",  0x180000, 0x80000, CRC(9dd014c6) SHA1(0f046d9de57db0272810adde7d49cc348b78f1f7) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "ramb3-05.bin", 0x00000, 0x80000, CRC(0179dc40) SHA1(89feb708618ae7fa96883473d5c7a09dcc6f452a) )
+ROM_END
+
+ROM_START( rambo3p ) /* Is this set a prototype or possible bootleg? */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "r3-0e.rom",  0x00000, 0x10000, CRC(3efa4177) SHA1(5e4995e34b92f625f7825238dfbc9e76d4090871) )
+	ROM_LOAD16_BYTE( "r3-0o.rom",  0x00001, 0x10000, CRC(55c38d92) SHA1(4f712b4eb20ee176da83a5f1154d5890d1360398) )
+
+	/*NOTE: there is a hole in address space here */
+
+	ROM_LOAD16_BYTE( "r3-1e.rom" , 0x40000, 0x20000, CRC(40e363c7) SHA1(9907def4736fbff15cf769a762bf1811f890d1c7) )
+	ROM_LOAD16_BYTE( "r3-1o.rom" , 0x40001, 0x20000, CRC(7f1fe6ab) SHA1(31231747982d9c42f693f650bc137794b438c2b7) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "r3-00.rom", 0x00000, 0x10000, CRC(df7a6ed6) SHA1(68f7f17c9ead6aee653b02de234ec54b519907d7) )
+
+	ROM_REGION( 0x200000, "tc0180vcu", 0 )
+	ROM_LOAD16_BYTE( "r3-ch1ll.rom", 0x000000, 0x020000, CRC(c86ea5fc) SHA1(daf89340bb5d6ae57ef6faedb3f86c944c68fc45) )
+	ROM_LOAD16_BYTE( "r3-ch1hl.rom", 0x040000, 0x020000, CRC(7525eb92) SHA1(f691a000580d078f207ea6e9bc8a527e74bc20e5) )
+	ROM_LOAD16_BYTE( "r3-ch3ll.rom", 0x080000, 0x020000, CRC(abe54b1e) SHA1(4b6d0c694d9c1fcdec87b70fbadee9fb3455b42c) )
+	ROM_LOAD16_BYTE( "r3-ch3hl.rom", 0x0c0000, 0x020000, CRC(80e5647e) SHA1(744e9dcc651b80ef4b3cc29ed0ebb223bb65f106) )
+
+	ROM_LOAD16_BYTE( "r3-ch1lh.rom", 0x000001, 0x020000, CRC(75568cf0) SHA1(78cb940fafb6e01a018d6823636b398a898e988a) )
+	ROM_LOAD16_BYTE( "r3-ch1hh.rom", 0x040001, 0x020000, CRC(e39cff37) SHA1(79680526759013f8641e82c27b3afc184c06f059) )
+	ROM_LOAD16_BYTE( "r3-ch3lh.rom", 0x080001, 0x020000, CRC(5a155c04) SHA1(9472ef6474275ac5993c2afb222cfbc8d848bd86) )
+	ROM_LOAD16_BYTE( "r3-ch3hh.rom", 0x0c0001, 0x020000, CRC(abe58fdb) SHA1(6429caa8680255c46457ab0ad6c0f610291d8a92) )
+
+	ROM_LOAD16_BYTE( "r3-ch0ll.rom", 0x100000, 0x020000, CRC(b416f1bf) SHA1(8ae546c8286d616a991766eb97c3d281dbafd944) )
+	ROM_LOAD16_BYTE( "r3-ch0hl.rom", 0x140000, 0x020000, CRC(a4cad36d) SHA1(f8327bcc490cb66703de9bbcd931d964609ae822) )
+	ROM_LOAD16_BYTE( "r3-ch2ll.rom", 0x180000, 0x020000, CRC(d0ce3051) SHA1(0dc57f53b82d8ae15106df8a08b404c076b9fcef) )
+	ROM_LOAD16_BYTE( "r3-ch2hl.rom", 0x1c0000, 0x020000, CRC(837d8677) SHA1(6a3b36399e89c8ff031b25bcf62704197d711a5b) )
+
+	ROM_LOAD16_BYTE( "r3-ch0lh.rom", 0x100001, 0x020000, CRC(76a330a2) SHA1(4324bceca7bf5155f7b2543748989e2d364a7e97) )
+	ROM_LOAD16_BYTE( "r3-ch0hh.rom", 0x140001, 0x020000, CRC(4dc69751) SHA1(2abf657dc951dc263b53a2c7a4ed2f4aaf5f9a98) )
+	ROM_LOAD16_BYTE( "r3-ch2lh.rom", 0x180001, 0x020000, CRC(df3bc48f) SHA1(6747a453da4bca0b837f4ef1f1bbe871f15332ed) )
+	ROM_LOAD16_BYTE( "r3-ch2hh.rom", 0x1c0001, 0x020000, CRC(bf37dfac) SHA1(27e825bd0a4d7ae65714fefeb6fedac501984ba9) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "r3-a1.rom", 0x00000, 0x20000, CRC(4396fa19) SHA1(cb6d983f210249676c500723041d74fa3fdc517d) )
+	ROM_LOAD( "r3-a2.rom", 0x20000, 0x20000, CRC(41fe53a8) SHA1(1723046111d0115d3f64c3111c50d51306e88ad0) )
+	ROM_LOAD( "r3-a3.rom", 0x40000, 0x20000, CRC(e89249ba) SHA1(cd94492a0643e9e1e25b121160914822a6a7723e) )
+	ROM_LOAD( "r3-a4.rom", 0x60000, 0x20000, CRC(9cf4c21b) SHA1(756fc6bbc798a39a18eab3829e032cac8fe3f8ed) )
+ROM_END
+
+ROM_START( pbobble )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "pb-ic18.ic18", 0x00000, 0x40000, CRC(5de14f49) SHA1(91d537748f26e19a5c32de4b8dad341750de39ef) )
+	ROM_LOAD16_BYTE( "pb-ic2.ic2",   0x00001, 0x40000, CRC(2abe07d1) SHA1(2bb78b606a7341d74cced0447f8bd5ccc635cc4c) )
+
+	ROM_REGION( 0x20000, "audiocpu", 0 )     /* 128k for Z80 code */
+	ROM_LOAD( "pb-ic27.ic27", 0x00000, 0x20000, CRC(26efa4c4) SHA1(795af8f6d23c2cbe2c811ec9ab1f14a4eee3f99e) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "pb-ic14.ic14", 0x00000, 0x80000, CRC(55f90ea4) SHA1(793c79e5b72171124368ad09dd31235252c541f5) )
+	ROM_LOAD( "pb-ic9.ic9",   0x80000, 0x80000, CRC(3253aac9) SHA1(916d85aa96e2914630833292a0655b0389b4a39b) )
+
+	ROM_REGION( 0x100000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "pb-ic15.ic15", 0x000000, 0x100000, CRC(0840cbc4) SHA1(1adbd7aef44fa80832f63dfb8efdf69fd7256a57) )
+ROM_END
+
+ROM_START( bublbust ) // Purportedly a location test version, but has the same version number and build date as the released Japanese set below
+	ROM_REGION( 0x80000, "maincpu", 0 ) // 512k for 68000 code - located on Taito C0503005B main board
+	ROM_LOAD16_BYTE( "p.bobble_prg_h_kyotsu_6-15_c681.ic18", 0x00000, 0x40000, CRC(ba83e398) SHA1(2512ea5a805f0e5c470c4d216d679f3dc3c4aa82) ) // hand written label P.ボブル PRG H 共通 6/15 C681
+	ROM_LOAD16_BYTE( "p.bobble_prg_l_usa_6-15_e9e1.ic2",     0x00001, 0x40000, CRC(a12cb3f2) SHA1(06271d3a0af101a959e6e777f1f9e99bae1e6076) ) // hand written label P.ボブル PRG L USA 6/15 E9E1
+
+	ROM_REGION( 0x20000, "audiocpu", 0 ) // 128k for Z80 code - located on Taito C0503005B main board
+	ROM_LOAD( "prg_snd.ic27", 0x00000, 0x20000, CRC(2f288fe0) SHA1(4ba707f4b3a1ca0e573652d1c733ee889f9fef8a) ) // hand written label PRG SND IC 27 - no checksum listed
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 ) // located on Taito C0503002A ROM PCB
+	ROM_LOAD16_BYTE( "p.bobble_chr-1l_6-14_eaa0.ic11_ch_1_0l", 0x00000, 0x40000, CRC(8d3fa2f0) SHA1(3d36944e35081740469df61a40e538eb94ea2ef6) ) // hand written label P.ボブル CHR 1L 6/14 EAA0
+	ROM_LOAD16_BYTE( "p.bobble_chr-1h_6-14_1515.ic12_ch_1_0h", 0x00001, 0x40000, CRC(a2eb4d32) SHA1(571811a543af50cc5e0f1d7aad9fc388919e93e6) ) // hand written label P.ボブル CHR 1H 6/14 1515
+	ROM_LOAD16_BYTE( "p.bobble_chr-0l_6-14_86d5.ic7_ch_0_0l",  0x80000, 0x40000, CRC(80f1aab0) SHA1(f5cdb93aa702fb8ba91eaf8f470b6e2a61a581b5) ) // hand written label P.ボブル CHR 0L 6/14 86D5
+	ROM_LOAD16_BYTE( "p.bobble_chr-0h_6-14_d180.ic8_ch_0_0h",  0x80001, 0x40000, CRC(d773cac8) SHA1(b008a21c39650a28cba402cd1c4de0567e275bc9) ) // hand written label P.ボブル CHR 0H 6/14 D180 (label torn, checksum illegible besides final 0)
+
+	ROM_REGION( 0x100000, "ymsnd:adpcma", 0 ) // located on Taito C0503002A ROM PCB - Half the size of the Japanese ADPCMA sample ROM
+	ROM_LOAD( "cr40-kaigai-7bec.ic15_ach_0", 0x00000, 0x80000, CRC(f203ae52) SHA1(d41b880ef17eea6614e2911318db5cd070473381) ) // hand written label CR40 海外 7BEC
+ROM_END
+
+ROM_START( spacedx )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "d89-06.ic18", 0x00000, 0x40000, CRC(7122751e) SHA1(4b4eb58af28f1988ff102251407449d0affbd4c2) )
+	ROM_LOAD16_BYTE( "d89-xx.ic2",  0x00001, 0x40000, CRC(56b0be6c) SHA1(37e3e28a23fb4af35bdf7c751e4c3a743e505c46) ) // need to verify / correct ROM label
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "d89-07.ic27", 0x00000, 0x10000, CRC(bd743401) SHA1(bf1ff2255bbd79be21855814d52daced71fbe198) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "d89-02.ic14", 0x00000, 0x80000, CRC(c36544b9) SHA1(6bd5257dfb27532621b75f43e31aa351ad2192a2) )
+	ROM_LOAD( "d89-01.ic9",  0x80000, 0x80000, CRC(fffa0660) SHA1(de1abe1b1e9d14405b5663103ea4a6119fce7cc5) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )   /* ADPCM samples */
+	ROM_LOAD( "d89-03.ic15", 0x00000, 0x80000, CRC(218f31a4) SHA1(9f52b9fa8f02003888180524a6e9ee7c9230f55d) )
+
+	ROM_REGION( 0x0c00, "plds", 0 )
+	ROM_LOAD( "pal16l8-d72-05.ic37",   0x0000, 0x0104, CRC(c3d4cb7e) SHA1(1f3453a543dd98d02183595d66c67773fbf0ed07) ) /* Matches D72-05 in qzshowby */
+	ROM_LOAD( "pal16l8-d72-06.ic50",   0x0200, 0x0104, CRC(e96b7f37) SHA1(568087d0ab0ed55814deccc11630d3e26f765450) ) /* Differs from D72-06 in qzshowby */
+	ROM_LOAD( "palce20v8-d72-07.ic28", 0x0400, 0x0157, CRC(6359e64c) SHA1(83786f047aef591eb147a16a282f5312b36bc489) ) /* Matches D72-07 in qzshowby */
+	ROM_LOAD( "palce20v8-d72-09.ic47", 0x0600, 0x0157, CRC(de1760fd) SHA1(332156699408e5b0a698f031c01f8aa85c3d5d32) ) /* Differs from D72-09 in qzshowby */
+	ROM_LOAD( "palce16v8-d72-10.ic12", 0x0800, 0x0117, CRC(a5181ba2) SHA1(8315d6efa26be2ed98d4c0b39a196033789ab947) ) /* Matches D72-10 in qzshowby */
+	ROM_LOAD( "pal20l8b-d89-04.ic40",  0x0a00, 0x0144, NO_DUMP ) /* PAL is read protected */
+ROM_END
+
+ROM_START( spacedxj )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "d89-06.ic18", 0x00000, 0x40000, CRC(7122751e) SHA1(4b4eb58af28f1988ff102251407449d0affbd4c2) )
+	ROM_LOAD16_BYTE( "d89-05.ic2",  0x00001, 0x40000, CRC(be1638af) SHA1(5d28af674dd355159602e323800419a33e0b77d2) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "d89-07.ic27", 0x00000, 0x10000, CRC(bd743401) SHA1(bf1ff2255bbd79be21855814d52daced71fbe198) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "d89-02.ic14", 0x00000, 0x80000, CRC(c36544b9) SHA1(6bd5257dfb27532621b75f43e31aa351ad2192a2) )
+	ROM_LOAD( "d89-01.ic9" , 0x80000, 0x80000, CRC(fffa0660) SHA1(de1abe1b1e9d14405b5663103ea4a6119fce7cc5) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )   /* ADPCM samples */
+	ROM_LOAD( "d89-03.ic15", 0x00000, 0x80000, CRC(218f31a4) SHA1(9f52b9fa8f02003888180524a6e9ee7c9230f55d) )
+
+	ROM_REGION( 0x0c00, "plds", 0 )
+	ROM_LOAD( "pal16l8-d72-05.ic37",   0x0000, 0x0104, CRC(c3d4cb7e) SHA1(1f3453a543dd98d02183595d66c67773fbf0ed07) ) /* Matches D72-05 in qzshowby */
+	ROM_LOAD( "pal16l8-d72-06.ic50",   0x0200, 0x0104, CRC(e96b7f37) SHA1(568087d0ab0ed55814deccc11630d3e26f765450) ) /* Differs from D72-06 in qzshowby */
+	ROM_LOAD( "palce20v8-d72-07.ic28", 0x0400, 0x0157, CRC(6359e64c) SHA1(83786f047aef591eb147a16a282f5312b36bc489) ) /* Matches D72-07 in qzshowby */
+	ROM_LOAD( "palce20v8-d72-09.ic47", 0x0600, 0x0157, CRC(de1760fd) SHA1(332156699408e5b0a698f031c01f8aa85c3d5d32) ) /* Differs from D72-09 in qzshowby */
+	ROM_LOAD( "palce16v8-d72-10.ic12", 0x0800, 0x0117, CRC(a5181ba2) SHA1(8315d6efa26be2ed98d4c0b39a196033789ab947) ) /* Matches D72-10 in qzshowby */
+	ROM_LOAD( "pal20l8b-d89-04.ic40",  0x0a00, 0x0144, NO_DUMP ) /* PAL is read protected */
+ROM_END
+
+ROM_START( spacedxo ) // different PCB type, similar to Silent Dragon
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "d89-08.bin",  0x00000, 0x20000, CRC(0c2fe7f9) SHA1(a0773c059c8ff2c9e367e0fb460d7e5f9a762ab1) )
+	ROM_LOAD16_BYTE( "d89-09.bin",  0x00001, 0x20000, CRC(7f0a0ba4) SHA1(479df027929201997aeebbea5901a0a494f2dd61) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "d89-07.ic27", 0x00000, 0x10000, CRC(bd743401) SHA1(bf1ff2255bbd79be21855814d52daced71fbe198) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "d89-12.bin",0x00000, 0x80000, CRC(53df86f1) SHA1(f03d77dd54eb455462133a29dd8fec007abedcfd) )
+	ROM_LOAD( "d89-13.bin",0x80000, 0x80000, CRC(c44c1352) SHA1(78a04fe0ade6e8f9e6bbda7652a54a79b6208fdd) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )   /* ADPCM samples */
+	ROM_LOAD( "d89-03.ic15", 0x00000, 0x80000, CRC(218f31a4) SHA1(9f52b9fa8f02003888180524a6e9ee7c9230f55d) )
+ROM_END
+
+ROM_START( qzshowby )
+	ROM_REGION( 0x100000, "maincpu", 0 )     /* 1M for 68000 code */
+	ROM_LOAD16_BYTE( "d72-13.bin", 0x00000, 0x80000, CRC(a867759f) SHA1(ab06f42d58ae099fe5c1f810786c2a3e5a667e8e) )
+	ROM_LOAD16_BYTE( "d72-12.bin", 0x00001, 0x80000, CRC(522c09a7) SHA1(2ceeb7ac24bb621630cc996381e57501f9ea672e) )
+
+	ROM_REGION( 0x20000, "audiocpu", 0 )     /* 128k for Z80 code */
+	ROM_LOAD( "d72-11.bin", 0x00000, 0x20000, CRC(2ca046e2) SHA1(983620e657d729e1441d509f18141bb3bb581855) )
+
+	ROM_REGION( 0x400000, "tc0180vcu", 0 )
+	ROM_LOAD( "d72-03.bin", 0x000000, 0x200000, CRC(1de257d0) SHA1(df03b1fb5cd69e2d2eb2088f96f26b0ea9756fb7) )
+	ROM_LOAD( "d72-02.bin", 0x200000, 0x200000, CRC(bf0da640) SHA1(2b2493904ed0b94dc12b56dae71cc5c25701aef9) )
+
+	ROM_REGION( 0x200000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "d72-01.bin", 0x00000, 0x200000, CRC(b82b8830) SHA1(4b2dca16fe072a5ee51de5cf40637e3f1b39f695) )
+
+	ROM_REGION( 0x0c00, "plds", 0 )
+	ROM_LOAD( "pal16l8-d72-05.bin",   0x0000, 0x0104, CRC(c3d4cb7e) SHA1(1f3453a543dd98d02183595d66c67773fbf0ed07) )
+	ROM_LOAD( "pal16l8-d72-06.bin",   0x0200, 0x0104, CRC(27580efc) SHA1(11b3c0e2b344926dd068672a952574f06989d30a) ) /* This one or spacedx's D72-06 is a bad dump, should match */
+	ROM_LOAD( "palce20v8-d72-07.bin", 0x0400, 0x0157, CRC(6359e64c) SHA1(83786f047aef591eb147a16a282f5312b36bc489) )
+	ROM_LOAD( "palce20v8-d72-08.bin", 0x0600, 0x0157, CRC(746a6474) SHA1(f6c45ff53a01c03b1fc622dc161843b5faf0d2e4) )
+	ROM_LOAD( "palce20v8-d72-09.bin", 0x0800, 0x0157, CRC(9f680800) SHA1(2fa41ead85136e851d465432a7b9d3ec848c7a22) ) /* This one or spacedx's D72-09 is a bad dump, should match */
+	ROM_LOAD( "palce16v8-d72-10.bin", 0x0a00, 0x0117, CRC(a5181ba2) SHA1(8315d6efa26be2ed98d4c0b39a196033789ab947) )
+ROM_END
+
+ROM_START( viofight )
+	ROM_REGION( 0x080000, "maincpu", 0 )     /* 1M for 68000 code */
+	ROM_LOAD16_BYTE( "c16-11.42", 0x00000, 0x10000, CRC(23dbd388) SHA1(488f928826d16b201dcc4b491b09955d0af91f19) )
+	ROM_LOAD16_BYTE( "c16-14.23", 0x00001, 0x10000, CRC(dc934f6a) SHA1(36d7b10478f2b97d0521edb84f1f4fa5a11f962b) )
+	ROM_LOAD16_BYTE( "c16-07.41", 0x40000, 0x20000, CRC(64d1d059) SHA1(643ac7fa5076147b24810a8e1b925dfe09f75864) )
+	ROM_LOAD16_BYTE( "c16-06.22", 0x40001, 0x20000, CRC(043761d8) SHA1(4587cadd73b628b4b9ac5c537cec20f90fb4959d) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 128k for Z80 code */
+	ROM_LOAD( "c16-12.32", 0x00000, 0x10000, CRC(6fb028c7) SHA1(a808d82e872914f994652e95dca3fcad00ba02fc) )
+
+	ROM_REGION( 0x200000, "tc0180vcu", 0 )
+	// ROM dumps are confirmed good. Some bad GFX (MAME gfxdecode: 0000,0001, 1000,1001, 2000,2001, 3000,3001).
+	// See 3rd stage tiger fight background for example, see MT8048 for more information.
+	ROM_LOAD( "c16-01.1", 0x000000, 0x080000, CRC(7059ce83) SHA1(1e6825ab944254cd4ba6574762172245b3352319) )
+	ROM_LOAD( "c16-02.2", 0x080000, 0x080000, CRC(b458e905) SHA1(b712cbf4a4015e1fc2243871fe753e230f0172c2) )
+	ROM_LOAD( "c16-03.3", 0x100000, 0x080000, CRC(515a9431) SHA1(836be28614326d093be8841617cca83cef8d55cc) )
+	ROM_LOAD( "c16-04.4", 0x180000, 0x080000, CRC(ebf285e2) SHA1(0f806e42778e28e9687d85b2601ee08dd786869b) )
+
+	ROM_REGION( 0x80000, "oki", 0 )
+	ROM_LOAD( "c16-05.47", 0x000000, 0x80000, CRC(a49d064a) SHA1(f9ed675cfaae69b68c99c7dce7c2a457b5b5c293) )
+
+	ROM_REGION( 0x0400, "plds", 0 )
+	ROM_LOAD( "pal16l8b-c16-08.ic34", 0x0000, 0x0104, CRC(9456d278) SHA1(cd5986f260aac0ae1df1cea6dbd1dbee82536105) )
+	ROM_LOAD( "pal16l8b-c16-09.ic35", 0x0200, 0x0104, CRC(0965baab) SHA1(3f704cd42d5277e9ba0b0680a2722488fc4cc630) )
+ROM_END
+
+ROM_START( viofightu )
+	ROM_REGION( 0x080000, "maincpu", 0 )     /* 1M for 68000 code */
+	ROM_LOAD16_BYTE( "c16-11.42", 0x00000, 0x10000, CRC(23dbd388) SHA1(488f928826d16b201dcc4b491b09955d0af91f19) )
+	ROM_LOAD16_BYTE( "c16-13.23", 0x00001, 0x10000, CRC(ab947ffc) SHA1(103023cee4b20afa5086ba60522ea5aa723aebef) )
+	ROM_LOAD16_BYTE( "c16-07.41", 0x40000, 0x20000, CRC(64d1d059) SHA1(643ac7fa5076147b24810a8e1b925dfe09f75864) )
+	ROM_LOAD16_BYTE( "c16-06.22", 0x40001, 0x20000, CRC(043761d8) SHA1(4587cadd73b628b4b9ac5c537cec20f90fb4959d) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 128k for Z80 code */
+	ROM_LOAD( "c16-12.32", 0x00000, 0x10000, CRC(6fb028c7) SHA1(a808d82e872914f994652e95dca3fcad00ba02fc) )
+
+	ROM_REGION( 0x200000, "tc0180vcu", 0 )
+	ROM_LOAD( "c16-01.1", 0x000000, 0x080000, CRC(7059ce83) SHA1(1e6825ab944254cd4ba6574762172245b3352319) )
+	ROM_LOAD( "c16-02.2", 0x080000, 0x080000, CRC(b458e905) SHA1(b712cbf4a4015e1fc2243871fe753e230f0172c2) )
+	ROM_LOAD( "c16-03.3", 0x100000, 0x080000, CRC(515a9431) SHA1(836be28614326d093be8841617cca83cef8d55cc) )
+	ROM_LOAD( "c16-04.4", 0x180000, 0x080000, CRC(ebf285e2) SHA1(0f806e42778e28e9687d85b2601ee08dd786869b) )
+
+	ROM_REGION( 0x80000, "oki", 0 )
+	ROM_LOAD( "c16-05.47", 0x000000, 0x80000, CRC(a49d064a) SHA1(f9ed675cfaae69b68c99c7dce7c2a457b5b5c293) )
+
+	ROM_REGION( 0x00400, "plds", 0 )
+	ROM_LOAD( "pal16l8b-c16-08.ic34", 0x0000, 0x0104, CRC(9456d278) SHA1(cd5986f260aac0ae1df1cea6dbd1dbee82536105) )
+	ROM_LOAD( "pal16l8b-c16-09.ic35", 0x0200, 0x0104, CRC(0965baab) SHA1(3f704cd42d5277e9ba0b0680a2722488fc4cc630) )
+ROM_END
+
+ROM_START( viofightj )
+	ROM_REGION( 0x080000, "maincpu", 0 )     /* 1M for 68000 code */
+	ROM_LOAD16_BYTE( "c16-11.42", 0x00000, 0x10000, CRC(23dbd388) SHA1(488f928826d16b201dcc4b491b09955d0af91f19) )
+	ROM_LOAD16_BYTE( "c16-10.23", 0x00001, 0x10000, CRC(329d2e46) SHA1(044e8a283e3bdd3d64dbeb9b6982088e967b10ff) )
+	ROM_LOAD16_BYTE( "c16-07.41", 0x40000, 0x20000, CRC(64d1d059) SHA1(643ac7fa5076147b24810a8e1b925dfe09f75864) )
+	ROM_LOAD16_BYTE( "c16-06.22", 0x40001, 0x20000, CRC(043761d8) SHA1(4587cadd73b628b4b9ac5c537cec20f90fb4959d) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 128k for Z80 code */
+	ROM_LOAD( "c16-12.32", 0x00000, 0x10000, CRC(6fb028c7) SHA1(a808d82e872914f994652e95dca3fcad00ba02fc) )
+
+	ROM_REGION( 0x200000, "tc0180vcu", 0 )
+	ROM_LOAD( "c16-01.1", 0x000000, 0x080000, CRC(7059ce83) SHA1(1e6825ab944254cd4ba6574762172245b3352319) )
+	ROM_LOAD( "c16-02.2", 0x080000, 0x080000, CRC(b458e905) SHA1(b712cbf4a4015e1fc2243871fe753e230f0172c2) )
+	ROM_LOAD( "c16-03.3", 0x100000, 0x080000, CRC(515a9431) SHA1(836be28614326d093be8841617cca83cef8d55cc) )
+	ROM_LOAD( "c16-04.4", 0x180000, 0x080000, CRC(ebf285e2) SHA1(0f806e42778e28e9687d85b2601ee08dd786869b) )
+
+	ROM_REGION( 0x80000, "oki", 0 )
+	ROM_LOAD( "c16-05.47", 0x000000, 0x80000, CRC(a49d064a) SHA1(f9ed675cfaae69b68c99c7dce7c2a457b5b5c293) )
+
+	ROM_REGION( 0x00400, "plds", 0 )
+	ROM_LOAD( "pal16l8b-c16-08.ic34", 0x0000, 0x0104, CRC(9456d278) SHA1(cd5986f260aac0ae1df1cea6dbd1dbee82536105) )
+	ROM_LOAD( "pal16l8b-c16-09.ic35", 0x0200, 0x0104, CRC(0965baab) SHA1(3f704cd42d5277e9ba0b0680a2722488fc4cc630) )
+ROM_END
+
+ROM_START( masterw )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b72_06.33", 0x00000, 0x20000, CRC(ae848eff) SHA1(8715e64c5e03097aff5bf1a27e3809619a7731f0) )
+	ROM_LOAD16_BYTE( "b72_12.24", 0x00001, 0x20000, CRC(7176ce70) SHA1(f3462ab9fe7e118b16fbe31d8caca27452280bf9) )
+	ROM_LOAD16_BYTE( "b72_04.34", 0x40000, 0x20000, CRC(141e964c) SHA1(324e881317a3bf9885c81bb53cdc3de782ec2952) )
+	ROM_LOAD16_BYTE( "b72_03.25", 0x40001, 0x20000, CRC(f4523496) SHA1(2c3e9d014ace1ae5127f432292f8d19c3a0ae1b0) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b72_07.30", 0x00000, 0x10000, CRC(2b1a946f) SHA1(cc9512e44bd92020ab5a53716b6399b7a6cde76d) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b72-02.6", 0x000000, 0x080000, CRC(843444eb) SHA1(2b466045f882996c80e0090009ee957e11d32825) )
+	ROM_LOAD( "b72-01.5", 0x080000, 0x080000, CRC(a24ac26e) SHA1(895715a2bb0cb15334cba2283bd228b4fc08cd0c) )
+
+	ROM_REGION( 0x00600, "plds", 0 )
+	ROM_LOAD( "b72-08.ic3",  0x0000, 0x0104, CRC(1501a44a) SHA1(4dcda59238f17ce9d8654c27f45e217e6460fc03) )
+	ROM_LOAD( "b72-09.ic23", 0x0200, 0x0104, CRC(a1d19d49) SHA1(5ca983147ef57240f6b6a05a07a821f72bb13001) )
+	ROM_LOAD( "b72-10.ic32", 0x0400, 0x0104, CRC(20b0450b) SHA1(235ebbfd5b4cd179bb4d87e30d0e449028bb1df6) )
+ROM_END
+
+ROM_START( masterwu )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b72_06.33", 0x00000, 0x20000, CRC(ae848eff) SHA1(8715e64c5e03097aff5bf1a27e3809619a7731f0) )
+	ROM_LOAD16_BYTE( "b72_11.24", 0x00001, 0x20000, CRC(0671fee6) SHA1(6bec65d5e6704b4ec62c91f814675841ae9316a0) )
+	ROM_LOAD16_BYTE( "b72_04.34", 0x40000, 0x20000, CRC(141e964c) SHA1(324e881317a3bf9885c81bb53cdc3de782ec2952) )
+	ROM_LOAD16_BYTE( "b72_03.25", 0x40001, 0x20000, CRC(f4523496) SHA1(2c3e9d014ace1ae5127f432292f8d19c3a0ae1b0) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b72_07.30", 0x00000, 0x10000, CRC(2b1a946f) SHA1(cc9512e44bd92020ab5a53716b6399b7a6cde76d) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b72-02.6", 0x000000, 0x080000, CRC(843444eb) SHA1(2b466045f882996c80e0090009ee957e11d32825) )
+	ROM_LOAD( "b72-01.5", 0x080000, 0x080000, CRC(a24ac26e) SHA1(895715a2bb0cb15334cba2283bd228b4fc08cd0c) )
+
+	ROM_REGION( 0x00600, "plds", 0 )
+	ROM_LOAD( "b72-08.ic3",  0x0000, 0x0104, CRC(1501a44a) SHA1(4dcda59238f17ce9d8654c27f45e217e6460fc03) )
+	ROM_LOAD( "b72-09.ic23", 0x0200, 0x0104, CRC(a1d19d49) SHA1(5ca983147ef57240f6b6a05a07a821f72bb13001) )
+	ROM_LOAD( "b72-10.ic32", 0x0400, 0x0104, CRC(20b0450b) SHA1(235ebbfd5b4cd179bb4d87e30d0e449028bb1df6) )
+ROM_END
+
+ROM_START( masterwj )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "b72_06.33", 0x00000, 0x20000, CRC(ae848eff) SHA1(8715e64c5e03097aff5bf1a27e3809619a7731f0) )
+	ROM_LOAD16_BYTE( "b72_05.24", 0x00001, 0x20000, CRC(9f78af5c) SHA1(5f3ca663c7257f5cec071907b1526fff3ab07b20) )
+	ROM_LOAD16_BYTE( "b72_04.34", 0x40000, 0x20000, CRC(141e964c) SHA1(324e881317a3bf9885c81bb53cdc3de782ec2952) )
+	ROM_LOAD16_BYTE( "b72_03.25", 0x40001, 0x20000, CRC(f4523496) SHA1(2c3e9d014ace1ae5127f432292f8d19c3a0ae1b0) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "b72_07.30", 0x00000, 0x10000, CRC(2b1a946f) SHA1(cc9512e44bd92020ab5a53716b6399b7a6cde76d) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "b72-02.6", 0x000000, 0x080000, CRC(843444eb) SHA1(2b466045f882996c80e0090009ee957e11d32825) )
+	ROM_LOAD( "b72-01.5", 0x080000, 0x080000, CRC(a24ac26e) SHA1(895715a2bb0cb15334cba2283bd228b4fc08cd0c) )
+
+	ROM_REGION( 0x00600, "plds", 0 )
+	ROM_LOAD( "b72-08.ic3",  0x0000, 0x0104, CRC(1501a44a) SHA1(4dcda59238f17ce9d8654c27f45e217e6460fc03) )
+	ROM_LOAD( "b72-09.ic23", 0x0200, 0x0104, CRC(a1d19d49) SHA1(5ca983147ef57240f6b6a05a07a821f72bb13001) )
+	ROM_LOAD( "b72-10.ic32", 0x0400, 0x0104, CRC(20b0450b) SHA1(235ebbfd5b4cd179bb4d87e30d0e449028bb1df6) )
+ROM_END
+
+ROM_START( yukiwo ) /* Prototype of Master of Weapon */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 512k for 68000 code */
+	ROM_LOAD16_BYTE( "ic33-rom0e.bin", 0x00000, 0x20000, CRC(a0dd51d9) SHA1(a4740bf08e26e1e576344c95d945df5d970738f2) )
+	ROM_LOAD16_BYTE( "ic24-e882.bin",  0x00001, 0x20000, CRC(d66f29d4) SHA1(0854f1a0943a20693e6cd02825666e39b4fe28ca) )
+	ROM_LOAD16_BYTE( "ic34-rom1e.bin", 0x40000, 0x10000, CRC(5ab7bc95) SHA1(393edefda5657853dccc21fa7848239789dbca65) )
+	ROM_LOAD16_BYTE( "ic25-rom10.bin", 0x40001, 0x10000, CRC(0571b986) SHA1(aba9ac5fa4bd86cfa037baf34980b6a72417836b) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "ic30-snd.bin", 0x00000, 0x08000, CRC(8632adb7) SHA1(a746ed0e7e2c2c216874b5729d59d7ed37689e4f) ) // TMM27256AD-20
+	ROM_RELOAD(0x8000, 0x8000)
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD16_BYTE( "ic1-a010.bin", 0x000001, 0x020000, CRC(0030dce2) SHA1(649e0caf83b259814e1f0c2f6de40ebd8ea1a639) )
+	ROM_LOAD16_BYTE( "ic5-9df1.bin", 0x000000, 0x020000, CRC(0507b908) SHA1(72f9913ddec37cd4e6b0b611619d0195302eb7e8) )
+	ROM_LOAD16_BYTE( "ic3-1305.bin", 0x080001, 0x020000, CRC(8772b1a6) SHA1(961c8da0fcc3ce9dd334d7bcae75d8b93ded0bb4) )
+	ROM_LOAD16_BYTE( "ic7-7c16.bin", 0x080000, 0x020000, CRC(a366bffd) SHA1(0b68163c73a8a020edbcd016b175d269ce2ad825) )
+	ROM_LOAD16_BYTE( "ic2-6588.bin", 0x040001, 0x020000, CRC(25e79bc2) SHA1(f5b88ced9816338f45eb3430f7df0ecd5326321d) )
+	ROM_LOAD16_BYTE( "ic6-6f3f.bin", 0x040000, 0x020000, CRC(77afcf80) SHA1(93886ad1bddc3bce578f575598e55bdd6e31c5ee) )
+	ROM_LOAD16_BYTE( "ic4-9e5e.bin", 0x0c0001, 0x020000, CRC(3b30166b) SHA1(9450bcd30cf903cc0ae6c5f1cf2735ddd457e5f0) )
+	ROM_LOAD16_BYTE( "ic8-e28a.bin", 0x0c0000, 0x020000, CRC(1b3db354) SHA1(a8481799182e5a06e105a4600679d4544317a350) )
+ROM_END
+
+ROM_START( silentd ) /* Silkscreened PCB number ET910000B */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "east-12-1.ic32", 0x00000, 0x20000, CRC(5883d362) SHA1(21c3af053fa92c26f119466ecd655697cc72ff3a) )
+	ROM_LOAD16_BYTE( "east-15-1.ic10", 0x00001, 0x20000, CRC(8c0a72ae) SHA1(2199c4d6b87913ffb24cdccd6ca5176a97132baa) )
+	ROM_LOAD16_BYTE( "east-11.ic31",   0x40000, 0x20000, CRC(35da4428) SHA1(5374bd97ad58aa2d67404cb05c862bb3aba40d6a) )
+	ROM_LOAD16_BYTE( "east-09.ic9",    0x40001, 0x20000, CRC(2f05b14a) SHA1(f9ae935612e95d8ac2596af1728a6062569e9a42) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "east-13.ic15", 0x00000, 0x10000, CRC(651861ab) SHA1(f94a120b70a4d59e17a6e120ca461b1f37587c0c) )
+
+	ROM_REGION( 0x400000, "tc0180vcu", 0 )
+	ROM_LOAD( "east-04.ic28", 0x000000, 0x100000, CRC(53237217) SHA1(fec044c26b8c99235f88c8be0d9ac63b81a3a094) )
+	ROM_LOAD( "east-06.ic29", 0x100000, 0x100000, CRC(e6e6dfa7) SHA1(913fa9a21cea175a1af87023144ebc98b3b0f33b) )
+	ROM_LOAD( "east-03.ic39", 0x200000, 0x100000, CRC(1b9b2846) SHA1(d9c87e130bc3baa949d8a8738daad648fcf284df) )
+	ROM_LOAD( "east-05.ic40", 0x300000, 0x100000, CRC(e02472c5) SHA1(35572610f6823ec980a928a75abd689197ebe207) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "east-01.ic1", 0x00000, 0x80000, CRC(b41fff1a) SHA1(54920d13fa2b3000eedab9d0050a299ae743c663) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcmb", 0 )
+	ROM_LOAD( "east-02.ic3", 0x00000, 0x80000, CRC(e0de5c39) SHA1(75d0e193d882e67921c216c3293454e34304d25e) )
+ROM_END
+
+ROM_START( silentdj ) /* Silkscreened PCB number ET910000B */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "east-12-1.ic32", 0x00000, 0x20000, CRC(5883d362) SHA1(21c3af053fa92c26f119466ecd655697cc72ff3a) )
+	ROM_LOAD16_BYTE( "east-10-1.ic10", 0x00001, 0x20000, CRC(584306fc) SHA1(961cb6aaa426e3d83c499d101ef369b86a84c5d8) )
+	ROM_LOAD16_BYTE( "east-11.ic31",   0x40000, 0x20000, CRC(35da4428) SHA1(5374bd97ad58aa2d67404cb05c862bb3aba40d6a) )
+	ROM_LOAD16_BYTE( "east-09.ic9",    0x40001, 0x20000, CRC(2f05b14a) SHA1(f9ae935612e95d8ac2596af1728a6062569e9a42) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "east-13.ic15", 0x00000, 0x10000, CRC(651861ab) SHA1(f94a120b70a4d59e17a6e120ca461b1f37587c0c) )
+
+	ROM_REGION( 0x400000, "tc0180vcu", 0 )
+	ROM_LOAD( "east-04.ic28", 0x000000, 0x100000, CRC(53237217) SHA1(fec044c26b8c99235f88c8be0d9ac63b81a3a094) )
+	ROM_LOAD( "east-06.ic29", 0x100000, 0x100000, CRC(e6e6dfa7) SHA1(913fa9a21cea175a1af87023144ebc98b3b0f33b) )
+	ROM_LOAD( "east-03.ic39", 0x200000, 0x100000, CRC(1b9b2846) SHA1(d9c87e130bc3baa949d8a8738daad648fcf284df) )
+	ROM_LOAD( "east-05.ic40", 0x300000, 0x100000, CRC(e02472c5) SHA1(35572610f6823ec980a928a75abd689197ebe207) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "east-01.ic1", 0x00000, 0x80000, CRC(b41fff1a) SHA1(54920d13fa2b3000eedab9d0050a299ae743c663) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcmb", 0 )
+	ROM_LOAD( "east-02.ic3", 0x00000, 0x80000, CRC(e0de5c39) SHA1(75d0e193d882e67921c216c3293454e34304d25e) )
+ROM_END
+
+ROM_START( silentdu ) /* Dumped from an original Taito PCB (ET910000B) */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "east-12-1.ic32", 0x00000, 0x20000, CRC(5883d362) SHA1(21c3af053fa92c26f119466ecd655697cc72ff3a) )
+	ROM_LOAD16_BYTE( "east-14-1.ic10", 0x00001, 0x20000, CRC(3267bcd5) SHA1(358a717d0cdd22d84eb0d928c36e4e72a40c2882) )
+	ROM_LOAD16_BYTE( "east-11.ic31",   0x40000, 0x20000, CRC(35da4428) SHA1(5374bd97ad58aa2d67404cb05c862bb3aba40d6a) )
+	ROM_LOAD16_BYTE( "east-09.ic9",    0x40001, 0x20000, CRC(2f05b14a) SHA1(f9ae935612e95d8ac2596af1728a6062569e9a42) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "east-13.ic15", 0x00000, 0x10000, CRC(651861ab) SHA1(f94a120b70a4d59e17a6e120ca461b1f37587c0c) )
+
+	ROM_REGION( 0x400000, "tc0180vcu", 0 )
+	ROM_LOAD( "east-04.ic28", 0x000000, 0x100000, CRC(53237217) SHA1(fec044c26b8c99235f88c8be0d9ac63b81a3a094) )
+	ROM_LOAD( "east-06.ic29", 0x100000, 0x100000, CRC(e6e6dfa7) SHA1(913fa9a21cea175a1af87023144ebc98b3b0f33b) )
+	ROM_LOAD( "east-03.ic39", 0x200000, 0x100000, CRC(1b9b2846) SHA1(d9c87e130bc3baa949d8a8738daad648fcf284df) )
+	ROM_LOAD( "east-05.ic40", 0x300000, 0x100000, CRC(e02472c5) SHA1(35572610f6823ec980a928a75abd689197ebe207) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )
+	ROM_LOAD( "east-01.ic1", 0x00000, 0x80000, CRC(b41fff1a) SHA1(54920d13fa2b3000eedab9d0050a299ae743c663) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcmb", 0 )
+	ROM_LOAD( "east-02.ic3", 0x00000, 0x80000, CRC(e0de5c39) SHA1(75d0e193d882e67921c216c3293454e34304d25e) )
+ROM_END
+
+ROM_START( selfeena ) /* Silkscreened PCB number ET910000A */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "se-02.27", 0x00000, 0x20000, CRC(08f0c8e3) SHA1(2279ebfcd0cd05eec9c7a01ca7db82fcdc3b7ca7) )
+	ROM_LOAD16_BYTE( "se-01.26", 0x00001, 0x20000, CRC(a06ca64b) SHA1(6bfd3c5faf169678ba9bb1c483901b6c06605faf) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "se-03.39",0x00000, 0x10000, CRC(675998be) SHA1(16e59a9b7dc46aeee0022cb73cf6feced6796c35) )
+
+	ROM_REGION( 0x100000, "tc0180vcu", 0 )
+	ROM_LOAD( "se-04.2",  0x000000, 0x80000, CRC(920ad100) SHA1(69cd2af6218db90632f09a131d2956ab69034643) )
+	ROM_LOAD( "se-05.1",  0x080000, 0x80000, CRC(d297c995) SHA1(e5ad5a8ce222621c9156c2949916bee6b3099c4e) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )   /* ADPCM samples */
+	ROM_LOAD( "se-06.11", 0x00000, 0x80000, CRC(80d5e772) SHA1(bee4982a3d65210ff86495e36a0b656934b00c7d) )
+ROM_END
+
+ROM_START( ryujin ) /* Silkscreened PCB number ET910000B */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "rjn_02.ic32", 0x00000, 0x20000, CRC(5fd353d5) SHA1(76c5e173f5945f9d69f805961ffc190f4f1532d7) ) /* Yes!, these were labeled RJN 02 & RJN 01 (unlike the rest labeled RUJ xx) */
+	ROM_LOAD16_BYTE( "rjn_01.ic10", 0x00001, 0x20000, CRC(f775e4b6) SHA1(1b85b217daf4784e35e0beb088bee229244f1207) )
+	ROM_LOAD16_BYTE( "ruj_04.ic31", 0x40000, 0x20000, CRC(0c153cab) SHA1(16fac3863c1394c9f41173174a4aca20cded6278) ) /* ET910000B PCB uses different IC locations */
+	ROM_LOAD16_BYTE( "ruj_03.ic9",  0x40001, 0x20000, CRC(7695f89c) SHA1(755eb7ef40da190d55de80ee5e0e0a537c22e5f1) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "ruj_05.ic15",0x00000, 0x10000, CRC(95270b16) SHA1(c1ad76268679cf198e9f1514360f280b73e49ab5) )
+
+	ROM_REGION( 0x200000, "tc0180vcu", 0 )
+	ROM_LOAD( "ryujin-07.ic28", 0x000000, 0x100000, CRC(34f50980) SHA1(432384bd283389bca17611602eb310726c9d78a4) )
+	ROM_LOAD( "ryujin-06.ic39", 0x100000, 0x100000, CRC(1b85ff34) SHA1(5ad259e6f7aa4a0c08975da73bf41400495f2e61) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )   /* ADPCM samples */
+	ROM_LOAD( "ryujin-08.ic1", 0x00000, 0x80000, CRC(480d040d) SHA1(50add2f304ef34f7f45f25a2a2cf0568d58259ad) )
+
+	ROM_REGION( 0x00400, "plds", 0 )
+	ROM_LOAD( "pal16l8b-east-07.ic46", 0x0000, 0x0104, CRC(0cb80f64) SHA1(53c38fc795d05277172391d7994c96d8c66b49c4) )
+	ROM_LOAD( "pal16l8b-east-08.ic47", 0x0200, 0x0104, CRC(bdce045f) SHA1(cc67b2afa1b57345a4b91f5fafd99cae5286827a) )
+ROM_END
+
+ROM_START( ryujina ) /* Silkscreened PCB number ET910000A */
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "ruj_02.27", 0x00000, 0x20000, CRC(0d223aee) SHA1(33f5498a650b244c5a4a22415408a269da597abf) )
+	ROM_LOAD16_BYTE( "ruj_01.26", 0x00001, 0x20000, CRC(c6bcdd1e) SHA1(d8620995ad1bc256eab4ed7e1c549e8b6ec5c3fb) )
+	ROM_LOAD16_BYTE( "ruj_04.29", 0x40000, 0x20000, CRC(0c153cab) SHA1(16fac3863c1394c9f41173174a4aca20cded6278) )
+	ROM_LOAD16_BYTE( "ruj_03.28", 0x40001, 0x20000, CRC(7695f89c) SHA1(755eb7ef40da190d55de80ee5e0e0a537c22e5f1) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "ruj_05.39",0x00000, 0x10000, CRC(95270b16) SHA1(c1ad76268679cf198e9f1514360f280b73e49ab5) )
+
+	ROM_REGION( 0x200000, "tc0180vcu", 0 )
+	ROM_LOAD( "ryujin-07.2", 0x000000, 0x100000, CRC(34f50980) SHA1(432384bd283389bca17611602eb310726c9d78a4) )
+	ROM_LOAD( "ryujin-06.1", 0x100000, 0x100000, CRC(1b85ff34) SHA1(5ad259e6f7aa4a0c08975da73bf41400495f2e61) )
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )   /* ADPCM samples */
+	ROM_LOAD( "ryujin-08.11", 0x00000, 0x80000, CRC(480d040d) SHA1(50add2f304ef34f7f45f25a2a2cf0568d58259ad) )
+ROM_END
+
+ROM_START( sbm )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "c69-20-2.ic10", 0x00000, 0x20000, CRC(225952a3) SHA1(d95ef971929d4a8c19193e80499052f57d205001) )
+	ROM_LOAD16_BYTE( "c69-22-2.ic12", 0x00001, 0x20000, CRC(d900ce83) SHA1(b86c3e7c2f9f2dbd415b7a355e5978de46fc3564) )
+	ROM_LOAD16_BYTE( "c69-19-2.ic9" , 0x40000, 0x20000, CRC(d6cfacfb) SHA1(0f910e92a81e0d7ac35d0ffc799dd723f64d47d1) )
+	ROM_LOAD16_BYTE( "c69-25-2.ic11", 0x40001, 0x20000, CRC(70903898) SHA1(879412e3c385533fd0bf1e47956e3e9bea78378d) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c69-31.ic28",0x00000, 0x10000, CRC(c999f753) SHA1(5d944b492893a0bb605743e2928c802427a85fbf) )
+
+	ROM_REGION( 0x400000, "tc0180vcu", 0 )
+	ROM_LOAD       ( "c69-01.ic5", 0x000000, 0x100000, CRC(521fabe3) SHA1(f81303688ac014145a7e9325affc4a0f86755ba9) )
+	ROM_LOAD16_BYTE( "c69-13.ic2", 0x100000, 0x020000, CRC(d1550884) SHA1(f3a65827c45959fe5ac4bfc92831a8bed76bf287) )
+	ROM_LOAD16_BYTE( "c69-12.ic1", 0x100001, 0x020000, CRC(eb56582c) SHA1(41b77704aeaecf3eaa3f87e97c0b59fd00e5349e) )
+	/* 140000-1fffff empty */
+	ROM_LOAD       ( "c69-02.ic6", 0x200000, 0x100000, CRC(f0e20d35) SHA1(af67f39498f68523ece4cd91045456092038e0a4) )
+	ROM_LOAD16_BYTE( "c69-15.ic4", 0x300000, 0x020000, CRC(9761d316) SHA1(f03216bbade96948ff433a925e8bffb8760b4101) )
+	ROM_LOAD16_BYTE( "c69-14.ic3", 0x300001, 0x020000, CRC(0ed0272a) SHA1(03b15654213ff71ffc96d3a87657bdeb724e9269) )
+	/* 340000-3fffff empty */
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )   /* ADPCM samples */
+	ROM_LOAD( "c69-26.ic36", 0x00000, 0x80000, CRC(8784058b) SHA1(c3d9c620704fb5e80719e996e97f6191a5bd9f8c) )
+
+	ROM_REGION( 0x1800, "plds", 0 )
+	ROM_LOAD( "c69-04.ic6",  0x000, 0x104, CRC(80498715) SHA1(076c26f365b74f3b6adb2c4c1a3add5a46a257ea) ) // 16l8
+	ROM_LOAD( "c69-05.ic25", 0x200, 0x104, CRC(35e345b4) SHA1(befbea944c645dafb143d8dba83fcc16f1edd3e6) ) // 16l8
+	ROM_LOAD( "c69-06.ic17", 0x400, 0x144, CRC(3988e5d1) SHA1(24e03455fd9e653e3fc901bef2c3f3ea59f04ea5) ) // 20l8
+ROM_END
+
+ROM_START( sbmj )
+	ROM_REGION( 0x80000, "maincpu", 0 )     /* 256k for 68000 code */
+	ROM_LOAD16_BYTE( "c69-20-1.10", 0x00000, 0x20000, CRC(b40e4910) SHA1(1436990b8c3c1d0763283133b2ce9d47cd65f825) )
+	ROM_LOAD16_BYTE( "c69-22-1.12", 0x00001, 0x20000, CRC(ecbcf830) SHA1(49f04a198d327866b26b978a302ddc7aea5ac6de) )
+	ROM_LOAD16_BYTE( "c69-19-1.9" , 0x40000, 0x20000, CRC(5719c158) SHA1(e1cdf89695e1dba75f92e449d08fa6df57e9b388) )
+	ROM_LOAD16_BYTE( "c69-21-1.11", 0x40001, 0x20000, CRC(73562394) SHA1(ef9cf4718db05d9b99d6e2630e8f6ad248f30b9a) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )     /* 64k for Z80 code */
+	ROM_LOAD( "c69-23.28",0x00000, 0x10000, CRC(b2fce13e) SHA1(ecdb08482af80fd04cc8b67157e11ca61ce06437) )
+
+	ROM_REGION( 0x400000, "tc0180vcu", 0 )
+	ROM_LOAD       ( "c69-01.ic5", 0x000000, 0x100000, CRC(521fabe3) SHA1(f81303688ac014145a7e9325affc4a0f86755ba9) )
+	ROM_LOAD16_BYTE( "c69-13.ic2", 0x100000, 0x020000, CRC(d1550884) SHA1(f3a65827c45959fe5ac4bfc92831a8bed76bf287) )
+	ROM_LOAD16_BYTE( "c69-12.ic1", 0x100001, 0x020000, CRC(eb56582c) SHA1(41b77704aeaecf3eaa3f87e97c0b59fd00e5349e) )
+	/* 140000-1fffff empty */
+	ROM_LOAD       ( "c69-02.ic6", 0x200000, 0x100000, CRC(f0e20d35) SHA1(af67f39498f68523ece4cd91045456092038e0a4) )
+	ROM_LOAD16_BYTE( "c69-15.ic4", 0x300000, 0x020000, CRC(9761d316) SHA1(f03216bbade96948ff433a925e8bffb8760b4101) )
+	ROM_LOAD16_BYTE( "c69-14.ic3", 0x300001, 0x020000, CRC(0ed0272a) SHA1(03b15654213ff71ffc96d3a87657bdeb724e9269) )
+	/* 340000-3fffff empty */
+
+	ROM_REGION( 0x80000, "ymsnd:adpcma", 0 )   /* ADPCM samples */
+	ROM_LOAD( "c69-03.36", 0x00000, 0x80000, CRC(63e6b6e7) SHA1(72574ca7505eee15fabc4996f253505d9dd65898) )
+ROM_END
+
+ROM_START( realpunc )
+	ROM_REGION( 0x100000, "maincpu", 0 )    /* 1024k for 68000 code */
+	ROM_LOAD16_BYTE( "d76_05.47", 0x00000, 0x80000, CRC(879b7e6a) SHA1(2b06fb4b92d4c23edba97974161da1cb88e0daf5) )
+	ROM_LOAD16_BYTE( "d76_18.48", 0x00001, 0x80000, CRC(46ed7a9f) SHA1(5af7f23e79b9a947f15d36fe54111aa76bc1037b) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )    /* 64k for Z80 code */
+	ROM_LOAD( "d76_06.106",0x00000, 0x10000, CRC(72c799fd) SHA1(ab086be38b890152b33f0c4e33d0f02d0a5321bc) )
+
+	ROM_REGION( 0x400000, "tc0180vcu", 0 )
+	ROM_LOAD( "d76_02.76", 0x000000, 0x100000, CRC(57691b93) SHA1(570dbefda40f8be5f1da58c5433b8a8084f49cac) )
+	ROM_LOAD( "d76_03.45", 0x200000, 0x100000, CRC(9f0aefd8) SHA1(d516c64baabd268f99dc5e67b7adf135b4eb45fd) )
+
+	ROM_REGION( 0x200000, "ymsnd:adpcma", 0 )      /* ADPCM samples */
+	ROM_LOAD( "d76_01.93", 0x000000, 0x200000, CRC(2bc265f2) SHA1(409b822989e2aad50872f80f5160d4909c42206c) )
+ROM_END
+
+ROM_START( realpuncj )
+	ROM_REGION( 0x100000, "maincpu", 0 )    /* 1024k for 68000 code */
+	ROM_LOAD16_BYTE( "d76_05.47", 0x00000, 0x80000, CRC(879b7e6a) SHA1(2b06fb4b92d4c23edba97974161da1cb88e0daf5) )
+	ROM_LOAD16_BYTE( "d76_04.48", 0x00001, 0x80000, CRC(bb8ab32d) SHA1(60e04d406bbd3e1b66edde15c6e8d4df4d32703b) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )    /* 64k for Z80 code */
+	ROM_LOAD( "d76_06.106",0x00000, 0x10000, CRC(72c799fd) SHA1(ab086be38b890152b33f0c4e33d0f02d0a5321bc) )
+
+	ROM_REGION( 0x400000, "tc0180vcu", 0 )
+	ROM_LOAD( "d76_02.76", 0x000000, 0x100000, CRC(57691b93) SHA1(570dbefda40f8be5f1da58c5433b8a8084f49cac) )
+	ROM_LOAD( "d76_03.45", 0x200000, 0x100000, CRC(9f0aefd8) SHA1(d516c64baabd268f99dc5e67b7adf135b4eb45fd) )
+
+	ROM_REGION( 0x200000, "ymsnd:adpcma", 0 )      /* ADPCM samples */
+	ROM_LOAD( "d76_01.93", 0x000000, 0x200000, CRC(2bc265f2) SHA1(409b822989e2aad50872f80f5160d4909c42206c) )
+ROM_END
+
+GAME( 1989, masterw,  0,       masterw,  masterw,   taitob_state, empty_init, ROT270, "Taito Corporation Japan",   "Master of Weapon (World)",  MACHINE_SUPPORTS_SAVE )
+GAME( 1989, masterwu, masterw, masterw,  masterwu,  taitob_state, empty_init, ROT270, "Taito America Corporation", "Master of Weapon (US)",     MACHINE_SUPPORTS_SAVE )
+GAME( 1989, masterwj, masterw, masterw,  masterwj,  taitob_state, empty_init, ROT270, "Taito Corporation",         "Master of Weapon (Japan)",  MACHINE_SUPPORTS_SAVE )
+GAME( 1989, yukiwo,   masterw, masterw,  yukiwo,    taitob_state, empty_init, ROT270, "Taito Corporation Japan",   "Yukiwo (World, prototype)", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1988, nastar,   0,       rastsag2, nastar,    taitob_state, empty_init, ROT0,   "Taito Corporation Japan",   "Nastar (World)",        MACHINE_SUPPORTS_SAVE )
+GAME( 1988, nastarw,  nastar,  rastsag2, nastarw,   taitob_state, empty_init, ROT0,   "Taito America Corporation", "Nastar Warrior (US)",   MACHINE_SUPPORTS_SAVE )
+GAME( 1988, rastsag2, nastar,  rastsag2, rastsag2,  taitob_state, empty_init, ROT0,   "Taito Corporation",         "Rastan Saga 2 (Japan)", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1989, rambo3,   0,       rambo3,   rambo3,    rambo3_state, empty_init, ROT0,   "Taito Europe Corporation",  "Rambo III (Europe)",         MACHINE_SUPPORTS_SAVE )
+GAME( 1989, rambo3u,  rambo3,  rambo3,   rambo3u,   rambo3_state, empty_init, ROT0,   "Taito America Corporation", "Rambo III (US)",             MACHINE_SUPPORTS_SAVE )
+GAME( 1989, rambo3p,  rambo3,  rambo3p,  rambo3p,   rambo3_state, empty_init, ROT0,   "Taito Europe Corporation",  "Rambo III (Europe, Proto?)", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1989, crimec,   0,       crimec,   crimec,    taitob_state, empty_init, ROT0,   "Taito Corporation Japan",   "Crime City (World)", MACHINE_SUPPORTS_SAVE )
+GAME( 1989, crimecu,  crimec,  crimec,   crimecu,   taitob_state, empty_init, ROT0,   "Taito America Corporation", "Crime City (US)",    MACHINE_SUPPORTS_SAVE )
+GAME( 1989, crimecj,  crimec,  crimec,   crimecj,   taitob_state, empty_init, ROT0,   "Taito Corporation",         "Crime City (Japan)", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1988, tetrist,  tetris,  tetrist,  tetrist,   taitob_state, empty_init, ROT0,   "Sega", "Tetris (Japan, Taito B-System, Nastar Conversion Kit)",           MACHINE_SUPPORTS_SAVE )
+GAME( 1988, tetrista, tetris,  tetrista, tetrist,   taitob_state, empty_init, ROT0,   "Sega", "Tetris (Japan, Taito B-System, Master of Weapon Conversion Kit)", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1989, viofight, 0,       viofight, viofight,  taitob_state, empty_init, ROT0,   "Taito Corporation Japan",   "Violence Fight (World)", MACHINE_SUPPORTS_SAVE )
+GAME( 1989, viofightu,viofight,viofight, viofightu, taitob_state, empty_init, ROT0,   "Taito America Corporation", "Violence Fight (US)",    MACHINE_SUPPORTS_SAVE )
+GAME( 1989, viofightj,viofight,viofight, viofightj, taitob_state, empty_init, ROT0,   "Taito Corporation",         "Violence Fight (Japan)", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1990, ashura,   0,       ashura,   ashura,    taitob_state, empty_init, ROT270, "Taito Corporation Japan",   "Ashura Blaster (World)", MACHINE_SUPPORTS_SAVE )
+GAME( 1990, ashuraj,  ashura,  ashura,   ashuraj,   taitob_state, empty_init, ROT270, "Taito Corporation",         "Ashura Blaster (Japan)", MACHINE_SUPPORTS_SAVE )
+GAME( 1990, ashurau,  ashura,  ashura,   ashurau,   taitob_state, empty_init, ROT270, "Taito America Corporation", "Ashura Blaster (US)",    MACHINE_SUPPORTS_SAVE )
+
+GAME( 1990, hitice,   0,       hitice,   hitice,    hitice_state, empty_init, ROT0,   "Taito Corporation (Williams license)",     "Hit the Ice (US)",                   MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
+GAME( 1990, hiticerb, hitice,  hitice,   hitice,    hitice_state, empty_init, ROT0,   "Taito Corporation (Williams license)",     "Hit the Ice (US, with riser board)", MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
+GAME( 1990, hiticej,  hitice,  hitice,   hiticej,   hitice_state, empty_init, ROT0,   "Taito Corporation (licensed from Midway)", "Hit the Ice (Japan)",                MACHINE_IMPERFECT_GRAPHICS | MACHINE_SUPPORTS_SAVE )
+
+GAME( 1991, selfeena, 0,       selfeena, selfeena,  taitob_state, empty_init, ROT0,   "East Technology", "Sel Feena", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1992, silentd,  0,       silentd,  silentd,   taitob_state, empty_init, ROT0,   "Taito Corporation Japan",   "Silent Dragon (World)", MACHINE_SUPPORTS_SAVE )
+GAME( 1992, silentdj, silentd, silentd,  silentdj,  taitob_state, empty_init, ROT0,   "Taito Corporation",         "Silent Dragon (Japan)", MACHINE_SUPPORTS_SAVE )
+GAME( 1992, silentdu, silentd, silentd,  silentdu,  taitob_state, empty_init, ROT0,   "Taito America Corporation", "Silent Dragon (US)",    MACHINE_SUPPORTS_SAVE )
+
+GAME( 1993, ryujin,   0,       silentd,  ryujin,    taitob_state, empty_init, ROT270, "Taito Corporation", "Ryu Jin (Japan, ET910000B PCB)", MACHINE_SUPPORTS_SAVE )
+GAME( 1993, ryujina,  ryujin,  selfeena, ryujin,    taitob_state, empty_init, ROT270, "Taito Corporation", "Ryu Jin (Japan, ET910000A PCB)", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1993, qzshowby, 0,       qzshowby, qzshowby,  taitob_state, empty_init, ROT0,   "Taito Corporation", "Quiz Sekai wa SHOW by shobai (Japan)", MACHINE_SUPPORTS_SAVE )
+
+GAME( 1994, pbobble,  0,       pbobble,  pbobble,   taitob_state, empty_init, ROT0,   "Taito Corporation",         "Puzzle Bobble (Japan, B-System)", MACHINE_SUPPORTS_SAVE ) // PUZZLE  VER 2.0J   1994/06/15  15:28:30
+GAME( 1994, bublbust, pbobble, pbobble,  pbobble,   taitob_state, empty_init, ROT0,   "Taito America Corporation", "Bubble Buster (USA, B-System)",   MACHINE_SUPPORTS_SAVE ) // PUZZLE  VER 2.0A   1994/06/15  15:28:30 - Location test but same build as Japan release?
+
+GAME( 1994, spacedx,  0,       spacedx,  pbobble,   taitob_state, empty_init, ROT0,   "Taito Corporation", "Space Invaders DX (US, v2.1)",    MACHINE_SUPPORTS_SAVE )
+GAME( 1994, spacedxj, spacedx, spacedx,  pbobble,   taitob_state, empty_init, ROT0,   "Taito Corporation", "Space Invaders DX (Japan, v2.1)", MACHINE_SUPPORTS_SAVE )
+GAME( 1994, spacedxo, spacedx, spacedxo, spacedxo,  taitob_state, empty_init, ROT0,   "Taito Corporation", "Space Invaders DX (Japan, v2.0)", MACHINE_SUPPORTS_SAVE )
+
+// Sonic Blast Man is a ticket dispensing game. (Japanese version however does not dispense them, only US does - try the "sbm_patch" in the machine_config).
+// It is a bit different from other games running on this system, in that it has a punching pad that player needs to punch to hit the enemy.
+GAME( 1990, sbm,      0,       sbm,      sbm,       taitob_state,   empty_init, ROT0, "Taito Corporation",       "Sonic Blast Man (US)",    MACHINE_SUPPORTS_SAVE | MACHINE_MECHANICAL )
+GAME( 1990, sbmj,     sbm,     sbm,      sbmj,      taitob_state,   empty_init, ROT0, "Taito Corporation",       "Sonic Blast Man (Japan)", MACHINE_SUPPORTS_SAVE | MACHINE_MECHANICAL )
+GAME( 1994, realpunc, 0,       realpunc, realpunc,  taitob_c_state, empty_init, ROT0, "Taito Corporation Japan", "Real Puncher (World, v2.12O)",   MACHINE_SUPPORTS_SAVE | MACHINE_MECHANICAL )
+GAME( 1994, realpuncj,realpunc,realpunc, realpunc,  taitob_c_state, empty_init, ROT0, "Taito Corporation Japan", "Real Puncher (Japan, v2.12J)",   MACHINE_SUPPORTS_SAVE | MACHINE_MECHANICAL )
diff --git a/cores/taitob/doc/taitoio.cpp b/cores/taitob/doc/taitoio.cpp
new file mode 100644
index 000000000..dc59d63d2
--- /dev/null
+++ b/cores/taitob/doc/taitoio.cpp
@@ -0,0 +1,574 @@
+// license:BSD-3-Clause
+// copyright-holders:Nicola Salmoria
+/***************************************************************************
+
+TC0040IOC
+---------
+Taito's first custom I/O interface differs a bit from its successors,
+being a 64-pin DIP with an address port and a data port. Besides digital
+inputs, coin-related outputs and an integrated watchdog, this chip also
+handles steering wheel and trackball input conversion in various games (not
+emulated here yet).
+
+
+TC0220IOC
+---------
+A simple I/O interface with integrated watchdog in a 80-pin flat package.
+It has four address inputs, which would suggest 16 bytes of addressing space,
+but only the first 8 seem to be used.
+
+000 R  IN00-07 (DSA)
+000  W watchdog reset
+001 R  IN08-15 (DSB)
+002 R  IN16-23 (1P)
+002  W unknown. Usually written on startup: initialize?
+003 R  IN24-31 (2P)
+004 RW coin counters and lockout
+005  W unknown
+006  W unknown
+007 R  INB0-7 (coin)
+
+
+TC0510NIO
+---------
+Newer QFP100 version of the I/O chip
+
+000 R  DSWA
+000  W watchdog reset
+001 R  DSWB
+001  W unknown (ssi)
+002 R  1P
+003 R  2P
+003  W unknown (yuyugogo, qzquest and qzchikyu use it a lot)
+004 RW coin counters and lockout
+005  W unknown
+006  W unknown (koshien and pulirula use it a lot)
+007 R  coin
+
+
+TC0640FIO
+---------
+Newer version of the I/O chip ?
+
+
+***************************************************************************/
+
+#include "emu.h"
+#include "taitoio.h"
+
+#include <algorithm>
+
+/***************************************************************************/
+/*                                                                         */
+/*                              TC0040IOC                                  */
+/*                                                                         */
+/***************************************************************************/
+
+DEFINE_DEVICE_TYPE(TC0040IOC, tc0040ioc_device, "tc0040ioc", "Taito TC0040IOC")
+
+tc0040ioc_device::tc0040ioc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, TC0040IOC, tag, owner, clock),
+	m_port(0),
+	m_watchdog(*this, "watchdog"),
+	m_read_0_cb(*this, 0),
+	m_read_1_cb(*this, 0),
+	m_read_2_cb(*this, 0),
+	m_read_3_cb(*this, 0),
+	m_write_4_cb(*this),
+	m_read_7_cb(*this, 0)
+{
+	std::fill(std::begin(m_regs), std::end(m_regs), 0);
+}
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void tc0040ioc_device::device_start()
+{
+	save_item(NAME(m_regs));
+	save_item(NAME(m_port));
+}
+
+//-------------------------------------------------
+//  device_reset - device-specific reset
+//-------------------------------------------------
+
+void tc0040ioc_device::device_reset()
+{
+	m_port = 0;
+
+	std::fill(std::begin(m_regs), std::end(m_regs), 0);
+}
+
+//-------------------------------------------------
+//  device_add_mconfig - add device configuration
+//-------------------------------------------------
+
+void tc0040ioc_device::device_add_mconfig(machine_config &config)
+{
+	WATCHDOG_TIMER(config, m_watchdog);
+}
+
+/*****************************************************************************
+    DEVICE HANDLERS
+*****************************************************************************/
+
+u8 tc0040ioc_device::read(offs_t offset)
+{
+	if (offset & 1)
+		return watchdog_r();
+	else
+		return portreg_r();
+}
+
+void tc0040ioc_device::write(offs_t offset, u8 data)
+{
+	if (offset & 1)
+		port_w(data);
+	else
+		portreg_w(data);
+}
+
+u8 tc0040ioc_device::watchdog_r()
+{
+	if (!machine().side_effects_disabled())
+		m_watchdog->watchdog_reset();
+	return 0;
+}
+
+// only used now for "input bypass" hacks
+u8 tc0040ioc_device::port_r()
+{
+	return m_port;
+}
+
+void tc0040ioc_device::port_w(u8 data)
+{
+	m_port = data;
+}
+
+u8 tc0040ioc_device::portreg_r()
+{
+	switch (m_port)
+	{
+		case 0x00:
+			return m_read_0_cb(0);
+
+		case 0x01:
+			return m_read_1_cb(0);
+
+		case 0x02:
+			return m_read_2_cb(0);
+
+		case 0x03:
+			return m_read_3_cb(0);
+
+		case 0x04:  /* coin counters and lockout */
+			return m_regs[4];
+
+		case 0x07:
+			return m_read_7_cb(0);
+
+		default:
+//logerror("%s: warning - read TC0040IOC address %02x\n",m_maincpu->pc(),m_port);
+			return 0xff;
+	}
+}
+
+void tc0040ioc_device::portreg_w(u8 data)
+{
+	if (m_port < std::size(m_regs))
+		m_regs[m_port] = data;
+	switch (m_port)
+	{
+		case 0x04:  /* coin counters and lockout, hi nibble irrelevant */
+			m_write_4_cb(data & 0x0f);
+
+//if (data & 0xf0)
+//logerror("%s: warning - write %02x to TC0040IOC address %02x\n",m_maincpu->pc(),data,m_port);
+
+			break;
+
+		default:
+//logerror("%s: warning - write %02x to TC0040IOC address %02x\n",m_maincpu->pc(),data,m_port);
+			break;
+	}
+}
+
+
+/***************************************************************************/
+/*                                                                         */
+/*                              TC0220IOC                                  */
+/*                                                                         */
+/***************************************************************************/
+
+DEFINE_DEVICE_TYPE(TC0220IOC, tc0220ioc_device, "tc0220ioc", "Taito TC0220IOC")
+
+tc0220ioc_device::tc0220ioc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, TC0220IOC, tag, owner, clock),
+	m_watchdog(*this, "watchdog"),
+	m_read_0_cb(*this, 0),
+	m_read_1_cb(*this, 0),
+	m_read_2_cb(*this, 0),
+	m_read_3_cb(*this, 0),
+	m_write_3_cb(*this),
+	m_write_4_cb(*this),
+	m_read_7_cb(*this, 0)
+{
+	std::fill(std::begin(m_regs), std::end(m_regs), 0);
+}
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void tc0220ioc_device::device_start()
+{
+	save_item(NAME(m_regs));
+}
+
+//-------------------------------------------------
+//  device_reset - device-specific reset
+//-------------------------------------------------
+
+void tc0220ioc_device::device_reset()
+{
+	std::fill(std::begin(m_regs), std::end(m_regs), 0);
+}
+
+//-------------------------------------------------
+//  device_add_mconfig - add device configuration
+//-------------------------------------------------
+
+void tc0220ioc_device::device_add_mconfig(machine_config &config)
+{
+	WATCHDOG_TIMER(config, m_watchdog);
+//  m_watchdog->set_time(attotime::from_msec(3200));
+}
+
+/*****************************************************************************
+    DEVICE HANDLERS
+*****************************************************************************/
+
+u8 tc0220ioc_device::read(offs_t offset)
+{
+	switch (offset)
+	{
+		case 0x00:
+			return m_read_0_cb(0);
+
+		case 0x01:
+			return m_read_1_cb(0);
+
+		case 0x02:
+			return m_read_2_cb(0);
+
+		case 0x03:
+			return m_read_3_cb(0);
+
+		case 0x04:  /* coin counters and lockout */
+			return m_regs[4];
+
+		case 0x07:
+			return m_read_7_cb(0);
+
+		default:
+//logerror("%s: warning - read TC0220IOC address %02x\n",m_maincpu->pc(),offset);
+			return 0xff;
+	}
+}
+
+void tc0220ioc_device::write(offs_t offset, u8 data)
+{
+	m_regs[offset] = data;
+	switch (offset)
+	{
+		case 0x00:
+			m_watchdog->watchdog_reset();
+			break;
+
+		case 0x03:
+			m_write_3_cb(data);
+			break;
+
+		case 0x04:  /* coin counters and lockout, hi nibble irrelevant */
+			m_write_4_cb(data & 0x0f);
+
+//if (data & 0xf0)
+//logerror("%s: warning - write %02x to TC0220IOC address %02x\n",m_maincpu->pc(),data,offset);
+
+			break;
+
+		default:
+//logerror("%s: warning - write %02x to TC0220IOC address %02x\n",m_maincpu->pc(),data,offset);
+			break;
+	}
+}
+
+/***************************************************************************/
+/*                                                                         */
+/*                              TC0510NIO                                  */
+/*                                                                         */
+/***************************************************************************/
+
+
+DEFINE_DEVICE_TYPE(TC0510NIO, tc0510nio_device, "tc0510nio", "Taito TC0510NIO")
+
+tc0510nio_device::tc0510nio_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: device_t(mconfig, TC0510NIO, tag, owner, clock),
+	m_watchdog(*this, "watchdog"),
+	m_read_0_cb(*this, 0),
+	m_read_1_cb(*this, 0),
+	m_read_2_cb(*this, 0),
+	m_read_3_cb(*this, 0),
+	m_write_3_cb(*this),
+	m_write_4_cb(*this),
+	m_read_7_cb(*this, 0)
+{
+	std::fill(std::begin(m_regs), std::end(m_regs), 0);
+}
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void tc0510nio_device::device_start()
+{
+	save_item(NAME(m_regs));
+}
+
+//-------------------------------------------------
+//  device_reset - device-specific reset
+//-------------------------------------------------
+
+void tc0510nio_device::device_reset()
+{
+	std::fill(std::begin(m_regs), std::end(m_regs), 0);
+}
+
+//-------------------------------------------------
+//  device_add_mconfig - add device configuration
+//-------------------------------------------------
+
+void tc0510nio_device::device_add_mconfig(machine_config &config)
+{
+	WATCHDOG_TIMER(config, m_watchdog);
+}
+
+/*****************************************************************************
+    DEVICE HANDLERS
+*****************************************************************************/
+
+u8 tc0510nio_device::read(offs_t offset)
+{
+	switch (offset)
+	{
+		case 0x00:
+			return m_read_0_cb(0);
+
+		case 0x01:
+			return m_read_1_cb(0);
+
+		case 0x02:
+			return m_read_2_cb(0);
+
+		case 0x03:
+			return m_read_3_cb(0);
+
+		case 0x04:  /* coin counters and lockout */
+			return m_regs[4];
+
+		case 0x07:
+			return m_read_7_cb(0);
+
+		default:
+//logerror("%s: warning - read TC0510NIO address %02x\n",m_maincpu->pc(),offset);
+			return 0xff;
+	}
+}
+
+void tc0510nio_device::write(offs_t offset, u8 data)
+{
+	m_regs[offset] = data;
+
+	switch (offset)
+	{
+		case 0x00:
+			m_watchdog->watchdog_reset();
+			break;
+
+		case 0x03:
+			m_write_3_cb(data);
+			break;
+
+		case 0x04:  /* coin counters and lockout */
+			m_write_4_cb(data & 0x0f);
+			break;
+
+		default:
+//logerror("%s: warning - write %02x to TC0510NIO address %02x\n",m_maincpu->pc(),data,offset);
+			break;
+	}
+}
+
+u16 tc0510nio_device::halfword_r(offs_t offset)
+{
+	return read(offset);
+}
+
+void tc0510nio_device::halfword_w(offs_t offset, u16 data, u16 mem_mask)
+{
+	if (ACCESSING_BITS_0_7)
+		write(offset, data & 0xff);
+	else
+	{
+		/* driftout writes the coin counters here - bug? */
+//logerror("CPU #0 %s: warning - write to MSB of TC0510NIO address %02x\n",m_maincpu->pc(),offset);
+		write(offset, (data >> 8) & 0xff);
+	}
+}
+
+u16 tc0510nio_device::halfword_wordswap_r(offs_t offset)
+{
+	return halfword_r(offset ^ 1);
+}
+
+void tc0510nio_device::halfword_wordswap_w(offs_t offset, u16 data, u16 mem_mask)
+{
+	halfword_w(offset ^ 1,data, mem_mask);
+}
+
+
+/***************************************************************************/
+/*                                                                         */
+/*                              TC0640FIO                                  */
+/*                                                                         */
+/***************************************************************************/
+
+
+DEFINE_DEVICE_TYPE(TC0640FIO, tc0640fio_device, "tc0640fio", "Taito TC0640FIO")
+
+tc0640fio_device::tc0640fio_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
+	: device_t(mconfig, TC0640FIO, tag, owner, clock),
+	m_watchdog(*this, "watchdog"),
+	m_read_0_cb(*this, 0),
+	m_read_1_cb(*this, 0),
+	m_read_2_cb(*this, 0),
+	m_read_3_cb(*this, 0),
+	m_write_4_cb(*this),
+	m_read_7_cb(*this, 0)
+{
+	std::fill(std::begin(m_regs), std::end(m_regs), 0);
+}
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void tc0640fio_device::device_start()
+{
+	save_item(NAME(m_regs));
+}
+
+//-------------------------------------------------
+//  device_reset - device-specific reset
+//-------------------------------------------------
+
+void tc0640fio_device::device_reset()
+{
+	std::fill(std::begin(m_regs), std::end(m_regs), 0);
+}
+
+//-------------------------------------------------
+//  device_add_mconfig - add device configuration
+//-------------------------------------------------
+
+void tc0640fio_device::device_add_mconfig(machine_config &config)
+{
+	WATCHDOG_TIMER(config, m_watchdog);
+}
+
+
+/*****************************************************************************
+    DEVICE HANDLERS
+*****************************************************************************/
+
+u8 tc0640fio_device::read(offs_t offset)
+{
+	switch (offset)
+	{
+		case 0x00:
+			return m_read_0_cb(0);
+
+		case 0x01:
+			return m_read_1_cb(0);
+
+		case 0x02:
+			return m_read_2_cb(0);
+
+		case 0x03:
+			return m_read_3_cb(0);
+
+		case 0x04:  /* coin counters and lockout */
+			return m_regs[4];
+
+		case 0x07:
+			return m_read_7_cb(0);
+
+		default:
+//logerror("%s: warning - read TC0640FIO address %02x\n",m_maincpu->pc(),offset);
+			return 0xff;
+	}
+}
+
+void tc0640fio_device::write(offs_t offset, u8 data)
+{
+	m_regs[offset] = data;
+	switch (offset)
+	{
+		case 0x00:
+			m_watchdog->watchdog_reset();
+			break;
+
+		case 0x04:  /* coin counters and lockout */
+			m_write_4_cb(data & 0x0f);
+			break;
+
+		default:
+//logerror("%s: warning - write %02x to TC0640FIO address %02x\n",m_maincpu->pc(),data,offset);
+			break;
+	}
+}
+
+u16 tc0640fio_device::halfword_r(offs_t offset)
+{
+	return read(offset);
+}
+
+void tc0640fio_device::halfword_w(offs_t offset, u16 data, u16 mem_mask)
+{
+	if (ACCESSING_BITS_0_7)
+		write(offset, data & 0xff);
+	else
+	{
+		write(offset, (data >> 8) & 0xff);
+//logerror("CPU #0 %s: warning - write to MSB of TC0640FIO address %02x\n",m_maincpu->pc(),offset);
+	}
+}
+
+u16 tc0640fio_device::halfword_byteswap_r(offs_t offset)
+{
+	return halfword_r(offset) << 8;
+}
+
+void tc0640fio_device::halfword_byteswap_w(offs_t offset, u16 data, u16 mem_mask)
+{
+	if (ACCESSING_BITS_8_15)
+		write(offset, (data >> 8) & 0xff);
+	else
+	{
+		write(offset, data & 0xff);
+//logerror("CPU #0 %s: warning - write to LSB of TC0640FIO address %02x\n",m_maincpu->pc(),offset);
+	}
+}
diff --git a/cores/taitob/doc/taitoio.h b/cores/taitob/doc/taitoio.h
new file mode 100644
index 000000000..610b4c453
--- /dev/null
+++ b/cores/taitob/doc/taitoio.h
@@ -0,0 +1,185 @@
+// license:BSD-3-Clause
+// copyright-holders:Nicola Salmoria
+/*************************************************************************
+
+    taitoio.h
+
+    Implementation of various Taito custom I/O ICs
+
+**************************************************************************/
+
+#ifndef MAME_TAITO_TAITOIO_H
+#define MAME_TAITO_TAITOIO_H
+
+#pragma once
+
+#include "machine/watchdog.h"
+
+
+class tc0040ioc_device : public device_t
+{
+public:
+	tc0040ioc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	auto read_0_callback() { return m_read_0_cb.bind(); }
+	auto read_1_callback() { return m_read_1_cb.bind(); }
+	auto read_2_callback() { return m_read_2_cb.bind(); }
+	auto read_3_callback() { return m_read_3_cb.bind(); }
+	auto write_4_callback() { return m_write_4_cb.bind(); }
+	auto read_7_callback() { return m_read_7_cb.bind(); }
+
+	u8 read(offs_t offset);
+	void write(offs_t offset, u8 data);
+	u8 watchdog_r();
+	u8 port_r();
+	void port_w(u8 data);
+	u8 portreg_r();
+	void portreg_w(u8 data);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+private:
+	// internal state
+	u8      m_regs[8];
+	u8      m_port;
+
+	required_device<watchdog_timer_device> m_watchdog;
+
+	devcb_read8 m_read_0_cb;
+	devcb_read8 m_read_1_cb;
+	devcb_read8 m_read_2_cb;
+	devcb_read8 m_read_3_cb;
+	devcb_write8 m_write_4_cb;
+	devcb_read8 m_read_7_cb;
+};
+
+DECLARE_DEVICE_TYPE(TC0040IOC, tc0040ioc_device)
+
+class tc0220ioc_device : public device_t
+{
+public:
+	tc0220ioc_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	auto read_0_callback() { return m_read_0_cb.bind(); }
+	auto read_1_callback() { return m_read_1_cb.bind(); }
+	auto read_2_callback() { return m_read_2_cb.bind(); }
+	auto read_3_callback() { return m_read_3_cb.bind(); }
+	auto write_3_callback() { return m_write_3_cb.bind(); }
+	auto write_4_callback() { return m_write_4_cb.bind(); }
+	auto read_7_callback() { return m_read_7_cb.bind(); }
+
+	u8 read(offs_t offset);
+	void write(offs_t offset, u8 data);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+private:
+	// internal state
+	u8      m_regs[8];
+
+	required_device<watchdog_timer_device> m_watchdog;
+
+	devcb_read8 m_read_0_cb;
+	devcb_read8 m_read_1_cb;
+	devcb_read8 m_read_2_cb;
+	devcb_read8 m_read_3_cb;
+	devcb_write8 m_write_3_cb;
+	devcb_write8 m_write_4_cb;
+	devcb_read8 m_read_7_cb;
+};
+
+DECLARE_DEVICE_TYPE(TC0220IOC, tc0220ioc_device)
+
+class tc0510nio_device : public device_t
+{
+public:
+	tc0510nio_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	auto read_0_callback() { return m_read_0_cb.bind(); }
+	auto read_1_callback() { return m_read_1_cb.bind(); }
+	auto read_2_callback() { return m_read_2_cb.bind(); }
+	auto read_3_callback() { return m_read_3_cb.bind(); }
+	auto write_3_callback() { return m_write_3_cb.bind(); }
+	auto write_4_callback() { return m_write_4_cb.bind(); }
+	auto read_7_callback() { return m_read_7_cb.bind(); }
+
+	u8 read(offs_t offset);
+	void write(offs_t offset, u8 data);
+	u16 halfword_r(offs_t offset);
+	void halfword_w(offs_t offset, u16 data, u16 mem_mask = ~0);
+	u16 halfword_wordswap_r(offs_t offset);
+	void halfword_wordswap_w(offs_t offset, u16 data, u16 mem_mask = ~0);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+private:
+	// internal state
+	u8   m_regs[8];
+
+	required_device<watchdog_timer_device> m_watchdog;
+
+	devcb_read8 m_read_0_cb;
+	devcb_read8 m_read_1_cb;
+	devcb_read8 m_read_2_cb;
+	devcb_read8 m_read_3_cb;
+	devcb_write8 m_write_3_cb;
+	devcb_write8 m_write_4_cb;
+	devcb_read8 m_read_7_cb;
+};
+
+DECLARE_DEVICE_TYPE(TC0510NIO, tc0510nio_device)
+
+class tc0640fio_device : public device_t
+{
+public:
+	tc0640fio_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	auto read_0_callback() { return m_read_0_cb.bind(); }
+	auto read_1_callback() { return m_read_1_cb.bind(); }
+	auto read_2_callback() { return m_read_2_cb.bind(); }
+	auto read_3_callback() { return m_read_3_cb.bind(); }
+	auto write_4_callback() { return m_write_4_cb.bind(); }
+	auto read_7_callback() { return m_read_7_cb.bind(); }
+
+	u8 read(offs_t offset);
+	void write(offs_t offset, u8 data);
+	u16 halfword_r(offs_t offset);
+	void halfword_w(offs_t offset, u16 data, u16 mem_mask = ~0);
+	u16 halfword_byteswap_r(offs_t offset);
+	void halfword_byteswap_w(offs_t offset, u16 data, u16 mem_mask = ~0);
+
+protected:
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+	virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
+
+	private:
+	// internal state
+	u8   m_regs[8];
+
+	required_device<watchdog_timer_device> m_watchdog;
+
+	devcb_read8 m_read_0_cb;
+	devcb_read8 m_read_1_cb;
+	devcb_read8 m_read_2_cb;
+	devcb_read8 m_read_3_cb;
+	devcb_write8 m_write_4_cb;
+	devcb_read8 m_read_7_cb;
+};
+
+DECLARE_DEVICE_TYPE(TC0640FIO, tc0640fio_device)
+
+#endif // MAME_TAITO_TAITOIO_H
diff --git a/cores/taitob/doc/taitosnd.cpp b/cores/taitob/doc/taitosnd.cpp
new file mode 100644
index 000000000..03d6911ed
--- /dev/null
+++ b/cores/taitob/doc/taitosnd.cpp
@@ -0,0 +1,335 @@
+// license:BSD-3-Clause
+// copyright-holders:Philip Bennett
+/**********************************************************************************************
+
+    Taito TC0140SYT
+
+    TODO:
+     - Add pinout and description
+     - Create a separate implementation for the PC060HA
+
+    General rule seems to be that TC0140SYT supports a YM2610,
+    whereas PC060HA goes with a YM2203 or YM2151.
+
+    The PC060HA has been decapped and verified to be a ULA.
+
+**********************************************************************************************/
+
+#include "emu.h"
+#include "taitosnd.h"
+
+#include "cpu/z80/z80.h"
+
+
+/**********************************************************************************************
+
+    It seems like 1 nibble commands are only for control purposes.
+    2 nibble commands are the real messages passed from one board to the other.
+
+**********************************************************************************************/
+
+static constexpr u8 TC0140SYT_PORT01_FULL =        0x01;
+static constexpr u8 TC0140SYT_PORT23_FULL =        0x02;
+static constexpr u8 TC0140SYT_PORT01_FULL_MASTER = 0x04;
+static constexpr u8 TC0140SYT_PORT23_FULL_MASTER = 0x08;
+
+
+// device type definition
+DEFINE_DEVICE_TYPE(TC0140SYT, tc0140syt_device, "tc0140syt", "Taito TC0140SYT")
+DEFINE_DEVICE_TYPE(PC060HA, pc060ha_device, "pc060ha", "Taito PC060HA CIU")
+
+
+//**************************************************************************
+//  LIVE DEVICE
+//**************************************************************************
+
+//-------------------------------------------------
+//  tc0140syt_device - constructor
+//-------------------------------------------------
+
+tc0140syt_device::tc0140syt_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock)
+	: device_t(mconfig, type, tag, owner, clock)
+	, m_mainmode(0)
+	, m_submode(0)
+	, m_status(0)
+	, m_nmi_enabled(0)
+	, m_nmi_cb(*this)
+	, m_reset_cb(*this)
+{
+	std::fill(std::begin(m_slavedata), std::end(m_slavedata), 0);
+	std::fill(std::begin(m_masterdata), std::end(m_masterdata), 0);
+}
+
+tc0140syt_device::tc0140syt_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+	: tc0140syt_device(mconfig, TC0140SYT, tag, owner, clock)
+{
+}
+
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void tc0140syt_device::device_start()
+{
+	save_item(NAME(m_mainmode));
+	save_item(NAME(m_submode));
+	save_item(NAME(m_status));
+	save_item(NAME(m_nmi_enabled));
+	save_item(NAME(m_slavedata));
+	save_item(NAME(m_masterdata));
+}
+
+
+//-------------------------------------------------
+//  device_reset - device-specific reset
+//-------------------------------------------------
+
+void tc0140syt_device::device_reset()
+{
+	m_mainmode = 0;
+	m_submode = 0;
+	m_status = 0;
+	m_nmi_enabled = 0;
+
+	for (u8 i = 0; i < 4; i++)
+	{
+		m_slavedata[i] = 0;
+		m_masterdata[i] = 0;
+	}
+}
+
+
+//-------------------------------------------------
+//  DEVICE HANDLERS
+//-------------------------------------------------
+
+void tc0140syt_device::update_nmi()
+{
+	u32 const nmi_pending = m_status & (TC0140SYT_PORT23_FULL | TC0140SYT_PORT01_FULL);
+	m_nmi_cb((nmi_pending && m_nmi_enabled) ? ASSERT_LINE : CLEAR_LINE);
+}
+
+
+//-------------------------------------------------
+//  MASTER SIDE
+//-------------------------------------------------
+
+void tc0140syt_device::master_port_w(u8 data)
+{
+	data &= 0x0f;
+	m_mainmode = data;
+
+	if (data > 4)
+	{
+		logerror("tc0140syt : error Master entering unknown mode[%02x]\n", data);
+	}
+}
+
+void tc0140syt_device::master_comm_w(u8 data)
+{
+	// let slavecpu catch up (after we return and the main cpu finishes what it's doing)
+	machine().scheduler().synchronize();
+
+	data &= 0x0f; // this is important, otherwise ballbros won't work
+
+	switch (m_mainmode)
+	{
+		case 0x00: // mode #0
+			m_slavedata[m_mainmode++] = data;
+			break;
+
+		case 0x01: // mode #1
+			m_slavedata[m_mainmode++] = data;
+			m_status |= TC0140SYT_PORT01_FULL;
+			update_nmi();
+			break;
+
+		case 0x02: // mode #2
+			m_slavedata[m_mainmode++] = data;
+			break;
+
+		case 0x03: // mode #3
+			m_slavedata[m_mainmode++] = data;
+			m_status |= TC0140SYT_PORT23_FULL;
+			update_nmi();
+			break;
+
+		case 0x04: // port status
+			/* this does a hi-lo transition to reset the sound cpu */
+			m_reset_cb(data ? ASSERT_LINE : CLEAR_LINE);
+			break;
+
+		default:
+			break;
+	}
+}
+
+u8 tc0140syt_device::master_comm_r()
+{
+	// let slavecpu catch up (after we return and the main cpu finishes what it's doing)
+	if (!machine().side_effects_disabled())
+		machine().scheduler().synchronize();
+
+	u8 res = 0;
+
+	switch (m_mainmode)
+	{
+		case 0x00: // mode #0
+			res = m_masterdata[m_mainmode];
+			if (!machine().side_effects_disabled())
+				m_mainmode++;
+			break;
+
+		case 0x01: // mode #1
+			res = m_masterdata[m_mainmode];
+			if (!machine().side_effects_disabled())
+			{
+				m_status &= ~TC0140SYT_PORT01_FULL_MASTER;
+				m_mainmode++;
+			}
+			break;
+
+		case 0x02: // mode #2
+			res = m_masterdata[m_mainmode];
+			if (!machine().side_effects_disabled())
+				m_mainmode++;
+			break;
+
+		case 0x03: // mode #3
+			res = m_masterdata[m_mainmode];
+			if (!machine().side_effects_disabled())
+			{
+				m_status &= ~TC0140SYT_PORT23_FULL_MASTER;
+				m_mainmode++;
+			}
+			break;
+
+		case 0x04: // port status
+			res = m_status;
+			break;
+
+		default:
+			break;
+	}
+
+	return res;
+}
+
+
+//-------------------------------------------------
+//  SLAVE SIDE
+//-------------------------------------------------
+
+void tc0140syt_device::slave_port_w(u8 data)
+{
+	data &= 0x0f;
+	m_submode = data;
+
+	if (data > 6)
+	{
+		logerror("tc0140syt error : Slave cpu unknown mode[%02x]\n", data);
+	}
+}
+
+void tc0140syt_device::slave_comm_w(u8 data)
+{
+	data &= 0x0f;
+
+	switch (m_submode)
+	{
+		case 0x00: // mode #0
+			m_masterdata[m_submode++] = data;
+			break;
+
+		case 0x01: // mode #1
+			m_masterdata[m_submode++] = data;
+			m_status |= TC0140SYT_PORT01_FULL_MASTER;
+			break;
+
+		case 0x02: // mode #2
+			m_masterdata[m_submode++] = data;
+			break;
+
+		case 0x03: // mode #3
+			m_masterdata[m_submode++] = data;
+			m_status |= TC0140SYT_PORT23_FULL_MASTER;
+			break;
+
+		case 0x04: // port status
+			//m_status = TC0140SYT_SET_OK;
+			break;
+
+		case 0x05: // NMI disable
+			m_nmi_enabled = 0;
+			update_nmi();
+			break;
+
+		case 0x06: // NMI enable
+			m_nmi_enabled = 1;
+			update_nmi();
+			break;
+
+		default:
+			break;
+	}
+}
+
+u8 tc0140syt_device::slave_comm_r()
+{
+	u8 res = 0;
+
+	switch (m_submode)
+	{
+		case 0x00: // mode #0
+			res = m_slavedata[m_submode];
+			if (!machine().side_effects_disabled())
+				m_submode++;
+			break;
+
+		case 0x01: // mode #1
+			res = m_slavedata[m_submode];
+			if (!machine().side_effects_disabled())
+			{
+				m_status &= ~TC0140SYT_PORT01_FULL;
+				m_submode++;
+				update_nmi();
+			}
+			break;
+
+		case 0x02: // mode #2
+			res = m_slavedata[m_submode];
+			if (!machine().side_effects_disabled())
+				m_submode++;
+			break;
+
+		case 0x03: // mode #3
+			res = m_slavedata[m_submode];
+			if (!machine().side_effects_disabled())
+			{
+				m_status &= ~TC0140SYT_PORT23_FULL;
+				m_submode++;
+				update_nmi();
+			}
+			break;
+
+		case 0x04: // port status
+			res = m_status;
+			break;
+
+		default:
+			break;
+	}
+
+	return res;
+}
+
+
+//-------------------------------------------------
+//  pc060ha_device - constructor
+//-------------------------------------------------
+
+pc060ha_device::pc060ha_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
+	: tc0140syt_device(mconfig, PC060HA, tag, owner, clock)
+{
+}
diff --git a/cores/taitob/doc/taitosnd.h b/cores/taitob/doc/taitosnd.h
new file mode 100644
index 000000000..97829e17f
--- /dev/null
+++ b/cores/taitob/doc/taitosnd.h
@@ -0,0 +1,64 @@
+// license:BSD-3-Clause
+// copyright-holders:Philip Bennett
+#ifndef MAME_SHARED_TAITOSND_H
+#define MAME_SHARED_TAITOSND_H
+
+
+//**************************************************************************
+//  TYPE DEFINITIONS
+//**************************************************************************
+
+// ======================> tc0140syt_device
+
+class tc0140syt_device : public device_t
+{
+public:
+	tc0140syt_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+
+	auto nmi_callback() { return m_nmi_cb.bind(); }
+	auto reset_callback() { return m_reset_cb.bind(); }
+
+	// MASTER (4-bit bus) control functions
+	void master_port_w(u8 data);
+	void master_comm_w(u8 data);
+	u8 master_comm_r();
+
+	// SLAVE (4-bit bus) control functions ONLY
+	void slave_port_w(u8 data);
+	u8 slave_comm_r();
+	void slave_comm_w(u8 data);
+
+protected:
+	tc0140syt_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, u32 clock);
+
+	// device-level overrides
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+private:
+	void update_nmi();
+
+	u8     m_slavedata[4];  /* Data on master->slave port (4 nibbles) */
+	u8     m_masterdata[4]; /* Data on slave->master port (4 nibbles) */
+	u8     m_mainmode;      /* Access mode on master cpu side */
+	u8     m_submode;       /* Access mode on slave cpu side */
+	u8     m_status;        /* Status data */
+	u8     m_nmi_enabled;   /* 1 if slave cpu has nmi's enabled */
+
+	devcb_write_line m_nmi_cb;
+	devcb_write_line m_reset_cb;
+};
+
+// ======================> pc060ha_device
+
+class pc060ha_device : public tc0140syt_device
+{
+public:
+	pc060ha_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
+};
+
+DECLARE_DEVICE_TYPE(TC0140SYT, tc0140syt_device)
+DECLARE_DEVICE_TYPE(PC060HA, pc060ha_device)
+
+
+#endif // MAME_SHARED_TAITOSND_H
diff --git a/cores/taitob/doc/tc0180vcu.cpp b/cores/taitob/doc/tc0180vcu.cpp
new file mode 100644
index 000000000..72826b000
--- /dev/null
+++ b/cores/taitob/doc/tc0180vcu.cpp
@@ -0,0 +1,599 @@
+// license:BSD-3-Clause
+// copyright-holders:Nicola Salmoria
+/* Taito TC0180VCU */
+// Sprite/Framebuffer emulation by Jarek Burczynski (from taito_b.cpp)
+
+#include "emu.h"
+#include "tc0180vcu.h"
+#include "screen.h"
+
+//#define TC0180VCU_RAM_SIZE          0x10000
+//#define TC0180VCU_SCROLLRAM_SIZE    0x0800
+
+const gfx_layout tc0180vcu_device::charlayout =
+{
+	8,8,
+	RGN_FRAC(1,2),
+	4,
+	{ 0, 8, RGN_FRAC(1,2), RGN_FRAC(1,2)+8 },
+	{ STEP8(0,1) },
+	{ STEP8(0,8*2) },
+	16*8
+};
+
+const gfx_layout tc0180vcu_device::tilelayout =
+{
+	16,16,
+	RGN_FRAC(1,2),
+	4,
+	{ 0, 8, RGN_FRAC(1,2), RGN_FRAC(1,2)+8 },
+	{ STEP8(0,1), STEP8(8*8*2,1) },
+	{ STEP8(0,8*2), STEP8(8*8*2*2,8*2) },
+	64*8
+};
+
+GFXDECODE_MEMBER( tc0180vcu_device::gfxinfo )
+	GFXDECODE_DEVICE( DEVICE_SELF, 0, charlayout,  0, 256 )
+	GFXDECODE_DEVICE( DEVICE_SELF, 0, tilelayout,  0, 256 )
+GFXDECODE_END
+
+void tc0180vcu_device::tc0180vcu_memrw(address_map &map)
+{
+	map(0x00000, 0x0ffff).ram().w(FUNC(tc0180vcu_device::word_w)).share(m_vram);
+	map(0x10000, 0x1197f).ram().share(m_spriteram);
+	map(0x11980, 0x137ff).ram();
+	map(0x13800, 0x13fff).ram().share(m_scrollram);
+	map(0x18000, 0x1801f).ram().w(FUNC(tc0180vcu_device::ctrl_w)).share(m_ctrl);
+	map(0x40000, 0x7ffff).rw(FUNC(tc0180vcu_device::framebuffer_word_r), FUNC(tc0180vcu_device::framebuffer_word_w));
+}
+
+DEFINE_DEVICE_TYPE(TC0180VCU, tc0180vcu_device, "tc0180vcu", "Taito TC0180VCU")
+
+tc0180vcu_device::tc0180vcu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
+	device_t(mconfig, TC0180VCU, tag, owner, clock),
+	device_gfx_interface(mconfig, *this, gfxinfo),
+	device_video_interface(mconfig, *this),
+	m_spriteram(*this, "spriteram"),
+	m_vram(*this, "vram"),
+	m_scrollram(*this, "scrollram"),
+	m_ctrl(*this, "ctrl"),
+	//m_bg_rambank(0),
+	//m_fg_rambank(0),
+	//m_tx_rambank(0),
+	m_framebuffer_page(0),
+	m_video_control(0),
+	m_fb_color_base(0),
+	m_bg_color_base(0),
+	m_fg_color_base(0),
+	m_tx_color_base(0),
+	m_inth_callback(*this),
+	m_intl_callback(*this),
+	m_intl_timer(nullptr)
+{
+}
+
+//-------------------------------------------------
+//  device_start - device-specific startup
+//-------------------------------------------------
+
+void tc0180vcu_device::device_start()
+{
+	m_tilemap[0] = &machine().tilemap().create(*this, tilemap_get_info_delegate(*this, FUNC(tc0180vcu_device::get_bg_tile_info)), TILEMAP_SCAN_ROWS, 16, 16, 64, 64);
+	m_tilemap[1] = &machine().tilemap().create(*this, tilemap_get_info_delegate(*this, FUNC(tc0180vcu_device::get_fg_tile_info)), TILEMAP_SCAN_ROWS, 16, 16, 64, 64);
+	m_tilemap[2] = &machine().tilemap().create(*this, tilemap_get_info_delegate(*this, FUNC(tc0180vcu_device::get_tx_tile_info)), TILEMAP_SCAN_ROWS,  8,  8, 64, 32);
+
+	m_tilemap[1]->set_transparent_pen(0);
+	m_tilemap[2]->set_transparent_pen(0);
+
+	m_framebuffer[0].allocate(512, 256);
+	m_framebuffer[1].allocate(512, 256);
+
+	screen().register_vblank_callback(vblank_state_delegate(&tc0180vcu_device::vblank_callback, this));
+	m_intl_timer = timer_alloc(FUNC(tc0180vcu_device::update_intl), this);
+
+	save_item(NAME(m_bg_rambank));
+	save_item(NAME(m_fg_rambank));
+	save_item(NAME(m_tx_rambank));
+
+	save_item(NAME(m_framebuffer_page));
+
+	save_item(NAME(m_video_control));
+
+	save_item(NAME(m_framebuffer[0]));
+	save_item(NAME(m_framebuffer[1]));
+}
+
+//-------------------------------------------------
+//  device_reset - device-specific reset
+//-------------------------------------------------
+
+void tc0180vcu_device::device_reset()
+{
+	for (int i = 0; i < 0x10; i++)
+		m_ctrl[i] = 0;
+
+	m_bg_rambank[0] = 0;
+	m_bg_rambank[1] = 0;
+	m_fg_rambank[0] = 0;
+	m_fg_rambank[1] = 0;
+	m_tx_rambank = 0;
+
+	m_framebuffer_page = 0;
+	m_video_control = 0;
+}
+
+//-------------------------------------------------
+//  vblank_callback - generate blanking-related
+//  interrupts
+//-------------------------------------------------
+
+void tc0180vcu_device::vblank_callback(screen_device &screen, bool state)
+{
+	// TODO: Measure the actual duty cycle of the INTH/"INT5" (pin 67)
+	// and INTL/"INT4" (pin 66) interrupt outputs (both of which are externally
+	// encoded and acknowledged through a PAL and additional flip-flops).
+	// Is their timing programmable at all? Most registers are accounted for...
+
+	// TODO: Verify that INTH indeed fires before INTL, and not vice versa.
+
+	if (state)
+	{
+		vblank_update();
+
+		m_inth_callback(ASSERT_LINE);
+		m_intl_timer->adjust(screen.time_until_pos(screen.vpos() + 8));
+	}
+	else
+		m_intl_callback(CLEAR_LINE);
+}
+
+//-------------------------------------------------
+//  update_intl
+//-------------------------------------------------
+
+TIMER_CALLBACK_MEMBER(tc0180vcu_device::update_intl)
+{
+	m_inth_callback(CLEAR_LINE);
+	m_intl_callback(ASSERT_LINE);
+}
+
+
+/*****************************************************************************
+    DEVICE HANDLERS
+*****************************************************************************/
+
+/* TC0180VCU control registers:
+* offset:
+* 0 - -----xxx bg ram page 0 (tile codes)
+*     -xxx---- bg ram page 1 (attributes)
+* 1 - -----xxx fg ram page 0 (tile codes)
+*     -xxx---- fg ram page 1 (attributes)
+* 2 - xxxxxxxx number of independent foreground scrolling blocks (see below)
+* 3 - xxxxxxxx number of independent background scrolling blocks
+* 4 - --xxxxxx text tile bank 0
+* 5 - --xxxxxx text tile bank 1
+* 6 - ----xxxx text ram page
+* 7 - xxxxxxxx video control: pixelram page and enable, screen flip, sprite to foreground priority (see below)
+* 8 to f - unused (always zero)
+*
+******************************************************************************************
+*
+* offset 6 - text video page register:
+*            This location controls which page of video text ram to view
+* hitice:
+*     0x08 (00001000) - show game text: credits XX, player1 score
+*     0x09 (00001001) - show FBI logo
+* rambo3:
+*     0x08 (00001000) - show game text
+*     0x09 (00001001) - show taito logo
+*     0x0a (00001010) - used in pair with 0x09 to smooth screen transitions (attract mode)
+*
+* Is bit 3 (0x08) video text enable/disable ?
+*
+******************************************************************************************
+*
+* offset 7 - video control register:
+*            bit 0 (0x01) 1 = don't erase sprite frame buffer "after the beam"
+*            bit 3 (0x08) sprite to foreground priority
+*                         1 = bg, fg, obj, tx
+*                         0 = bg, obj1, fg, obj0, tx (obj0/obj1 selected by bit 0 of color code)
+*            bit 4 (0x10) screen flip (active HI) (this one is for sure)
+*            bit 5 (0x20) could be global video enable switch (Hit the Ice clears this
+*                         bit, clears videoram portions and sets this bit)
+*            bit 6 (0x40) frame buffer page to show when bit 7 is set
+*            bit 7 (0x80) don't flip frame buffer every vblank, use the page selected by bit 6
+*
+*/
+
+void tc0180vcu_device::video_control(uint8_t data)
+{
+#if 0
+	if (data != m_video_control)
+		popmessage("video control = %02x", data);
+#endif
+
+	m_video_control = data;
+
+	if (BIT(m_video_control, 7))
+		m_framebuffer_page = BIT(~m_video_control, 6);
+
+	machine().tilemap().set_flip_all(BIT(m_video_control, 4) ? (TILEMAP_FLIPX | TILEMAP_FLIPY) : 0 );
+}
+
+void tc0180vcu_device::ctrl_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	uint16_t const oldword = m_ctrl[offset];
+
+	COMBINE_DATA (&m_ctrl[offset]);
+
+	if (oldword ^ m_ctrl[offset])
+	{
+		if (ACCESSING_BITS_8_15)
+		{
+			switch(offset)
+			{
+			case 0:
+				m_tilemap[1]->mark_all_dirty();
+				m_fg_rambank[0] = (((m_ctrl[offset] >> 8) & 0x0f) << 12);
+				m_fg_rambank[1] = (((m_ctrl[offset] >> 12) & 0x0f) << 12);
+				break;
+			case 1:
+				m_tilemap[0]->mark_all_dirty();
+				m_bg_rambank[0] = (((m_ctrl[offset] >> 8) & 0x0f) << 12);
+				m_bg_rambank[1] = (((m_ctrl[offset] >> 12) & 0x0f) << 12);
+				break;
+			case 4:
+			case 5:
+				m_tilemap[2]->mark_all_dirty();
+				break;
+			case 6:
+				m_tilemap[2]->mark_all_dirty();
+				m_tx_rambank = (((m_ctrl[offset] >> 8) & 0x0f) << 11);
+				break;
+			case 7:
+				video_control((m_ctrl[offset] >> 8) & 0xff);
+				break;
+			default:
+				break;
+			}
+		}
+	}
+}
+
+uint16_t tc0180vcu_device::framebuffer_word_r(offs_t offset)
+{
+	int const sy = offset >> 8;
+	int const sx = 2 * (offset & 0xff);
+
+	return (m_framebuffer[sy >> 8].pix(sy & 0xff, sx + 0) << 8) | m_framebuffer[sy >> 8].pix(sy & 0xff, sx + 1);
+}
+
+void tc0180vcu_device::framebuffer_word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	int const sy = offset >> 8;
+	int const sx = 2 * (offset & 0xff);
+
+	if (ACCESSING_BITS_8_15)
+		m_framebuffer[sy >> 8].pix(sy & 0xff, sx + 0) = data >> 8;
+	if (ACCESSING_BITS_0_7)
+		m_framebuffer[sy >> 8].pix(sy & 0xff, sx + 1) = data & 0xff;
+}
+
+TILE_GET_INFO_MEMBER(tc0180vcu_device::get_bg_tile_info)
+{
+	int const tile  = m_vram[tile_index + m_bg_rambank[0]];
+	int const color = m_vram[tile_index + m_bg_rambank[1]];
+
+	tileinfo.set(1, tile,
+		m_bg_color_base + (color & 0x3f),
+		TILE_FLIPYX((color & 0x00c0) >> 6));
+}
+
+TILE_GET_INFO_MEMBER(tc0180vcu_device::get_fg_tile_info)
+{
+	int const tile  = m_vram[tile_index + m_fg_rambank[0]];
+	int const color = m_vram[tile_index + m_fg_rambank[1]];
+
+	tileinfo.set(1, tile,
+		m_fg_color_base + (color & 0x3f),
+		TILE_FLIPYX((color & 0x00c0) >> 6));
+}
+
+TILE_GET_INFO_MEMBER(tc0180vcu_device::get_tx_tile_info)
+{
+	int const tile = m_vram[tile_index + m_tx_rambank];
+
+	tileinfo.set(0,
+		(tile & 0x07ff) | ((m_ctrl[4 + BIT(tile, 11)] >> 8) << 11),
+		m_tx_color_base + ((tile >> 12) & 0x0f),
+		0);
+}
+
+void tc0180vcu_device::word_w(offs_t offset, uint16_t data, uint16_t mem_mask)
+{
+	COMBINE_DATA(&m_vram[offset]);
+
+	if ((offset & 0x7000) == m_fg_rambank[0] || (offset & 0x7000) == m_fg_rambank[1])
+		m_tilemap[1]->mark_tile_dirty(offset & 0x0fff);
+
+	if ((offset & 0x7000) == m_bg_rambank[0] || (offset & 0x7000) == m_bg_rambank[1])
+		m_tilemap[0]->mark_tile_dirty(offset & 0x0fff);
+
+	if ((offset & 0x7800) == m_tx_rambank)
+		m_tilemap[2]->mark_tile_dirty(offset & 0x7ff);
+}
+
+void tc0180vcu_device::tilemap_draw(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int tmap_num, int plane)
+{
+	assert(tmap_num < 3);
+
+	if (tmap_num == 2)
+		m_tilemap[2]->draw(screen, bitmap, cliprect, 0, 0);    /* not much to do for tx_tilemap */
+	else
+	{
+		/*plane = 0 fg tilemap*/
+		/*plane = 1 bg tilemap*/
+		rectangle my_clip;
+
+		int const lines_per_block = 256 - (m_ctrl[2 + plane] >> 8);    /* number of lines scrolled by the same amount (per one scroll value) */
+		int const number_of_blocks = 256 / lines_per_block;   /* number of such blocks per _screen_ (256 lines) */
+
+		my_clip.min_x = cliprect.min_x;
+		my_clip.max_x = cliprect.max_x;
+
+		for (int i = 0; i < number_of_blocks; i++)
+		{
+			int const scrollx = m_scrollram[plane * 0x200 + i * 2 * lines_per_block];
+			int const scrolly = m_scrollram[plane * 0x200 + i * 2 * lines_per_block + 1];
+
+			my_clip.min_y = i * lines_per_block;
+			my_clip.max_y = (i + 1) * lines_per_block - 1;
+
+			if (BIT(m_video_control, 4))   /*flip screen*/
+			{
+				my_clip.min_y = bitmap.height() - 1 - (i + 1) * lines_per_block - 1;
+				my_clip.max_y = bitmap.height() - 1 - i * lines_per_block;
+			}
+
+			my_clip &= cliprect;
+
+			if (my_clip.min_y <= my_clip.max_y)
+			{
+				m_tilemap[tmap_num]->set_scrollx(0, -scrollx);
+				m_tilemap[tmap_num]->set_scrolly(0, -scrolly);
+				m_tilemap[tmap_num]->draw(screen, bitmap, my_clip, 0, 0);
+			}
+		}
+	}
+}
+
+void tc0180vcu_device::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
+{
+/*  Sprite format: (16 bytes per sprite)
+  offs:             bits:
+  0000: 0xxxxxxxxxxxxxxx: tile code - 0x0000 to 0x7fff in qzshowby
+  0002: 0000000000xxxxxx: color (0x00 - 0x3f)
+        x000000000000000: flipy
+        0x00000000000000: flipx
+        00????????000000: unused ?
+  0004: xxxxxx0000000000: doesn't matter - some games (eg nastar) fill this with sign bit, some (eg ashura) do not
+        000000xxxxxxxxxx: x-coordinate 10 bits signed (all zero for sprites forming up a big sprite, except for the first one)
+  0006: xxxxxx0000000000: doesn't matter - same as x
+        000000xxxxxxxxxx: y-coordinate 10 bits signed (same as x)
+  0008: xxxxxxxx00000000: sprite x-zoom level
+        00000000xxxxxxxx: sprite y-zoom level
+      0x00 - non scaled = 100%
+      0x80 - scaled to 50%
+      0xc0 - scaled to 25%
+      0xe0 - scaled to 12.5%
+      0xff - scaled to zero pixels size (off)
+      Sprite zoom is used in Ashura Blaster just in the beginning
+      where you can see a big choplifter and a japanese title.
+      This japanese title is a scaled sprite.
+      It is used in Crime City also at the end of the third level (in the garage)
+      where there are four columns on the sides of the screen
+      Heaviest usage is in Rambo 3 - almost every sprite in game is scaled
+  000a: xxxxxxxx00000000: x-sprites number (big sprite) decremented by one
+        00000000xxxxxxxx: y-sprites number (big sprite) decremented by one
+  000c - 000f: unused
+*/
+
+	int xlatch = 0, ylatch = 0, x_no = 0, y_no = 0, x_num = 0, y_num = 0;
+	uint32_t zoomxlatch = 0, zoomylatch = 0;
+	bool big_sprite = false;
+
+	for (int offs = (0x1980 - 16) / 2; offs >=0; offs -= 8)
+	{
+		int code = m_spriteram[offs];
+
+		int color = m_spriteram[offs + 1];
+		bool const flipx = BIT(color, 14);
+		bool const flipy = BIT(color, 15);
+#if 0
+		/*check the unknown bits*/
+		if (color & 0x3fc0)
+		{
+			logerror("sprite color (taitob)=%4x ofs=%4x\n", color, offs);
+			color = machine().rand() & 0x3f;
+		}
+#endif
+		color = (color & 0x3f) * 16;
+
+		int x = m_spriteram[offs + 2] & 0x3ff;
+		int y = m_spriteram[offs + 3] & 0x3ff;
+		if (x >= 0x200)  x -= 0x400;
+		if (y >= 0x200)  y -= 0x400;
+
+		uint32_t data = m_spriteram[offs + 5];
+		if (data)
+		{
+			if (!big_sprite)
+			{
+				x_num = (data >> 8) & 0xff;
+				y_num = (data >> 0) & 0xff;
+				x_no  = 0;
+				y_no  = 0;
+				xlatch = x;
+				ylatch = y;
+				data = m_spriteram[offs + 4];
+				zoomxlatch = (data >> 8) & 0xff;
+				zoomylatch = (data >> 0) & 0xff;
+				big_sprite = true;
+			}
+		}
+
+		data = m_spriteram[offs + 4];
+		uint32_t zoomx = (data >> 8) & 0xff;
+		uint32_t zoomy = (data >> 0) & 0xff;
+		uint32_t zx = (0x100 - zoomx) / 16;
+		uint32_t zy = (0x100 - zoomy) / 16;
+
+		if (big_sprite)
+		{
+			zoomx = zoomxlatch;
+			zoomy = zoomylatch;
+
+			/* Note: like taito/taito_f2.cpp, this zoom implementation is wrong,
+			chopped up into 16x16 sections instead of one sprite. This
+			is especially visible in rambo3. */
+
+			x = xlatch + (x_no * (0xff - zoomx) + 15) / 16;
+			y = ylatch + (y_no * (0xff - zoomy) + 15) / 16;
+			zx = xlatch + ((x_no + 1) * (0xff - zoomx) + 15) / 16 - x;
+			zy = ylatch + ((y_no + 1) * (0xff - zoomy) + 15) / 16 - y;
+			y_no++;
+
+			if (y_no > y_num)
+			{
+				y_no = 0;
+				x_no++;
+
+				if (x_no > x_num)
+					big_sprite = false;
+			}
+		}
+
+		if (zoomx || zoomy)
+		{
+			gfx(1)->zoom_transpen_raw(bitmap,cliprect,
+				code,
+				color,
+				flipx, flipy,
+				x,y,
+				(zx << 16) / 16,(zy << 16) / 16,0);
+		}
+		else
+		{
+			gfx(1)->transpen_raw(bitmap,cliprect,
+				code,
+				color,
+				flipx, flipy,
+				x,y,
+				0);
+		}
+	}
+}
+
+void tc0180vcu_device::draw_framebuffer(bitmap_ind16 &bitmap, const rectangle &cliprect, int priority)
+{
+	rectangle myclip = cliprect;
+
+	auto profile = g_profiler.start(PROFILER_USER1);
+
+	priority <<= 4;
+
+	if (BIT(m_video_control, 3))
+	{
+		if (priority)
+			return;
+
+		if (BIT(m_video_control, 4))   /*flip screen*/
+		{
+			/*popmessage("1. X[%3i;%3i] Y[%3i;%3i]", myclip.min_x, myclip.max_x, myclip.min_y, myclip.max_y);*/
+			for (int y = myclip.min_y; y <= myclip.max_y; y++)
+			{
+				uint16_t const *src = &m_framebuffer[m_framebuffer_page].pix(y, myclip.min_x);
+				uint16_t *dst = &bitmap.pix(bitmap.height()-1-y, myclip.max_x);
+
+				for (int x = myclip.min_x; x <= myclip.max_x; x++)
+				{
+					uint16_t c = *src++;
+
+					if (c != 0)
+						*dst = m_fb_color_base + c;
+
+					dst--;
+				}
+			}
+		}
+		else
+		{
+			for (int y = myclip.min_y; y <= myclip.max_y; y++)
+			{
+				uint16_t const *src = &m_framebuffer[m_framebuffer_page].pix(y, myclip.min_x);
+				uint16_t *dst = &bitmap.pix(y, myclip.min_x);
+
+				for (int x = myclip.min_x; x <= myclip.max_x; x++)
+				{
+					uint16_t c = *src++;
+
+					if (c != 0)
+						*dst = m_fb_color_base + c;
+
+					dst++;
+				}
+			}
+		}
+	}
+	else
+	{
+		if (BIT(m_video_control, 4))   /*flip screen*/
+		{
+			/*popmessage("3. X[%3i;%3i] Y[%3i;%3i]", myclip.min_x, myclip.max_x, myclip.min_y, myclip.max_y);*/
+			for (int y = myclip.min_y ;y <= myclip.max_y; y++)
+			{
+				uint16_t const *src = &m_framebuffer[m_framebuffer_page].pix(y, myclip.min_x);
+				uint16_t *dst = &bitmap.pix(bitmap.height()-1-y, myclip.max_x);
+
+				for (int x = myclip.min_x; x <= myclip.max_x; x++)
+				{
+					uint16_t c = *src++;
+
+					if (c != 0 && (c & 0x10) == priority)
+						*dst = m_fb_color_base + c;
+
+					dst--;
+				}
+			}
+		}
+		else
+		{
+			for (int y = myclip.min_y; y <= myclip.max_y; y++)
+			{
+				uint16_t const *src = &m_framebuffer[m_framebuffer_page].pix(y, myclip.min_x);
+				uint16_t *dst = &bitmap.pix(y, myclip.min_x);
+
+				for (int x = myclip.min_x; x <= myclip.max_x; x++)
+				{
+					uint16_t c = *src++;
+
+					if (c != 0 && (c & 0x10) == priority)
+						*dst = m_fb_color_base + c;
+
+					dst++;
+				}
+			}
+		}
+	}
+}
+
+void tc0180vcu_device::vblank_update()
+{
+	if (BIT(~m_video_control, 0))
+		m_framebuffer[m_framebuffer_page].fill(0, screen().visible_area());
+
+	if (BIT(~m_video_control, 7))
+		m_framebuffer_page ^= 1;
+
+	draw_sprites(m_framebuffer[m_framebuffer_page], screen().visible_area());
+}
diff --git a/cores/taitob/doc/tc0180vcu.h b/cores/taitob/doc/tc0180vcu.h
new file mode 100644
index 000000000..93fb18ae4
--- /dev/null
+++ b/cores/taitob/doc/tc0180vcu.h
@@ -0,0 +1,81 @@
+// license:BSD-3-Clause
+// copyright-holders:Nicola Salmoria
+#ifndef MAME_TAITO_TC0180VCU_H
+#define MAME_TAITO_TC0180VCU_H
+
+#pragma once
+
+#include "tilemap.h"
+
+
+class tc0180vcu_device : public device_t, public device_gfx_interface, public device_video_interface
+{
+public:
+	tc0180vcu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
+
+	// configuration
+	void set_fb_colorbase(int color) { m_fb_color_base = color * 16; }
+	void set_bg_colorbase(int color) { m_bg_color_base = color; }
+	void set_fg_colorbase(int color) { m_fg_color_base = color; }
+	void set_tx_colorbase(int color) { m_tx_color_base = color; }
+	auto inth_callback() { return m_inth_callback.bind(); }
+	auto intl_callback() { return m_intl_callback.bind(); }
+
+	uint8_t get_videoctrl() { return m_video_control; }
+	void ctrl_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+	void word_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+	uint16_t framebuffer_word_r(offs_t offset);
+	void framebuffer_word_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
+	void tilemap_draw(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect, int tmap_num, int plane);
+	void draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect );
+	void draw_framebuffer( bitmap_ind16 &bitmap, const rectangle &cliprect, int priority );
+
+	void tc0180vcu_memrw(address_map &map) ATTR_COLD;
+protected:
+	// device_t implementation
+	virtual void device_start() override ATTR_COLD;
+	virtual void device_reset() override ATTR_COLD;
+
+	TIMER_CALLBACK_MEMBER(update_intl);
+
+private:
+	void vblank_callback(screen_device &screen, bool state);
+	void vblank_update();
+
+	// internal state
+
+	required_shared_ptr<uint16_t> m_spriteram;
+	required_shared_ptr<uint16_t> m_vram;
+	required_shared_ptr<uint16_t> m_scrollram;
+	required_shared_ptr<uint16_t> m_ctrl;
+	/* framebuffer is a raw bitmap, remapped as a last step */
+	bitmap_ind16 m_framebuffer[2];
+
+	tilemap_t    *m_tilemap[3]{};
+
+	uint16_t     m_bg_rambank[2], m_fg_rambank[2], m_tx_rambank;
+	uint8_t      m_framebuffer_page;
+	uint8_t      m_video_control;
+
+	int          m_fb_color_base;
+	int          m_bg_color_base;
+	int          m_fg_color_base;
+	int          m_tx_color_base;
+
+	static const gfx_layout charlayout, tilelayout;
+	DECLARE_GFXDECODE_MEMBER(gfxinfo);
+
+	devcb_write_line m_inth_callback;
+	devcb_write_line m_intl_callback;
+	emu_timer *m_intl_timer;
+
+	TILE_GET_INFO_MEMBER(get_bg_tile_info);
+	TILE_GET_INFO_MEMBER(get_fg_tile_info);
+	TILE_GET_INFO_MEMBER(get_tx_tile_info);
+
+	void video_control(uint8_t data);
+};
+
+DECLARE_DEVICE_TYPE(TC0180VCU, tc0180vcu_device)
+
+#endif // MAME_TAITO_TC0180VCU_H
diff --git a/cores/taitob/hdl/jttaitob_colmix.v b/cores/taitob/hdl/jttaitob_colmix.v
new file mode 100644
index 000000000..02cc5576e
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_colmix.v
@@ -0,0 +1,95 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    Author: Andrea Bogazzi.
+    Date: 5-2026 */
+
+// ============================================================================
+// jttaitob_colmix — TC0260DAR replacement
+// ============================================================================
+//
+// The TC0260DAR is a passive 12-bit RGBx_444 palette DAC (no internal
+// logic in MAME — it's just a palette_device with RGBx_444 format,
+// taito_b.cpp:1887). Palette RAM lives at 0x200000-0x201FFF and is
+// owned by jttaitob_main.v's u_pal BRAM (2048 words = 4 KB).
+//
+// In Phase 2 this module *owns* the palette read:
+//   1. Receives a 12-bit palette index from jttaitob_video.
+//   2. Drives pal_addr_b into main.v's u_pal BRAM port-B.
+//   3. Receives the 16-bit palette word.
+//   4. Splits into 4-bit R/G/B channels (the "x" nibble at [15:12] is
+//      unused — TC0260DAR has only 3 colour outputs).
+//
+// Palette word layout (TC0260DAR): MAME `palette_device::RGBx_444` —
+// the "x" is the LOW nibble; R/G/B occupy the upper three nibbles:
+//   bits [15:12] = R
+//   bits [11: 8] = G
+//   bits [ 7: 4] = B
+//   bits [ 3: 0] = unused (x)
+// The previous decode treated this as `xRGB_444` (x in HIGH nibble),
+// which painted the BG plane olive-green where it should have been
+// blue: the game's blue word `0x00B0` (R=0,G=0,B=B,x=0) ended up
+// driving the GREEN channel.
+//
+// Note: the BRAM read latency is 1 clk cycle. pal_addr_b is registered
+// in this module so the read result is stable on the next pxl_cen.
+// ============================================================================
+
+module jttaitob_colmix(
+    input               rst,
+    input               clk,
+    input               pxl_cen,
+
+    input               LHBL,
+    input               LVBL,
+
+    // From jttaitob_video — 12-bit palette index (0..4095).
+    // The MAME 4096-entry palette is laid out per the BG/FG/TX/sprite
+    // color_base regions (0x00 sprite, 0x80 FG, 0xC0 BG, 0x00 text).
+    // For Phase 2 only BG matters (high quarter of the palette).
+    input        [11:0] pal_idx,
+
+    // Palette RAM port-B — read interface to main.v's u_pal BRAM.
+    // pal_addr_b indexes the full 4096-word (8 KB) palette RAM with the
+    // 12-bit pal_idx. The BG color base 0xC0 lands at index 0xC00, which
+    // is above the lower 2K, so the whole 12-bit index is needed.
+    output reg   [11:0] pal_addr_b,
+    input        [15:0] pal_dout_b,
+
+    output reg   [ 3:0] red,
+    output reg   [ 3:0] green,
+    output reg   [ 3:0] blue
+);
+
+/* verilator lint_off UNUSED */
+wire _unused = rst | pxl_cen | |pal_dout_b[3:0];
+/* verilator lint_on UNUSED */
+
+// Register the palette index so the BRAM read settles before pxl_cen
+// fires the RGB latch. The visible-pipeline latency becomes 1 clk —
+// invisible at 6.79 MHz pixel rate over 48 MHz system clk.
+always @(posedge clk) begin
+    pal_addr_b <= pal_idx[11:0];
+end
+
+always @(posedge clk) begin
+    if (!LHBL || !LVBL) begin
+        red   <= 4'd0;
+        green <= 4'd0;
+        blue  <= 4'd0;
+    end else begin
+        red   <= pal_dout_b[15:12];
+        green <= pal_dout_b[11: 8];
+        blue  <= pal_dout_b[ 7: 4];
+    end
+end
+
+endmodule
diff --git a/cores/taitob/hdl/jttaitob_game.v b/cores/taitob/hdl/jttaitob_game.v
new file mode 100644
index 000000000..13d2d4a76
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_game.v
@@ -0,0 +1,415 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    Author: Andrea Bogazzi.
+    Date: 5-2026 */
+
+// ============================================================================
+// jttaitob_game — top-level wrapper for the Taito B System core
+// ============================================================================
+//
+// First target: Rastan Saga 2 / Nastar / Nastar Warrior (rastsag2 set).
+//
+// Wires together:
+//   • jttaitob_main  (68000 @ 12 MHz + work RAM + palette RAM + VRAM +
+//                     sprite/scroll RAM + VCU ctrl regs + chip selects)
+//   • jttaitob_snd   (Z80 @ 4 MHz + YM2610 @ 8 MHz)
+//   • jttaitob_syt   (TC0140SYT — main↔Z80 sound comms)
+//   • jttaitob_ioc   (TC0220IOC — DIPs + cabinet inputs + coin/lockout)
+//   • jttaitob_video (stub — palette viewer; real TC0180VCU pipeline TBD)
+//   • jttaitob_colmix(TC0260DAR passive palette DAC → RGB)
+//   • jtframe_cen48  (clock enables for 12 / 8 / 4 MHz)
+//   • jtframe_vtimer (320×224 raster at 8 MHz pxl_cen ≈ 60 Hz)
+//
+// First-iteration scope: 68k spine + sound subsystem + video timing.
+// The video output is a palette-viewer (whatever the 68k writes to
+// palette becomes visible as a grid). Real tile/sprite pipeline lands
+// once the TC0180VCU bring-up starts.
+// ============================================================================
+
+module jttaitob_game(
+    `include "jtframe_game_ports.inc"
+);
+
+// ─────────────────────────────────────────────────────────────────────────────
+// Wires between submodules
+// ─────────────────────────────────────────────────────────────────────────────
+wire [23:1] cpu_addr;
+wire [ 1:0] main_dsn;
+wire [15:0] main_dout;
+wire        main_rnw;
+
+// Sound: jt10 stereo output (framework auto-generates fm_l/fm_r as outputs
+// because cfg/mem.yaml declares an `fm` channel).
+wire signed [15:0] fm_l_w, fm_r_w;
+assign fm_l = fm_l_w;
+assign fm_r = fm_r_w;
+
+`ifdef JTFRAME_IOCTL_RD
+    assign ioctl_din = 8'h0;
+`endif
+
+// TC0140SYT master side wires (68k <-> SYT)
+wire        syt_cs_w, syt_addr_w, syt_we_w;
+wire [ 3:0] syt_din_w, syt_dout_w;
+
+// TC0220IOC bus
+wire        ioc_cs_w, ioc_rnw_w, ioc_lds_n_w;
+wire [ 3:0] ioc_addr_w;
+wire [ 7:0] ioc_din_w, ioc_dout_w;
+
+// VCU ctrl regs (latched in main.v, consumed in video.v)
+wire [127:0] vcu_ctrl_w;
+
+// Video subsystem BRAM port-B
+wire [11:0] pal_addr_b_w;
+wire [15:0] pal_dout_b_w;
+wire [14:0] vram_addr_b_w;
+wire [15:0] vram_dout_b_w;
+wire [12:0] oram_addr_b_w;
+wire [15:0] oram_dout_b_w;
+
+// DIP slicing — JTFRAME packs the dipsw into 32 bits low-to-high
+wire [ 7:0] dipsw_a = dipsw[ 7:0];
+wire [ 7:0] dipsw_b = dipsw[15:8];
+
+// Cabinet I/O packing — TAITO_B_SYSTEM_INPUT layout (taito_b.cpp:664).
+// Taito B uses TAITO_JOY_UDLR_2_BUTTONS (NOT the `_START` variant); the
+// START buttons live on IN2, not IN0/IN1.
+//
+//   IN0/IN1 (TAITO_JOY_UDLR_2_BUTTONS):
+//     bit 0 = UP        (active low)
+//     bit 1 = DOWN
+//     bit 2 = LEFT
+//     bit 3 = RIGHT
+//     bit 4 = BUTTON1
+//     bit 5 = BUTTON2
+//     bit 6 = unused (1)
+//     bit 7 = unused (1)
+//
+//   IN2 (TAITO_B_SYSTEM_INPUT):
+//     bit 0 = TILT      (active low)
+//     bit 1 = SERVICE1
+//     bit 2 = COIN1
+//     bit 3 = COIN2
+//     bit 4 = unused (1)
+//     bit 5 = unused (1)
+//     bit 6 = START1
+//     bit 7 = START2
+//
+// joystick1[5:0] = {B2, B1, R, L, D, U} after JTFRAME_JOY_RLDU bit-swap,
+// which matches MAME's IN0[5:0] verbatim.
+wire [ 7:0] cab_in0 = { 2'b11, joystick1[5:0] };
+wire [ 7:0] cab_in1 = { 2'b11, joystick2[5:0] };
+wire [ 7:0] cab_in2 = { cab_1p[1], cab_1p[0], 2'b11, coin[1], coin[0], service, tilt };
+
+// Debug merging
+wire [ 7:0] main_st, snd_st;
+assign st_dout    = (debug_bus[7]) ? snd_st : main_st;
+assign debug_view = main_st;
+assign dip_flip   = 1'b0;
+
+// ─────────────────────────────────────────────────────────────────────────────
+// Clock enables (48 MHz → 12 / 8 / 4 / 3 MHz etc.)
+// ─────────────────────────────────────────────────────────────────────────────
+wire cen12, cen8, cen4, cen6, cen3, cen3q, cen1p5;
+wire cen16, cen4_12;
+wire cen16b, cen12b, cen6b, cen3b, cen3qb, cen1p5b;
+
+jtframe_cen48 u_cen48(
+    .clk      ( clk      ),
+    .cen12    ( cen12    ),
+    .cen16    ( cen16    ),
+    .cen8     ( cen8     ),
+    .cen6     ( cen6     ),
+    .cen4     ( cen4     ),
+    .cen4_12  ( cen4_12  ),
+    .cen3     ( cen3     ),
+    .cen3q    ( cen3q    ),
+    .cen1p5   ( cen1p5   ),
+    .cen16b   ( cen16b   ),
+    .cen12b   ( cen12b   ),
+    .cen6b    ( cen6b    ),
+    .cen3b    ( cen3b    ),
+    .cen3qb   ( cen3qb   ),
+    .cen1p5b  ( cen1p5b  )
+);
+
+// Suppress lint warnings on cens we don't currently use
+/* verilator lint_off UNUSED */
+wire _unused_cens = cen12 | cen16 | cen6 | cen4_12 | cen3 | cen3q | cen1p5 |
+                    cen16b | cen12b | cen6b | cen3b | cen3qb | cen1p5b;
+/* verilator lint_on UNUSED */
+
+// ─────────────────────────────────────────────────────────────────────────────
+// 68k main CPU subsystem
+// ─────────────────────────────────────────────────────────────────────────────
+jttaitob_main u_main(
+    .rst        ( rst48              ),
+    .clk        ( clk48              ),
+    .LVBL       ( LVBL               ),
+    .LHBL       ( LHBL               ),
+    .dip_pause  ( dip_pause          ),
+
+    // ROM (SDRAM bank 0, "main" bus from mem.yaml)
+    .cpu_addr   ( cpu_addr           ),
+    .main_addr  ( main_addr          ),
+    .main_dsn   ( main_dsn           ),
+    .main_dout  ( main_dout          ),
+    .main_rnw   ( main_rnw           ),
+    .rom_cs     ( main_cs            ),
+    .rom_data   ( main_data          ),
+    .rom_ok     ( main_ok            ),
+
+    // Video BRAM port-B
+    .pal_addr_b  ( pal_addr_b_w      ),
+    .pal_dout_b  ( pal_dout_b_w      ),
+    .vram_addr_b ( vram_addr_b_w     ),
+    .vram_dout_b ( vram_dout_b_w     ),
+    .oram_addr_b ( oram_addr_b_w     ),
+    .oram_dout_b ( oram_dout_b_w     ),
+    .vcu_ctrl    ( vcu_ctrl_w        ),
+
+    // TC0140SYT master port
+    .syt_cs      ( syt_cs_w          ),
+    .syt_addr    ( syt_addr_w        ),
+    .syt_we      ( syt_we_w          ),
+    .syt_din     ( syt_din_w         ),
+    .syt_dout    ( syt_dout_w        ),
+
+    // TC0220IOC
+    .ioc_cs      ( ioc_cs_w          ),
+    .ioc_addr    ( ioc_addr_w        ),
+    .ioc_rnw     ( ioc_rnw_w         ),
+    .ioc_lds_n   ( ioc_lds_n_w       ),
+    .ioc_din     ( ioc_din_w         ),
+    .ioc_dout    ( ioc_dout_w        ),
+
+    .debug_bus  ( debug_bus          ),
+    .st_dout    ( main_st            )
+);
+
+// ─────────────────────────────────────────────────────────────────────────────
+// TC0140SYT — sound-comm chip between 68k and Z80
+// ─────────────────────────────────────────────────────────────────────────────
+wire        snd_rom_cs_w, snd_ram_cs_w, snd_ym_cs_w, snd_syt_sel_w;
+wire [ 1:0] snd_rom_a16_w;
+wire        snd_rst_w, snd_nmi_n_w;
+wire [ 7:0] syt_z80_dout;
+wire [15:0] z80_addr_w;
+wire [ 7:0] z80_dout_w;
+wire        z80_mreq_n_w, z80_rd_n_w, z80_wr_n_w;
+
+jttaitob_syt u_syt(
+    .rst        ( rst48              ),
+    .clk        ( clk48              ),
+
+    // 68k master
+    .main_cs    ( syt_cs_w           ),
+    .main_addr  ( syt_addr_w         ),
+    .main_dout  ( syt_din_w          ),
+    .main_din   ( syt_dout_w         ),
+    .main_we    ( syt_we_w           ),
+
+    // Z80 slave
+    .snd_addr   ( z80_addr_w         ),
+    .snd_dout   ( z80_dout_w         ),
+    .snd_din    ( syt_z80_dout       ),
+    .snd_mreq_n ( z80_mreq_n_w       ),
+    .snd_rd_n   ( z80_rd_n_w         ),
+    .snd_wr_n   ( z80_wr_n_w         ),
+
+    .snd_rom_cs ( snd_rom_cs_w       ),
+    .snd_rom_a16( snd_rom_a16_w      ),
+    .snd_ram_cs ( snd_ram_cs_w       ),
+    .snd_ym_cs  ( snd_ym_cs_w        ),
+    .snd_syt_sel( snd_syt_sel_w      ),
+    .snd_rst    ( snd_rst_w          ),
+    .snd_nmi_n  ( snd_nmi_n_w        )
+);
+
+// ─────────────────────────────────────────────────────────────────────────────
+// Z80 + YM2610 sound subsystem
+// ─────────────────────────────────────────────────────────────────────────────
+jttaitob_snd u_snd(
+    .rst         ( rst48             ),
+    .clk         ( clk48             ),
+    .cen_z80     ( cen4              ),
+    .cen_ym      ( cen8              ),
+
+    .snd_rom_cs  ( snd_rom_cs_w      ),
+    .snd_rom_a16 ( snd_rom_a16_w     ),
+    .snd_ram_cs  ( snd_ram_cs_w      ),
+    .snd_ym_cs   ( snd_ym_cs_w       ),
+    .snd_syt_sel ( snd_syt_sel_w     ),
+    .snd_rst_soft( snd_rst_w         ),
+    .snd_nmi_n   ( snd_nmi_n_w       ),
+    .syt_dout_z80( syt_z80_dout      ),
+
+    .z80_addr    ( z80_addr_w        ),
+    .z80_dout    ( z80_dout_w        ),
+    .z80_mreq_n  ( z80_mreq_n_w      ),
+    .z80_rd_n    ( z80_rd_n_w        ),
+    .z80_wr_n    ( z80_wr_n_w        ),
+
+    .rom_addr    ( snd_addr          ),
+    .rom_cs      ( snd_cs            ),
+    .rom_data    ( snd_data          ),
+    .rom_ok      ( snd_ok            ),
+
+    .adpcma_addr ( adpcma_addr       ),
+    .adpcma_cs   ( adpcma_cs         ),
+    .adpcma_data ( adpcma_data       ),
+    .adpcma_ok   ( adpcma_ok         ),
+
+    .adpcmb_addr ( adpcmb_addr       ),
+    .adpcmb_cs   ( adpcmb_cs         ),
+    .adpcmb_data ( adpcmb_data       ),
+    .adpcmb_ok   ( adpcmb_ok         ),
+
+    .fm_l        ( fm_l_w            ),
+    .fm_r        ( fm_r_w            ),
+
+    .debug_bus   ( debug_bus         ),
+    .st_dout     ( snd_st            )
+);
+
+// ─────────────────────────────────────────────────────────────────────────────
+// TC0220IOC — I/O controller
+// ─────────────────────────────────────────────────────────────────────────────
+jttaitob_ioc u_ioc(
+    .rst        ( rst48              ),
+    .clk        ( clk48              ),
+
+    .cs         ( ioc_cs_w           ),
+    .addr       ( ioc_addr_w         ),
+    .rnw        ( ioc_rnw_w          ),
+    .lds_n      ( ioc_lds_n_w        ),
+    .din        ( ioc_din_w          ),
+    .dout       ( ioc_dout_w         ),
+
+    .dipsw_a    ( dipsw_a            ),
+    .dipsw_b    ( dipsw_b            ),
+    .in0        ( cab_in0            ),
+    .in1        ( cab_in1            ),
+    .in2        ( cab_in2            )
+);
+
+// ─────────────────────────────────────────────────────────────────────────────
+// Video timing — 320×224 active, ~60 Hz at 7 MHz pxl_cen
+// ─────────────────────────────────────────────────────────────────────────────
+// 7 MHz × (448 cols × 260 rows)⁻¹ ≈ 60.10 Hz refresh, 15.625 kHz H-rate.
+// Active: hdump 0..319 (320 cols visible).
+//         vdump 15..238 (224 rows visible).
+// H-blank = 128 px (320..447) → ~878 clk @48MHz, enough for the sequential
+// BG/FG/TX ring fills (~840 clk). Image width 71% of the line.
+wire [8:0] hdump_v, vdump_v, vrender_v;
+
+jtframe_vtimer #(
+    .HB_START ( 9'd320 ),    // visible 0..319, blanking 320..447
+    .HS_START ( 9'd368 ),    // HS pulse 368..395 (27 cyc, ~3.9us @7MHz), centered
+    .HCNT_END ( 9'd447 ),    // 448-col cycle
+    .HB_END   ( 9'd0   ),
+    .V_START  ( 9'd000 ),
+    .VS_START ( 9'd245 ),    // VS pulse 245..247 (3 rows)
+    .VB_START ( 9'd239 ),    // visible ends after row 238 (15 + 224 = 239)
+    .VCNT_END ( 9'd259 ),    // 260-row cycle
+    .VB_END   ( 9'd015 )     // visible begins at row 15
+) u_vtimer(
+    .clk        ( clk     ),
+    .pxl_cen    ( pxl_cen ),
+    .vdump      ( vdump_v ),
+    .vrender    ( vrender_v ),
+    .vrender1   (         ),
+    .H          ( hdump_v ),
+    .Hinit      (         ),
+    .Vinit      (         ),
+    .LHBL       ( LHBL    ),
+    .LVBL       ( LVBL    ),
+    .HS         ( HS      ),
+    .VS         ( VS      )
+);
+
+/* verilator lint_off UNUSED */
+wire _unused_vrender = |vrender_v;
+/* verilator lint_on UNUSED */
+
+// ─────────────────────────────────────────────────────────────────────────────
+// Video pipeline (stub — palette viewer)
+// ─────────────────────────────────────────────────────────────────────────────
+wire [11:0] pal_idx_w;
+
+jttaitob_video u_video(
+    .rst         ( rst48             ),
+    .clk         ( clk48             ),
+    .pxl_cen     ( pxl_cen           ),
+
+    .LHBL        ( LHBL              ),
+    .LVBL        ( LVBL              ),
+    .vdump       ( vdump_v           ),
+    .vrender     ( vrender_v         ),
+    .hdump       ( hdump_v           ),
+
+    .vcu_ctrl    ( vcu_ctrl_w        ),
+
+    .vram_addr_b ( vram_addr_b_w     ),
+    .vram_dout_b ( vram_dout_b_w     ),
+    .oram_addr_b ( oram_addr_b_w     ),
+    .oram_dout_b ( oram_dout_b_w     ),
+
+    // SDRAM bank 2 (gfx ROM) — three buses share the 1 MB region:
+    //   bg  → BG plane gfx
+    //   obj → FG plane gfx (sprites take this in Phase 3d)
+    //   tx  → text plane gfx
+    .bg_addr     ( bg_addr           ),
+    .bg_cs       ( bg_cs             ),
+    .bg_data     ( bg_data           ),
+    .bg_ok       ( bg_ok             ),
+    .obj_addr    ( obj_addr          ),
+    .obj_cs      ( obj_cs            ),
+    .obj_data    ( obj_data          ),
+    .obj_ok      ( obj_ok            ),
+    .tx_addr     ( tx_addr           ),
+    .tx_cs       ( tx_cs             ),
+    .tx_data     ( tx_data           ),
+    .tx_ok       ( tx_ok             ),
+    .fg_addr     ( fg_addr           ),
+    .fg_cs       ( fg_cs             ),
+    .fg_data     ( fg_data           ),
+    .fg_ok       ( fg_ok             ),
+
+    .pal_idx     ( pal_idx_w         )
+);
+
+// ─────────────────────────────────────────────────────────────────────────────
+// Colour mixer (TC0260DAR)
+// ─────────────────────────────────────────────────────────────────────────────
+jttaitob_colmix u_colmix(
+    .rst        ( rst48              ),
+    .clk        ( clk48              ),
+    .pxl_cen    ( pxl_cen            ),
+
+    .LHBL       ( LHBL               ),
+    .LVBL       ( LVBL               ),
+
+    .pal_idx    ( pal_idx_w          ),
+
+    .pal_addr_b ( pal_addr_b_w      ),
+    .pal_dout_b ( pal_dout_b_w      ),
+
+    .red        ( red                ),
+    .green      ( green              ),
+    .blue       ( blue               )
+);
+
+// obj bus driven by video.v (FG plane in Phase 3a).
+
+endmodule
diff --git a/cores/taitob/hdl/jttaitob_ioc.v b/cores/taitob/hdl/jttaitob_ioc.v
new file mode 100644
index 000000000..f2eb393a1
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_ioc.v
@@ -0,0 +1,109 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Andrea Bogazzi.
+    Date: 5-2026
+
+    Reference for protocol semantics:
+      - MAME taito/taitoio.cpp::tc0220ioc_device (mirrored in
+        cores/taitob/doc/taitoio.cpp lines 200-307).
+      - Arcade-TaitoF2_MiSTer rtl/tc0220ioc.sv (GPLv2, read-only).
+        85-line register file; not copied verbatim. The behaviour is
+        small enough that two implementations from the same MAME
+        reference are essentially identical.
+*/
+
+// Taito TC0220IOC — I/O controller used by the Taito B System and the
+// earlier Taito F2 boards. 16-register window decoded by A[4:1] off the
+// 68k bus. On Taito B the chip lives on the UPPER byte lane
+// (umask16(0xff00) in MAME), so the 68k accesses register N via byte
+// addresses 0xA0000<N> on the high byte.
+//
+// Register layout (per rastsag2_map machine_config @ taito_b.cpp:1870):
+//   0x0  R: DSW A           W: watchdog reset (any value)
+//   0x1  R: DSW B           W: -
+//   0x2  R: IN0 (P1 stick + buttons + start)
+//   0x3  R: IN1 (P2 stick + buttons + start)
+//   0x4  R: coin/lockout latch (last written value)  W: coin counter / lockout
+//   0x7  R: IN2 (coin, service, tilt)
+//   others: hi-Z (return 0xFF in the real chip)
+//
+// First-cut stub: combinational reads only, no watchdog wiring, no
+// coin-meter wiring. The coin-meter callback is set via the JT
+// framework's `coin` input on the JTFRAME side; we ignore the
+// 68k's writes to register 4 for now.
+
+module jttaitob_ioc(
+    input               rst,
+    input               clk,
+
+    // 68k bus (decoded by jttaitob_main.v)
+    input               cs,
+    input        [ 3:0] addr,                    // = 68k A[4:1]
+    input               rnw,                     // 1 = read
+    input               lds_n,                   // chip on UDS lane → use UDSn
+    input        [ 7:0] din,                     // 68k high byte
+    output reg   [ 7:0] dout,
+
+    // Cabinet inputs (active LOW, packed by jttaitob_game.v)
+    input        [ 7:0] dipsw_a,
+    input        [ 7:0] dipsw_b,
+    input        [ 7:0] in0,                     // P1 stick + buttons
+    input        [ 7:0] in1,                     // P2 stick + buttons
+    input        [ 7:0] in2                      // coin / service / tilt
+);
+
+reg [7:0] coin_latch;
+
+always @* begin
+    case (addr)
+        4'h0: dout = dipsw_a;
+        4'h1: dout = dipsw_b;
+        4'h2: dout = in0;
+        4'h3: dout = in1;
+        4'h4: dout = coin_latch;
+        4'h7: dout = in2;
+        default: dout = 8'hFF;
+    endcase
+end
+
+// Writes: only register 4 (coin counters / lockout) is captured.
+// Register 0 writes are watchdog kicks — we drop them on the floor
+// since JTFRAME provides its own framework-level watchdog.
+always @(posedge clk, posedge rst) begin
+    if (rst) begin
+        coin_latch <= 8'h00;
+    end else if (cs && ~rnw && ~lds_n) begin
+        if (addr == 4'h4) coin_latch <= din;
+    end
+end
+
+`ifdef SIMULATION
+// One-shot dump of every IOC register on its first read so we can
+// confirm the CPU actually sees the DIP / cabinet bits we think it does.
+reg [7:0] seen;
+initial seen = 8'h00;
+always @(posedge clk) begin
+    if (cs && rnw && addr[3] == 1'b0 /* only first 8 regs */ ) begin
+        if (!seen[addr[2:0]]) begin
+            $display("[%0t] IOC first read reg %0d -> 0x%02h  (dipsw_a=0x%02h dipsw_b=0x%02h in0=0x%02h in1=0x%02h in2=0x%02h)",
+                     $time, addr[2:0], dout,
+                     dipsw_a, dipsw_b, in0, in1, in2);
+            seen[addr[2:0]] <= 1'b1;
+        end
+    end
+end
+`endif
+
+endmodule
diff --git a/cores/taitob/hdl/jttaitob_main.v b/cores/taitob/hdl/jttaitob_main.v
new file mode 100644
index 000000000..be664cf39
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_main.v
@@ -0,0 +1,899 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Andrea Bogazzi.
+    Date: 5-2026 */
+
+// ============================================================================
+// jttaitob_main — 68000 main CPU subsystem for the Taito B System
+// ============================================================================
+//
+// PCB ref: K1100419A / J1100178A (rastsag2/nastar/nastarw, ROM prefix b81).
+// Two crystals on the board: 24 MHz drives the 68k; 16 MHz drives the
+// Z80 and YM2610; a third 27.164 MHz crystal drives the TC0180VCU pixel
+// clock. The 68k runs at 24/2 = 12 MHz.
+//
+//   • Motorola 68000  @ 24/2 = 12 MHz   ← this module
+//   • Zilog Z80       @ 16/4 =  4 MHz   ← jttaitob_snd.v
+//   • YM2610          @ 16/2 =  8 MHz   ← jt10 inside _snd.v
+//
+// Memory map (taito_b.cpp:369 rastsag2_map):
+//
+//   0x000000-0x07FFFF  68k ROM                  → SDRAM bank 0
+//   0x200000-0x201FFF  palette RAM (4 KB)       → BRAM in this module
+//   0x400000-0x47FFFF  TC0180VCU window         → BRAM in this module
+//                      (decoded into sub-regions per tc0180vcu_memrw)
+//   0x600000-0x607FFF  68k work RAM (32 KB)     → BRAM in this module
+//   0x800000-0x800003  TC0140SYT                → jttaitob_syt.v
+//   0xA00000-0xA0000F  TC0220IOC                → jttaitob_ioc.v
+//
+// IRQ source (taito_b.cpp:1895-1896): the TC0180VCU drives two interrupts:
+//   inth_callback → 68k IRQ 4   (HOLD_LINE)
+//   intl_callback → 68k IRQ 2   (HOLD_LINE)
+// IRQ 2 just sets a flag the IRQ 4 ISR checks (taito_b.cpp:44). For
+// first-cut bring-up we drive IRQ 4 on falling-edge LVBL (start of
+// vblank) and leave IRQ 2 idle — that gets the game out of the
+// "waiting for vblank" loop. When the VCU lands properly, swap
+// these for the real chip's INTH/INTL outputs.
+//
+// Read alongside:
+//   • cores/taitob/doc/taito_b.cpp          — MAME driver snapshot
+//   • cores/taitob/doc/tc0180vcu.cpp + .h   — VCU register reference
+//   • cores/taitob/doc/taitoio.cpp          — TC0220IOC reference
+//   • cores/superman/hdl/jtsuperman_main.v  — Taito X cousin
+//   • cores/rastan/hdl/jtrastan_main.v      — canonical Taito 68k spine
+// ============================================================================
+
+module jttaitob_main(
+    input               rst,
+    input               clk,                     // 48 MHz JTFRAME_CLK48
+
+    // Video timing
+    input               LVBL,
+    input               LHBL,                    // for IRQ-2 8-line-after-vbl
+    input               dip_pause,
+
+    // Program ROM (SDRAM bank 0, "main" bus from mem.yaml)
+    output       [23:1] cpu_addr,
+    output       [18:1] main_addr,
+    output       [ 1:0] main_dsn,                // {UDSn, LDSn}
+    output       [15:0] main_dout,
+    output              main_rnw,
+    output reg          rom_cs,
+    input        [15:0] rom_data,
+    input               rom_ok,
+
+    // Video subsystem port-B reads
+    input        [11:0] pal_addr_b,
+    output       [15:0] pal_dout_b,
+    input        [14:0] vram_addr_b,
+    output       [15:0] vram_dout_b,
+    input        [12:0] oram_addr_b,             // sprite/scroll combined window
+    output       [15:0] oram_dout_b,
+    // VCU control register file — full 8×16-bit array exposed to video.v.
+    // Layout per tc0180vcu.cpp (ctrl_w decoder):
+    //   ctrl[0]  hi byte = FG rambank pair {fg_rambank[1]<<4, fg_rambank[0]}
+    //   ctrl[1]  hi byte = BG rambank pair {bg_rambank[1]<<4, bg_rambank[0]}
+    //   ctrl[2]  hi byte = FG scrolling-blocks divisor
+    //   ctrl[3]  hi byte = BG scrolling-blocks divisor
+    //   ctrl[4]  hi byte = text tile bank 0
+    //   ctrl[5]  hi byte = text tile bank 1
+    //   ctrl[6]  hi byte = text ram page
+    //   ctrl[7]  hi byte = video_control (flip / fb page / sprite priority)
+    output reg   [127:0] vcu_ctrl,                // {ctrl[7], ctrl[6], ..., ctrl[0]}
+
+    // TC0140SYT master port
+    output              syt_cs,
+    output              syt_addr,                // = A[1] (0x800001 vs 0x800003)
+    output              syt_we,
+    output       [ 3:0] syt_din,
+    input        [ 3:0] syt_dout,
+
+    // TC0220IOC bus
+    output              ioc_cs,
+    output       [ 3:0] ioc_addr,                // = A[4:1]
+    output              ioc_rnw,
+    output              ioc_lds_n,
+    output       [ 7:0] ioc_din,                 // low byte of cpu_dout
+    input        [ 7:0] ioc_dout,
+
+    input        [ 7:0] debug_bus,
+    output reg   [ 7:0] st_dout
+);
+
+`ifndef NOMAIN
+
+// ============================================================================
+// 68000 core signals
+// ============================================================================
+wire [23:1] A;
+wire        cpu_cen, cpu_cenb;
+wire        UDSn, LDSn, RnW, ASn, VPAn, DTACKn;
+wire [ 2:0] FC, IPLn;
+wire [15:0] cpu_dout;
+reg  [15:0] cpu_din;
+wire        allFC;                               // high when NOT in IACK cycle
+reg         int4n, int2n;                        // IRQ 4 + IRQ 2 latched, active LOW
+reg         LVBLl, LHBLl;                        // edge detectors
+reg  [ 3:0] lines_since_vbl;                     // 0..15, saturates at 8
+reg         intl_fired_this_vbl;                 // gate IRQ 2 to one fire per vbl
+
+assign cpu_addr  = A;
+assign main_addr = A[18:1];
+assign main_dsn  = {UDSn, LDSn};
+assign main_dout = cpu_dout;
+assign main_rnw  = RnW;
+assign allFC     = ~&FC;                         // FC==7 means IACK cycle
+
+// IPL encoding: drive the lowest active level, idle = 3'b111.
+//   IRQ 4 active, IRQ 2 idle → IPLn = ~4 = 3'b011
+//   IRQ 2 active, IRQ 4 idle → IPLn = ~2 = 3'b101
+//   both active              → 68k autoselects highest (4) → 3'b011
+// The pin polarity on the 68k is "level encoded inverted", so
+// IPLn = ~level. We compute level first then invert.
+wire [2:0] irq_level = (~int4n) ? 3'd4 :
+                       (~int2n) ? 3'd2 :
+                                  3'd0;
+assign IPLn = ~irq_level;
+
+// VPAn: autovector IACK for any IRQ. Taito B uses level 2 and level 4 —
+// both autovectored. Asserting VPAn during any IACK (FC==7, ASn low,
+// RnW high) returns the autovector to the 68k.
+assign VPAn = !(!ASn && FC==3'd7 && RnW);
+
+// ============================================================================
+// Address decoder — combinational, ASn-gated
+// ============================================================================
+//
+// rastsag2_map (taito_b.cpp:369):
+//   A[23:20] = 0x0  ROM (0x000000-0x07FFFF)
+//   A[23:20] = 0x2  palette RAM   (0x200000-0x201FFF)  - 4 KB
+//   A[23:20] = 0x4  TC0180VCU window (0x400000-0x47FFFF)
+//     A[18:16] = 0     VRAM            (0x400000-0x40FFFF)  - 64 KB
+//     A[18:16] = 1     spr/scroll/pad  (0x410000-0x413FFF)  - 16 KB
+//     A[18:15] = 0011  ctrl regs       (0x418000-0x41801F)  - 32 bytes
+//     A[18:18] = 1     framebuffer     (0x440000-0x47FFFF)  - 256 KB (HITICE)
+//   A[23:20] = 0x6  work RAM (0x600000-0x607FFF)
+//   A[23:20] = 0x8  TC0140SYT (0x800001 / 0x800003)
+//   A[23:20] = 0xA  TC0220IOC (0xA00001-0xA0000F, byte at odd addresses)
+reg         pal_cs;
+reg         vram_cs;                             // 0x400000-0x40FFFF
+reg         oram_cs;                             // 0x410000-0x413FFF (spr+scroll+pad)
+reg         vcuctrl_cs;                          // 0x418000-0x41801F
+reg         fb_cs;                               // 0x440000-0x47FFFF (framebuffer)
+reg         ram_cs;                              // 0x600000-0x607FFF
+reg         syt_cs_r;
+reg         ioc_cs_r;
+
+always @* begin
+    rom_cs     = allFC && !ASn &&  A[23:19] == 5'h00;                 // 0x000000-0x07FFFF
+    pal_cs     = allFC && !ASn &&  A[23:13] == 11'b0010_0000_000;     // 0x200000-0x201FFF
+    vram_cs    = allFC && !ASn &&  A[23:16] == 8'h40;                 // 0x400000-0x40FFFF
+    oram_cs    = allFC && !ASn &&  A[23:14] == 10'b0100_0001_00;      // 0x410000-0x413FFF
+    vcuctrl_cs = allFC && !ASn &&  A[23: 5] == 19'b0100_0001_1000_0000_000; // 0x418000-0x41801F
+    fb_cs      = allFC && !ASn &&  A[23:18] == 6'b0100_01;            // 0x440000-0x47FFFF
+    ram_cs     = allFC && !ASn &&  A[23:15] == 9'b0110_0000_0;        // 0x600000-0x607FFF
+    syt_cs_r   = allFC && !ASn &&  A[23:20] == 4'h8;                  // 0x800000
+    ioc_cs_r   = allFC && !ASn &&  A[23:20] == 4'hA;                  // 0xA00000
+end
+
+// SYT bus drive (4-bit nibble on low lane, byte at A1 selects port vs comm)
+// Taito B System maps SYT at EVEN addresses ($800000=port, $800002=comm),
+// so the 4-bit byte data lands on the UPPER data lane (UDS) — bits 11:8 of
+// cpu_dout.  (Superman's Taito X System uses ODD addresses with LDS; that
+// drove the original copy here, which was wrong for the B-System bus.)
+assign syt_cs   = syt_cs_r;
+assign syt_addr = A[1];
+assign syt_we   = syt_cs_r & ~RnW & ~UDSn;
+assign syt_din  = cpu_dout[11:8];
+
+// TC0220IOC: A[4:1] selects 1 of 16 registers, byte on high lane
+// (umask16(0xff00) in MAME → reads/writes use UDSn, data is in
+// cpu_dout[15:8] / cpu_din[15:8]).
+assign ioc_cs    = ioc_cs_r;
+assign ioc_addr  = A[4:1];
+assign ioc_rnw   = RnW;
+assign ioc_lds_n = UDSn;                         // IOC sits on UPPER byte lane
+assign ioc_din   = cpu_dout[15:8];
+
+// Byte-lane writes
+wire [1:0] cpu_we = {~UDSn, ~LDSn} & {2{~RnW}};
+
+// ============================================================================
+// VCU ctrl register file — 16 bytes at 0x418000-0x41801F
+// ============================================================================
+//
+// Full 8×16-bit register file mirroring MAME's m_ctrl[0..7].
+//
+// The chip is byte-addressable from the 68k: even addr → upper byte (UDS),
+// odd addr → lower byte (LDS). A[3:1] selects which 16-bit word (0..7).
+// Reads return the latched value; writes update the addressed byte lane.
+//
+// MAME ctrl_w decoder (tc0180vcu.cpp:223) extracts these fields:
+//   ctrl[0] high byte : FG rambank pair  -> ((>>0)&0xf)<<12 / ((>>4)&0xf)<<12
+//   ctrl[1] high byte : BG rambank pair  -> same encoding
+//   ctrl[2..3] high   : per-block scroll-divisor counts (FG, BG)
+//   ctrl[4..5] high   : text tile bank 0 / 1
+//   ctrl[6] high      : text ram page  -> ((>>0)&0xf)<<11
+//   ctrl[7] high      : video_control  (flip, fb_page, sprite priority)
+//
+// We store the full word so any future field outside the high byte is
+// available without retro-fitting the latch.
+reg [15:0] ctrl_word [0:7];
+integer i;
+always @(posedge clk, posedge rst) begin
+    if (rst) begin
+        for (i = 0; i < 8; i = i + 1) ctrl_word[i] <= 16'h0;
+    end else if (vcuctrl_cs && ~RnW) begin
+        if (~UDSn) ctrl_word[A[3:1]][15:8] <= cpu_dout[15:8];
+        if (~LDSn) ctrl_word[A[3:1]][ 7:0] <= cpu_dout[ 7:0];
+    end
+end
+
+always @* begin
+    vcu_ctrl = { ctrl_word[7], ctrl_word[6], ctrl_word[5], ctrl_word[4],
+                 ctrl_word[3], ctrl_word[2], ctrl_word[1], ctrl_word[0] };
+end
+
+// ============================================================================
+// On-chip RAMs
+// ============================================================================
+wire [15:0] ram_dout, pal_dout_a, vram_dout_a, oram_dout_a;
+
+// Work RAM — 16K words = 32 KB at 0x600000-0x607FFF
+jtframe_dual_ram16 #(.AW(14)) u_workram(
+    .clk0  ( clk          ),
+    .data0 ( cpu_dout     ),
+    .addr0 ( A[14:1]      ),
+    .we0   ( cpu_we & {2{ram_cs}} ),
+    .q0    ( ram_dout     ),
+    .clk1  ( clk          ),
+    .data1 ( 16'h0        ),
+    .addr1 ( 14'd0        ),
+    .we1   ( 2'b00        ),
+    .q1    (              )
+);
+
+// Palette RAM — 2K words = 4 KB at 0x200000-0x201FFF
+jtframe_dual_ram16 #(.AW(12)) u_pal(
+    .clk0  ( clk          ),
+    .data0 ( cpu_dout     ),
+    .addr0 ( A[12:1]      ),
+    .we0   ( cpu_we & {2{pal_cs}} ),
+    .q0    ( pal_dout_a   ),
+    .clk1  ( clk          ),
+    .data1 ( 16'h0        ),
+    .addr1 ( pal_addr_b   ),
+    .we1   ( 2'b00        ),
+    .q1    ( pal_dout_b   )
+);
+
+// VRAM — 32K words = 64 KB at 0x400000-0x40FFFF
+// Holds BG/FG tile codes+attributes; the VCU bank-switches which
+// sub-regions feed each tile plane. For first cut the 68k just reads
+// and writes the whole window linearly.
+jtframe_dual_ram16 #(.AW(15)) u_vram(
+    .clk0  ( clk          ),
+    .data0 ( cpu_dout     ),
+    .addr0 ( A[15:1]      ),
+    .we0   ( cpu_we & {2{vram_cs}} ),
+    .q0    ( vram_dout_a  ),
+    .clk1  ( clk          ),
+    .data1 ( 16'h0        ),
+    .addr1 ( vram_addr_b  ),
+    .we1   ( 2'b00        ),
+    .q1    ( vram_dout_b  )
+);
+
+// Sprite/scroll combined — 8K words = 16 KB at 0x410000-0x413FFF
+// Layout (per tc0180vcu_memrw):
+//   0x10000-0x1197F  sprite RAM (~3.2K words)
+//   0x11980-0x137FF  unused/padding
+//   0x13800-0x13FFF  scroll RAM (1K words, line-scroll for BG/FG)
+// All 68k-readable as plain word RAM; the VCU pipeline carves up the
+// regions on the display side.
+jtframe_dual_ram16 #(.AW(13)) u_oram(
+    .clk0  ( clk          ),
+    .data0 ( cpu_dout     ),
+    .addr0 ( A[13:1]      ),
+    .we0   ( cpu_we & {2{oram_cs}} ),
+    .q0    ( oram_dout_a  ),
+    .clk1  ( clk          ),
+    .data1 ( 16'h0        ),
+    .addr1 ( oram_addr_b  ),
+    .we1   ( 2'b00        ),
+    .q1    ( oram_dout_b  )
+);
+
+// Framebuffer (0x440000-0x47FFFF) is currently a black hole — the
+// rastsag2 game doesn't touch it (it's a Hitice / Realpunc feature).
+// Reads return 0, writes ignored. If a game in this family ever needs
+// it, allocate ~256 KB of BRAM or external memory here.
+/* verilator lint_off UNUSED */
+wire _unused_fb = fb_cs;
+/* verilator lint_on UNUSED */
+
+// ============================================================================
+// Read multiplexer
+// ============================================================================
+always @(posedge clk) begin
+    cpu_din <= rom_cs     ? rom_data                          :
+               ram_cs     ? ram_dout                          :
+               pal_cs     ? pal_dout_a                        :
+               vram_cs    ? vram_dout_a                       :
+               oram_cs    ? oram_dout_a                       :
+               vcuctrl_cs ? ctrl_word[A[3:1]]                 :
+               syt_cs_r   ? {4'h0, syt_dout, 8'hFF}           :   // UDS lane on even addr
+               ioc_cs_r   ? {ioc_dout, 8'hFF}                 :  // umask 0xff00
+               16'hFFFF;
+end
+
+// ============================================================================
+// IRQ generation
+// ============================================================================
+//
+// Implements MAME tc0180vcu.cpp::vblank_callback + update_intl exactly:
+//
+//   At vblank start (LVBL 1→0):
+//       INTH (= IRQ 4) asserted (HOLD_LINE).
+//       Start an 8-scanline countdown.
+//   8 scanlines later:
+//       INTH cleared, INTL (= IRQ 2) asserted.
+//   At vblank end (LVBL 0→1):
+//       INTL cleared.
+//
+// HOLD_LINE in MAME means "line stays asserted until the 68k acknowledges
+// the IACK or the chip explicitly clears it." We mirror that with VPAn-
+// gated clearing per IRQ level.
+//
+// LHBL falling edge = start of a new horizontal line (LHBL goes low during
+// HBLANK). We use that to tick the scanline counter while inside vblank.
+//
+// Without IRQ 2 the game's vblank handler runs but never completes its
+// "phase B" frame-tick — the main loop at 0x59E spins forever. Wiring
+// both IRQs is the precondition for the game to exit self-test and
+// start writing tiles into VRAM (BOOT_TRACE.md §"Pre-vector landmark").
+always @(posedge clk, posedge rst) begin
+    if (rst) begin
+        int4n               <= 1'b1;
+        int2n               <= 1'b1;
+        LVBLl               <= 1'b1;
+        LHBLl               <= 1'b1;
+        lines_since_vbl     <= 4'd0;
+        intl_fired_this_vbl <= 1'b0;
+    end else begin
+        LVBLl <= LVBL;
+        LHBLl <= LHBL;
+
+        // ── Vblank entry: assert IRQ 4, reset line counter + intl gate ──
+        if (LVBLl & ~LVBL) begin
+            int4n               <= 1'b0;
+            lines_since_vbl     <= 4'd0;
+            intl_fired_this_vbl <= 1'b0;
+        end
+
+        // ── Inside vblank: count LHBL falling edges (one per scanline) ──
+        if (~LVBL && LHBLl & ~LHBL && lines_since_vbl != 4'd15) begin
+            lines_since_vbl <= lines_since_vbl + 4'd1;
+        end
+
+        // ── 8 lines after vblank entry: clear INTH (no-op if already ack'd
+        //    via IACK), assert INTL. Fires once per vblank regardless of
+        //    whether the 68k has yet acknowledged IRQ 4. This is the MAME
+        //    timer-callback path: m_intl_timer->adjust(... +8 lines ...)
+        //    then update_intl() unconditionally toggles inth→clear and
+        //    intl→assert.
+        if (~LVBL && lines_since_vbl == 4'd8 && !intl_fired_this_vbl) begin
+            int4n               <= 1'b1;
+            int2n               <= 1'b0;
+            intl_fired_this_vbl <= 1'b1;
+        end
+
+        // ── Vblank exit: clear INTL ──
+        if (~LVBLl & LVBL) begin
+            int2n <= 1'b1;
+        end
+
+        // ── IACK clears acknowledged IRQ (HOLD_LINE semantics) ──
+        if (!VPAn) begin
+            if (irq_level == 3'd4) int4n <= 1'b1;
+            if (irq_level == 3'd2) int2n <= 1'b1;
+        end
+    end
+end
+
+// ============================================================================
+// DTACK helper — 48 MHz × 1/4 = 12 MHz (Taito B 68k clock)
+// ============================================================================
+wire bus_cs    = rom_cs;
+wire bus_busy  = rom_cs & ~rom_ok;
+wire bus_legit = 1'b0;
+
+jtframe_68kdtack_cen #(.W(8)) u_dtack(
+    .rst        ( rst       ),
+    .clk        ( clk       ),
+    .cpu_cen    ( cpu_cen   ),
+    .cpu_cenb   ( cpu_cenb  ),
+    .bus_cs     ( bus_cs    ),
+    .bus_busy   ( bus_busy  ),
+    .bus_legit  ( bus_legit ),
+    .bus_ack    ( 1'b0      ),
+    .ASn        ( ASn       ),
+    .DSn        ({UDSn,LDSn}),
+    .num        ( 7'd1      ),                   // 48 × 1/4 = 12 MHz
+    .den        ( 8'd4      ),
+    .DTACKn     ( DTACKn    ),
+    .wait2      ( 1'b0      ),
+    .wait3      ( 1'b0      ),
+    .fave       (           ),
+    .fworst     (           )
+);
+
+// ============================================================================
+// jtframe_m68k — FX68K or J68 wrapper
+// ============================================================================
+jtframe_m68k u_cpu(
+    .clk      ( clk       ),
+    .rst      ( rst       ),
+    .RESETn   (           ),
+    .cpu_cen  ( cpu_cen   ),
+    .cpu_cenb ( cpu_cenb  ),
+
+    .eab      ( A         ),
+    .iEdb     ( cpu_din   ),
+    .oEdb     ( cpu_dout  ),
+
+    .eRWn     ( RnW       ),
+    .LDSn     ( LDSn      ),
+    .UDSn     ( UDSn      ),
+    .ASn      ( ASn       ),
+    .VPAn     ( VPAn      ),
+    .FC       ( FC        ),
+
+    .BERRn    ( 1'b1      ),
+    .HALTn    ( dip_pause ),
+    .BRn      ( 1'b1      ),
+    .BGACKn   ( 1'b1      ),
+    .BGn      (           ),
+
+    .DTACKn   ( DTACKn    ),
+    .IPLn     ( IPLn      )
+);
+
+// ============================================================================
+// SIMULATION-gated PC dumper — load-bearing diagnostic per AGENTS.md §2b
+// ============================================================================
+//
+// Sample cpu_din WHILE M1 / opcode-fetch is active and rom_ok is asserted —
+// NOT on the rising edge of M1, because the bus floats to FF the instant
+// MREQ goes back high. For 68k we approximate: pick up the address each
+// time the CPU starts a bus cycle (ASn falling) in supervisor space.
+`ifdef SIMULATION
+// ── Parallel rst tracker so we can compare main vs snd module view ──
+initial $display("[INIT] jttaitob_main debug block compiled in");
+reg main_rst_d = 1'b0;
+always @(posedge clk) begin
+    main_rst_d <= rst;
+    if (main_rst_d !== rst) begin
+        $display("[%0t] MAIN rst: %b → %b  (rom_count=%0d)",
+                 $time, main_rst_d, rst, rom_count);
+    end
+end
+integer main_state_ctr = 0;
+always @(posedge clk) begin
+    main_state_ctr <= main_state_ctr + 1;
+    if ((main_state_ctr & 32'h000FFFFF) == 32'h0) begin
+        $display("[%0t] MAIN state @ctr=%0d: rst=%b  PC_addr=0x%h  rom_cs=%b",
+                 $time, main_state_ctr, rst, {1'b0, A, 1'b0}, rom_cs);
+    end
+end
+
+integer rom_count = 0;
+integer irq_count = 0;
+integer pal_count = 0;
+integer vram_count = 0;
+integer oram_count = 0;
+integer syt_count = 0;
+integer ioc_count = 0;
+integer pal_w_count = 0, vram_w_count = 0, oram_w_count = 0;
+reg ASn_d;
+always @(posedge clk) begin
+    ASn_d <= ASn;
+    if (ASn_d & ~ASn) begin
+        if (rom_cs)    rom_count  <= rom_count  + 1;
+        if (pal_cs)    pal_count  <= pal_count  + 1;
+        if (vram_cs)   vram_count <= vram_count + 1;
+        if (oram_cs)   oram_count <= oram_count + 1;
+        if (syt_cs_r)  syt_count  <= syt_count  + 1;
+        if (ioc_cs_r)  ioc_count  <= ioc_count  + 1;
+    end
+    if (!VPAn) irq_count <= irq_count + 1;
+    // Per-region write counters — only count when cpu_we actually fires
+    if (pal_cs  && |cpu_we) pal_w_count  <= pal_w_count  + 1;
+    if (vram_cs && |cpu_we) vram_w_count <= vram_w_count + 1;
+    if (oram_cs && |cpu_we) oram_w_count <= oram_w_count + 1;
+end
+
+integer prev_print = 0;
+always @(posedge clk) begin
+    if (rom_count != prev_print && (rom_count % 250000) == 0) begin
+        $display("[%0t] SIM rom=%0d  irq=%0d  pal=%0d  vram=%0d  oram=%0d  syt=%0d  ioc=%0d",
+                 $time, rom_count, irq_count,
+                 pal_count, vram_count, oram_count, syt_count, ioc_count);
+        prev_print <= rom_count;
+    end
+end
+
+// ----------------------------------------------------------------------------
+// Validation-gate landmarks — one-shot $display on first hit of each gate.
+// These match cores/taitob/doc/BOOT_TRACE.md gates 1-6 on the 68k side.
+// ----------------------------------------------------------------------------
+reg gate_seen_404, gate_seen_sp, gate_seen_vctl, gate_seen_ioc,
+    gate_seen_syt, gate_seen_ramclr;
+reg [15:0] last_ramclr_pc;
+initial begin
+    gate_seen_404    = 1'b0;
+    gate_seen_sp     = 1'b0;
+    gate_seen_vctl   = 1'b0;
+    gate_seen_ioc    = 1'b0;
+    gate_seen_syt    = 1'b0;
+    gate_seen_ramclr = 1'b0;
+    last_ramclr_pc   = 16'h0;
+end
+
+reg gate_seen_scroll;
+initial gate_seen_scroll = 1'b0;
+
+always @(posedge clk) begin
+    if (ASn_d & ~ASn) begin
+        // Gate 1 — first ROM fetch at PC=0x404 (post-reset, after the
+        // implicit move #$2700,SR at 0x400 that MAME's trace skips).
+        if (!gate_seen_404 && rom_cs && A == 23'h000202 /* PC>>1 = 0x404>>1 */) begin
+            $display("[%0t] GATE 1: PC=0x000404 reached (first user fetch)", $time);
+            gate_seen_404 <= 1'b1;
+        end
+        // Gate 3 — first VCU ctrl write
+        if (!gate_seen_vctl && vcuctrl_cs && ~RnW) begin
+            $display("[%0t] GATE 3: VCU ctrl write @ 0x%h (offs %0d) <= 0x%h",
+                     $time, {1'b0, A, 1'b0}, A[3:1], cpu_dout);
+            gate_seen_vctl <= 1'b1;
+        end
+        // Gate 4 — first scroll-RAM write (FG @ 0x413800 or BG @ 0x413C00).
+        // oram_cs covers 0x410000-0x413FFF; gate fires on A[13:11] = 7 or higher.
+        if (!gate_seen_scroll && oram_cs && ~RnW &&
+            (A[13:11] == 3'b111 /* >= 0x413800 in the oram window */)) begin
+            $display("[%0t] GATE 4: scroll RAM write @ 0x%h <= 0x%h",
+                     $time, {1'b0, A, 1'b0}, cpu_dout);
+            gate_seen_scroll <= 1'b1;
+        end
+        // Gate 5 — first IOC write
+        if (!gate_seen_ioc && ioc_cs_r && ~RnW) begin
+            $display("[%0t] GATE 5: IOC write @ 0x%h <= 0x%h", $time,
+                     {1'b0, A, 1'b0}, cpu_dout[15:8]);
+            gate_seen_ioc <= 1'b1;
+        end
+        // Gate 10 — first SYT write
+        if (!gate_seen_syt && syt_cs_r && ~RnW) begin
+            $display("[%0t] GATE 10: SYT write @ 0x%h <= 0x%h", $time,
+                     {1'b0, A, 1'b0}, cpu_dout[15:8]);
+            gate_seen_syt <= 1'b1;
+        end
+        // Gate 6 — work-RAM clear progress (poll PC after each ASn fall
+        // for the loop body 0x486-0x48A). When we *stop* hitting that
+        // range we know the loop finished.
+        if (rom_cs && (A[18:1] == 18'h243 /* 0x486>>1 */)) begin
+            last_ramclr_pc <= 16'h0486;
+        end
+        if (!gate_seen_ramclr && last_ramclr_pc == 16'h0486 &&
+            rom_cs && A[18:1] > 18'h245 /* PC > 0x48A: loop exited */) begin
+            $display("[%0t] GATE 6: work-RAM clear loop exited (next PC > 0x48A)",
+                     $time);
+            gate_seen_ramclr <= 1'b1;
+        end
+    end
+end
+
+// ----------------------------------------------------------------------------
+// Live PC sampler — log every Nth ROM access AFTER gate 6 so we can see
+// where the CPU is heading (helps diagnose stalls between gates).
+// ----------------------------------------------------------------------------
+integer post_clear_sample = 0;
+reg seen_verify_loop = 1'b0;
+reg seen_verify_exit = 1'b0;
+integer verify_iter = 0;
+always @(posedge clk) begin
+    if (gate_seen_ramclr && ASn_d & ~ASn && rom_cs) begin
+        post_clear_sample <= post_clear_sample + 1;
+        // Print first hit outside the verify-loop body (PC<0x500 or PC>0x50E).
+        // This tells us when the verify loop terminates.
+        if (A[18:1] == 18'h281 /* 0x502 */) seen_verify_loop <= 1'b1;
+        if (!seen_verify_exit && seen_verify_loop &&
+            (A[18:1] >= 18'h288 /* 0x510 */)) begin
+            $display("[%0t] VERIFY: loop exited, next PC=0x%h after %0d iters",
+                     $time, {1'b0, A, 1'b0}, verify_iter);
+            seen_verify_exit <= 1'b1;
+        end
+        // Count loop iterations (one per cmp.b at 0x502 entry)
+        if (A[18:1] == 18'h281) verify_iter <= verify_iter + 1;
+        // Print every 50000th ROM access — keeps log small but visible.
+        // Include running PAL/VRAM counts so we can see if the game is
+        // still drawing or just spinning on a non-existent condition.
+        if ((post_clear_sample % 200000) == 0) begin
+            $display("[%0t] sample=%0d PC=0x%h pal=%0d vram=%0d (p0=%0d p1=%0d p2=%0d p3=%0d) oram=%0d",
+                     $time, post_clear_sample, {1'b0, A, 1'b0},
+                     pal_count, vram_count,
+                     vram_page_writes[0], vram_page_writes[1],
+                     vram_page_writes[2], vram_page_writes[3],
+                     oram_count);
+        end
+    end
+end
+
+// One-shot critical-path markers
+reg pc_960_seen, pc_2c9c_seen, pc_2d44_seen, pc_2d56_seen, pc_c0c_seen;
+initial begin
+    pc_960_seen  = 1'b0; pc_2c9c_seen = 1'b0; pc_2d44_seen = 1'b0;
+    pc_2d56_seen = 1'b0; pc_c0c_seen  = 1'b0;
+end
+always @(posedge clk) begin
+    if (ASn_d & ~ASn && rom_cs) begin
+        if (!pc_960_seen  && A == 23'h0004B0 /* 0x960>>1 */) begin
+            $display("[%0t] PC=0x960  (release-Z80-reset chain entry!)", $time);
+            pc_960_seen <= 1'b1;
+        end
+        if (!pc_2c9c_seen && A == 23'h00164E /* 0x2C9C>>1 */) begin
+            $display("[%0t] PC=0x2C9C (calls 2D44 release reset)", $time);
+            pc_2c9c_seen <= 1'b1;
+        end
+        if (!pc_2d44_seen && A == 23'h0016A2 /* 0x2D44>>1 */) begin
+            $display("[%0t] PC=0x2D44 (RELEASE Z80 RESET)", $time);
+            pc_2d44_seen <= 1'b1;
+        end
+        if (!pc_2d56_seen && A == 23'h0016AB /* 0x2D56>>1 */) begin
+            $display("[%0t] PC=0x2D56 (ASSERT Z80 RESET — early boot)", $time);
+            pc_2d56_seen <= 1'b1;
+        end
+        if (!pc_c0c_seen && A == 23'h000606 /* 0xC0C>>1 */) begin
+            $display("[%0t] PC=0xC0C  (checksum-fail bra.)", $time);
+            pc_c0c_seen <= 1'b1;
+        end
+    end
+end
+
+// One-shot IRQ entry markers — track when each handler first runs.
+// IRQ 4 vector handler lives at 0x5C0; IRQ 2 vector handler at 0x5A4
+// (from the ROM image at offset 0x68/0x70).
+reg irq4_entered, irq2_entered;
+integer irq4_hits = 0, irq2_hits = 0;
+initial begin irq4_entered = 1'b0; irq2_entered = 1'b0; end
+always @(posedge clk) begin
+    if (ASn_d & ~ASn && rom_cs) begin
+        if (A == 23'h0002E0 /* 0x5C0 >> 1 */) irq4_hits <= irq4_hits + 1;
+        if (A == 23'h0002D2 /* 0x5A4 >> 1 */) irq2_hits <= irq2_hits + 1;
+        if (!irq4_entered && A == 23'h0002E0) begin
+            $display("[%0t] IRQ4 vector reached at PC=0x5C0 (sample=%0d)",
+                     $time, post_clear_sample);
+            irq4_entered <= 1'b1;
+        end
+        if (!irq2_entered && A == 23'h0002D2) begin
+            $display("[%0t] IRQ2 vector reached at PC=0x5A4 (sample=%0d)",
+                     $time, post_clear_sample);
+            irq2_entered <= 1'b1;
+        end
+    end
+end
+
+// First VRAM / palette / sprite-RAM write — proves the game has started
+// drawing. These should fire after IRQ 2 is running properly.
+reg first_pal_seen, first_vram_seen, first_oram_seen;
+// Per-VRAM-page write counters (each page = 0x1000 words).
+// Page 0 = FG codes, page 1 = FG attrs, page 2 = BG codes, page 3 = BG attrs
+// (with nastar's ctrl[0]=0x10, ctrl[1]=0x32 config).
+integer vram_page_writes [0:7];
+integer pi;
+initial begin
+    first_pal_seen  = 1'b0;
+    first_vram_seen = 1'b0;
+    first_oram_seen = 1'b0;
+    for (pi = 0; pi < 8; pi = pi + 1) vram_page_writes[pi] = 0;
+end
+always @(posedge clk) begin
+    if (ASn_d & ~ASn) begin
+        if (!first_pal_seen && pal_cs && ~RnW) begin
+            $display("[%0t] FIRST PAL write @ 0x%h <= 0x%h (sample=%0d)",
+                     $time, {1'b0, A, 1'b0}, cpu_dout, post_clear_sample);
+            first_pal_seen <= 1'b1;
+        end
+        if (!first_vram_seen && vram_cs && ~RnW) begin
+            $display("[%0t] FIRST VRAM write @ 0x%h <= 0x%h (sample=%0d)",
+                     $time, {1'b0, A, 1'b0}, cpu_dout, post_clear_sample);
+            first_vram_seen <= 1'b1;
+        end
+        // Track VRAM writes per 4 KB page (A[15:13] selects page 0..7)
+        if (vram_cs && ~RnW) begin
+            vram_page_writes[A[15:13]] <= vram_page_writes[A[15:13]] + 1;
+        end
+        if (!first_oram_seen && oram_cs && ~RnW) begin
+            $display("[%0t] FIRST OBJ write @ 0x%h <= 0x%h (sample=%0d)",
+                     $time, {1'b0, A, 1'b0}, cpu_dout, post_clear_sample);
+            first_oram_seen <= 1'b1;
+        end
+    end
+end
+
+// End-of-sim summary + BRAM dump (Superman pattern, adapted).
+// Shadow arrays are mirrored to every CPU write so $writememh produces
+// a complete contents dump at sim end — usable for scene-replay later.
+reg [15:0] dbg_pal  [0:4095];      //  8 KB palette  ($200000-$201FFF)
+reg [15:0] dbg_vram [0:32767];     // 64 KB VRAM     ($400000-$40FFFF)
+reg [15:0] dbg_oram [0:8191];      // 16 KB OBJ/scr  ($410000-$413FFF)
+integer si;
+initial begin
+    for (si = 0; si <  4096; si = si + 1) dbg_pal[si]  = 16'h0;
+    for (si = 0; si < 32768; si = si + 1) dbg_vram[si] = 16'h0;
+    for (si = 0; si <  8192; si = si + 1) dbg_oram[si] = 16'h0;
+end
+// Mirror writes using the same gate as the real BRAM (cpu_we, which
+// requires UDS/LDS to be asserted — meaning data is valid). For byte
+// writes we preserve the un-written lane from the previous shadow value.
+reg first_vw_logged = 1'b0;
+
+// IRQ assertion counters (separate from handler-entry counters above)
+integer int4_assert_count = 0, int2_assert_count = 0, vbl_entry_count = 0;
+reg int4n_prev = 1'b1, int2n_prev = 1'b1;
+always @(posedge clk) begin
+    int4n_prev <= int4n;
+    int2n_prev <= int2n;
+    if (int4n_prev & ~int4n) int4_assert_count <= int4_assert_count + 1;
+    if (int2n_prev & ~int2n) int2_assert_count <= int2_assert_count + 1;
+    if (LVBLl & ~LVBL)       vbl_entry_count   <= vbl_entry_count   + 1;
+end
+always @(posedge clk) begin
+    if (pal_cs  && |cpu_we) begin
+        if (cpu_we[0]) dbg_pal [A[12:1]][ 7:0] <= cpu_dout[ 7:0];
+        if (cpu_we[1]) dbg_pal [A[12:1]][15:8] <= cpu_dout[15:8];
+    end
+    if (vram_cs && |cpu_we) begin
+        if (cpu_we[0]) dbg_vram[A[15:1]][ 7:0] <= cpu_dout[ 7:0];
+        if (cpu_we[1]) dbg_vram[A[15:1]][15:8] <= cpu_dout[15:8];
+        if (!first_vw_logged) begin
+            $display("[%0t] FIRST_VW: A=0x%h cpu_we=%b cpu_dout=0x%h",
+                     $time, {1'b0, A, 1'b0}, cpu_we, cpu_dout);
+            first_vw_logged <= 1'b1;
+        end
+    end
+    if (oram_cs && |cpu_we) begin
+        if (cpu_we[0]) dbg_oram[A[13:1]][ 7:0] <= cpu_dout[ 7:0];
+        if (cpu_we[1]) dbg_oram[A[13:1]][15:8] <= cpu_dout[15:8];
+    end
+end
+
+// Periodic BRAM dump — verilator's `final` block isn't reliably called
+// when -video N terminates the sim, so we trigger writememh after the
+// game has clearly passed self-test (IRQ 2 has been acked AND enough
+// palette writes have accumulated to imply real-content drawing).
+reg dump_done = 1'b0;
+always @(posedge clk) begin
+    if (!dump_done && irq2_hits > 250) begin
+        $display("[%0t] DUMP: pal=%0d vram=%0d oram=%0d irq4=%0d irq2=%0d palW=%0d vramW=%0d oramW=%0d vbl=%0d int4!=%0d int2!=%0d",
+                 $time, pal_count, vram_count, oram_count, irq4_hits, irq2_hits,
+                 pal_w_count, vram_w_count, oram_w_count,
+                 vbl_entry_count, int4_assert_count, int2_assert_count);
+        $writememh("sim_pal.hex",  dbg_pal);
+        $writememh("sim_vram.hex", dbg_vram);
+        $writememh("sim_oram.hex", dbg_oram);
+        dump_done <= 1'b1;
+    end
+end
+`endif
+
+// Debug status byte — exposed up to game.v
+always @(posedge clk) begin
+    case (debug_bus[2:0])
+        3'd0: st_dout <= {int4n, int2n, 1'b0, 1'b0, ctrl_word[7][11:8]};
+        3'd1: st_dout <= ioc_dout;
+        3'd2: st_dout <= {4'h0, syt_dout};
+        default: st_dout <= 8'hFF;
+    endcase
+end
+
+`else  // NOMAIN — scene replay
+
+// ============================================================================
+// Scene replay: the 68k/sound side is stubbed and the video pipeline is fed
+// from BRAMs preloaded with a MAME-captured scene.  See
+//   cores/taitob/ver/rastan2/mame_scripts/dump_burst.lua  (capture)
+//   cores/taitob/ver/game/rest2bin.sh                     (split dump.bin)
+// jtsim's `-s <scene>` flag splits dump.bin into pal.bin / vram.bin /
+// oram.bin / ctrl.hex in the working dir, which the loaders below pick up.
+// ============================================================================
+
+// Bus tie-offs for the stubbed CPU side.
+assign cpu_addr  = 23'd0;
+assign main_addr = 18'd0;
+assign main_dsn  = 2'b11;
+assign main_dout = 16'h0;
+assign main_rnw  = 1'b1;
+assign syt_cs    = 1'b0;
+assign syt_addr  = 1'b0;
+assign syt_we    = 1'b0;
+assign syt_din   = 4'h0;
+assign ioc_cs    = 1'b0;
+assign ioc_addr  = 4'd0;
+assign ioc_rnw   = 1'b1;
+assign ioc_lds_n = 1'b1;
+assign ioc_din   = 8'h0;
+initial begin
+    rom_cs  = 1'b0;
+    st_dout = 8'h0;
+end
+
+// VCU ctrl[0..7] restored from the scene (ctrl.hex = 8 big-endian 16-bit
+// words emitted by rest2bin.sh). Drives vcu_ctrl exactly like the live
+// branch builds it from ctrl_word[].
+reg [15:0] scene_ctrl [0:7];
+integer sci;
+initial begin
+    for (sci = 0; sci < 8; sci = sci + 1) scene_ctrl[sci] = 16'h0;
+    $readmemh("ctrl.hex", scene_ctrl);
+end
+always @* begin
+    vcu_ctrl = { scene_ctrl[7], scene_ctrl[6], scene_ctrl[5], scene_ctrl[4],
+                 scene_ctrl[3], scene_ctrl[2], scene_ctrl[1], scene_ctrl[0] };
+end
+
+// Scene palette / VRAM / OBJ-scroll RAMs — read-only, port-B to video.v.
+// ENDIAN=1 matches MAME's big-endian 68k byte stream (even=hi, odd=lo).
+jtframe_dual_ram16 #(.AW(12), .ENDIAN(1), .SIMFILE("pal.bin")) u_pal_sim(
+    .clk0  ( clk          ),
+    .data0 ( 16'h0        ),
+    .addr0 ( 12'd0        ),
+    .we0   ( 2'b00        ),
+    .q0    (              ),
+    .clk1  ( clk          ),
+    .data1 ( 16'h0        ),
+    .addr1 ( pal_addr_b   ),
+    .we1   ( 2'b00        ),
+    .q1    ( pal_dout_b   )
+);
+
+jtframe_dual_ram16 #(.AW(15), .ENDIAN(1), .SIMFILE("vram.bin")) u_vram_sim(
+    .clk0  ( clk          ),
+    .data0 ( 16'h0        ),
+    .addr0 ( 15'd0        ),
+    .we0   ( 2'b00        ),
+    .q0    (              ),
+    .clk1  ( clk          ),
+    .data1 ( 16'h0        ),
+    .addr1 ( vram_addr_b  ),
+    .we1   ( 2'b00        ),
+    .q1    ( vram_dout_b  )
+);
+
+jtframe_dual_ram16 #(.AW(13), .ENDIAN(1), .SIMFILE("oram.bin")) u_oram_sim(
+    .clk0  ( clk          ),
+    .data0 ( 16'h0        ),
+    .addr0 ( 13'd0        ),
+    .we0   ( 2'b00        ),
+    .q0    (              ),
+    .clk1  ( clk          ),
+    .data1 ( 16'h0        ),
+    .addr1 ( oram_addr_b  ),
+    .we1   ( 2'b00        ),
+    .q1    ( oram_dout_b  )
+);
+
+`endif
+
+endmodule
diff --git a/cores/taitob/hdl/jttaitob_obj.v b/cores/taitob/hdl/jttaitob_obj.v
new file mode 100644
index 000000000..aca1234e7
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_obj.v
@@ -0,0 +1,216 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Andrea Bogazzi.
+    Date: 5-2026 */
+
+// ============================================================================
+// jttaitob_obj — TC0180VCU sprite engine
+// ============================================================================
+// Phase 3d-a.1: real 16x16 gfx (unscaled, single-tile — big-sprite zoom are
+// 3d-b/c).  Per scanline the scanner walks the 408-slot sprite list; for each
+// slot covering the next line it reads code/color/x, fetches the tile's gfx
+// row from the obj bus (gsort'd, like BG/FG), decodes 16 pens (flipX/flipY)
+// and writes them into a jtframe_obj_buffer (ping-pong line buffer).  Pen 0 is
+// transparent (the buffer's ALPHA=0 skips it).
+//
+// Sprite slot (8 words, oram word offs = slot*8; scanned reverse hi->lo):
+//   +0 code[14:0]
+//   +1 color[5:0]  flipx[14]  flipy[15]
+//   +2 x  [9:0] signed (>=0x200 -> -0x400)
+//   +3 y  [9:0] signed
+//   +4 zoom  (3d-c)    +5 big (3d-b)
+//
+// oram + obj reads have 1-clk latency → address issued one state before use.
+// Line buffer filled during line N active for line N+1 (vrender), read on
+// line N+1 after jtframe_obj_buffer swaps at LHBL.
+// ============================================================================
+
+module jttaitob_obj(
+    input               rst,
+    input               clk,
+    input               pxl_cen,
+    input               LHBL,
+    input               LVBL,
+    input        [ 8:0] hdump,
+    input        [ 8:0] vrender,        // line being prepared (= vdump+1)
+
+    // sprite RAM read (oram) — arbitrated against the scroll FSM in video.v
+    output reg   [12:0] sc_addr,
+    output reg          sc_cs,
+    input        [15:0] sc_data,
+
+    // gfx ROM read (obj bus) — arbitrated against the FG fill in video.v
+    output reg   [18:0] gfx_addr,
+    output reg          gfx_cs,
+    input        [15:0] gfx_data,
+    input               gfx_ok,
+
+    // pixel output to the priority mux
+    output       [11:0] obj_pixel,
+    output              obj_visible
+);
+
+localparam [12:0] OBJ_TOP = 13'h0CB8;   // (0x1980-16)/2 — highest slot word offs
+
+localparam [3:0] IDLE=0, WAITY=1, GETY=2, WAITK=3, GETK=4, WAITC=5, GETC=6,
+                 WAITX=7, GETX=8, G0=9, G1=10, G2=11, G3=12, DRAW=13, NEXT=14;
+
+// gfx_sort swap (matches video.v / mem.yaml gfx_sort=hvvvx): the gfx region
+// is byte-reordered, so every gfx address is remapped {A[18:4],A[2:0],A[3]}.
+function [18:0] gsort; input [18:0] a; gsort = {a[18:4], a[2:0], a[3]}; endfunction
+
+// One 4bpp pen of a 16x16 tile row (same plane/byte order as the tile planes).
+function [3:0] obj_pen;
+    input [ 3:0] p;
+    input [15:0] w01l, w23l, w01r, w23r;
+    reg   [ 3:0] b;
+    reg   [15:0] w01, w23;
+    begin
+        b   = {1'b0, ~p[2:0]};
+        w01 = p[3] ? w01r : w01l;
+        w23 = p[3] ? w23r : w23l;
+        obj_pen = { w01[b], w01[b+4'd8], w23[b], w23[b+4'd8] };
+    end
+endfunction
+
+reg  [12:0] offs;
+reg  [ 3:0] st;
+reg  [13:0] spr_code;
+reg  [11:0] spr_pal;                    // color*16 (palette base)
+reg  [ 9:0] spr_x;
+reg         flipx, flipy;
+reg  [ 3:0] row_e;                      // tile row 0..15 (flipY applied)
+reg  [15:0] w01l, w23l, w01r, w23r;
+reg  [ 3:0] wcnt;
+reg         lhbl_d;
+reg         we;
+reg  [ 8:0] waddr;
+reg  [11:0] wdata;
+
+wire        line_start = ~lhbl_d & LHBL;
+
+// Coverage of the prepared line: vrender in [y, y+16).  y is 10-bit signed.
+wire signed [11:0] vren_s = $signed({3'b0, vrender});
+wire signed [11:0] y_now  = $signed({{2{sc_data[9]}}, sc_data[9:0]});
+wire               covered = (vren_s >= y_now) && (vren_s < (y_now + 12'sd16));
+wire        [ 3:0] row_now = (vren_s - y_now);        // 0..15 within the tile
+
+// gfx row addresses for the captured code + row (left/right 8px halves)
+wire [18:0] fw01l = gsort({spr_code[13:0], row_e[3], 1'b0, row_e[2:0]});
+wire [18:0] fw01r = gsort({spr_code[13:0], row_e[3], 1'b1, row_e[2:0]});
+wire [18:0] fw23l = fw01l + 19'h40000;
+wire [18:0] fw23r = fw01r + 19'h40000;
+
+// pixel index within the tile for the current write column (flipX)
+wire [ 3:0] pidx = flipx ? (4'd15 - wcnt) : wcnt;
+wire [ 3:0] pen  = obj_pen(pidx, w01l, w23l, w01r, w23r);
+
+always @(posedge clk) begin
+    if (rst) begin
+        st <= IDLE; offs <= 13'd0; sc_cs <= 1'b0; sc_addr <= 13'd0;
+        gfx_cs <= 1'b0; gfx_addr <= 19'd0; we <= 1'b0; wcnt <= 4'd0;
+        spr_code <= 14'd0; spr_pal <= 12'd0; spr_x <= 10'd0;
+        flipx <= 1'b0; flipy <= 1'b0; row_e <= 4'd0;
+        w01l <= 16'd0; w23l <= 16'd0; w01r <= 16'd0; w23r <= 16'd0; lhbl_d <= 1'b0;
+    end else begin
+        lhbl_d <= LHBL;
+        we     <= 1'b0;
+        case (st)
+        IDLE: begin
+            sc_cs <= 1'b0; gfx_cs <= 1'b0;
+            if (line_start && LVBL) begin
+                offs    <= OBJ_TOP;
+                sc_addr <= OBJ_TOP + 13'd3;          // issue y
+                sc_cs   <= 1'b1;
+                st      <= WAITY;
+            end
+        end
+        WAITY: st <= GETY;
+        GETY:  begin                                 // y valid
+            if (covered) begin
+                row_e   <= row_now;                  // flipY applied after color read
+                sc_addr <= offs + 13'd0;             // issue code
+                st <= WAITK;
+            end else st <= NEXT;
+        end
+        WAITK: st <= GETK;
+        GETK:  begin                                 // code valid
+            spr_code <= sc_data[13:0];
+            sc_addr  <= offs + 13'd1;                // issue color
+            st <= WAITC;
+        end
+        WAITC: st <= GETC;
+        GETC:  begin                                 // color valid
+            spr_pal <= {2'b01, sc_data[5:0], 4'b0};  // fb_color_base 0x400 + color*16
+            flipx   <= sc_data[14];
+            flipy   <= sc_data[15];
+            if (sc_data[15]) row_e <= ~row_e;        // flipY
+            sc_addr <= offs + 13'd2;                 // issue x
+            st <= WAITX;
+        end
+        WAITX: st <= GETX;
+        GETX:  begin                                 // x valid
+            spr_x   <= sc_data[9:0];
+            gfx_cs  <= 1'b1;
+            gfx_addr<= fw01l;                        // issue gfx w01l
+            st <= G0;
+        end
+        G0: if (gfx_ok) begin w01l <= gfx_data; gfx_addr <= fw23l; st <= G1; end
+        G1: if (gfx_ok) begin w23l <= gfx_data; gfx_addr <= fw01r; st <= G2; end
+        G2: if (gfx_ok) begin w01r <= gfx_data; gfx_addr <= fw23r; st <= G3; end
+        G3: if (gfx_ok) begin                        // gfx_data = w23r now
+            w23r <= gfx_data;                        // latch right-half planes 2/3
+            gfx_cs <= 1'b0; wcnt <= 4'd0; st <= DRAW;
+        end
+        DRAW: begin                                  // write 16 pens (pen 0 transparent)
+            we    <= 1'b1;
+            waddr <= spr_x[8:0] + {5'b0, wcnt};
+            wdata <= spr_pal | {8'h0, pen};
+            wcnt  <= wcnt + 4'd1;
+            if (wcnt == 4'd15) st <= NEXT;
+        end
+        NEXT: begin
+            if (offs == 13'd0) begin
+                sc_cs <= 1'b0; st <= IDLE;
+            end else begin
+                offs    <= offs - 13'd8;
+                sc_addr <= (offs - 13'd8) + 13'd3;   // issue next y
+                st <= WAITY;
+            end
+        end
+        default: st <= IDLE;
+        endcase
+    end
+end
+
+jtframe_obj_buffer #(.DW(12), .AW(9), .ALPHAW(4), .ALPHA(0), .BLANK(0)) u_line(
+    .clk     ( clk        ),
+    .LHBL    ( LHBL       ),
+    .flip    ( 1'b0       ),
+    .wr_data ( wdata      ),
+    .wr_addr ( waddr      ),
+    .we      ( we         ),
+    .rd_addr ( rd_addr    ),
+    .rd      ( pxl_cen    ),
+    .rd_data ( obj_pixel  )
+);
+
+// jtframe_obj_buffer registers rd_data on pxl_cen (1px latency, same as the
+// BG/FG/TX rings) — read one column ahead so sprites line up with the planes.
+wire [8:0] rd_addr = hdump + 9'd1;
+
+assign obj_visible = |obj_pixel;
+
+endmodule
diff --git a/cores/taitob/hdl/jttaitob_shifter.v b/cores/taitob/hdl/jttaitob_shifter.v
new file mode 100644
index 000000000..a0c6e7384
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_shifter.v
@@ -0,0 +1,88 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Andrea Bogazzi.
+    Date: 5-2026 */
+
+// ============================================================================
+// jttaitob_shifter — tile-row ring buffer with a fine-scroll read tap
+// ============================================================================
+//
+// Architecture borrowed from the Taito F2 TC0100SCN MiSTer core
+// (Arcade-TaitoF2_MiSTer/rtl/tc0100scn.sv :: tc0100scn_shifter).  The
+// TC0180VCU is a *different* chip, so only the rendering *technique* is
+// reused — register/VRAM semantics stay TC0180VCU-specific.
+//
+// A small ring of LEN tile-rows is filled tile-by-tile AHEAD of the beam by
+// the caller's prefetch FSM.  Read-out is a single `tap`:
+//   tap_index = tap[hi]  → which buffered tile
+//   tap_pixel = tap[lo]  → pixel within that tile (fine-scroll granularity)
+// Because the ring holds several consecutive tiles, the tap walks across
+// tile boundaries seamlessly, so arbitrary (sub-tile) horizontal scroll and
+// per-row scroll are handled for free — no per-screen-slice straddle.
+//
+// flipX is applied at LOAD (the caller passes load_flip); the tap always
+// reads left→right.  Pixels are 4bpp; load_pix holds TW pixels with pixel 0
+// in bits [3:0].  Each tile also carries a 12-bit palette base (color_base
+// already folded in by the caller); the tapped pen is OR-combined with it
+// downstream by the colour mux.
+// ============================================================================
+
+module jttaitob_shifter #(
+    parameter TW  = 16,                       // tile width in pixels (16 BG/FG, 8 TX)
+    parameter LEN = 4                         // ring depth in tiles
+)(
+    input                                   clk,
+    input                                   ce,
+
+    // Load port (prefetch FSM)
+    input                                   load,
+    input  [$clog2(LEN)-1:0]                load_index,
+    input  [11:0]                           load_pal,
+    input  [TW*4-1:0]                        load_pix,    // pixel 0 in [3:0]
+    input                                   load_flip,   // 1 = reverse pixel order
+
+    // Read tap (= screen_x - scroll), low bits select the sub-tile pixel
+    input  [$clog2(LEN)+$clog2(TW)-1:0]     tap,
+    output reg [11:0]                       pal_out,
+    output reg [ 3:0]                       pen_out
+);
+
+localparam IB = $clog2(LEN);
+localparam PB = $clog2(TW);
+
+reg [11:0]      pal_buf [0:LEN-1];
+reg [TW*4-1:0]  pix_buf [0:LEN-1];
+
+wire [IB-1:0] tap_index = tap[IB+PB-1:PB];
+wire [PB-1:0] tap_pixel = tap[PB-1:0];
+
+integer i;
+always @(posedge clk) begin
+    if (load) begin
+        pal_buf[load_index] <= load_pal;
+        if (load_flip) begin
+            for (i = 0; i < TW; i = i + 1)
+                pix_buf[load_index][4*((TW-1)-i) +: 4] <= load_pix[4*i +: 4];
+        end else begin
+            pix_buf[load_index] <= load_pix;
+        end
+    end
+    if (ce) begin
+        pal_out <= pal_buf[tap_index];
+        pen_out <= pix_buf[tap_index][4*tap_pixel +: 4];
+    end
+end
+
+endmodule
diff --git a/cores/taitob/hdl/jttaitob_snd.v b/cores/taitob/hdl/jttaitob_snd.v
new file mode 100644
index 000000000..c226b1be8
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_snd.v
@@ -0,0 +1,273 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    Author: Andrea Bogazzi.
+    Date: 5-2026 */
+
+// ============================================================================
+// jttaitob_snd — Z80 + YM2610 sound subsystem for Taito B System
+// ============================================================================
+//
+// Topology is identical to the Taito X System (Superman) — Z80 @ 4 MHz,
+// YM2610 @ 8 MHz, TC0140SYT handles the Z80 memory decode and chip
+// selects. ROM bank window at 0x4000-0x7FFF, RAM at 0xC000-0xDFFF,
+// YM at 0xE000-0xE0FF, SYT at 0xE200-0xE2FF, bank reg at 0xF200.
+//
+// Difference vs Superman:
+//   • Rastan Saga 2 has ADPCM-B samples (B81-01.1, 512 KB) wired into
+//     the YM2610 Delta-T port. They live in SDRAM bank 3 (`adpcmb` bus,
+//     JTFRAME_BA3_START) and feed the jt10 adpcmb_data input — Superman
+//     had no ADPCM-B region so it left that port at 0.
+//
+// Read alongside cores/superman/hdl/jtsuperman_snd.v — same shape.
+// ============================================================================
+
+module jttaitob_snd(
+    input               rst,
+    input               clk,                     // 48 MHz JTFRAME_CLK48
+    input               cen_z80,                 // 4 MHz Z80 cen
+    input               cen_ym,                  // 8 MHz YM2610 cen
+
+    // TC0140SYT slave-side connections (chip selects emitted by SYT)
+    input               snd_rom_cs,
+    input        [ 1:0] snd_rom_a16,
+    input               snd_ram_cs,
+    input               snd_ym_cs,
+    input               snd_syt_sel,
+    input               snd_rst_soft,
+    input               snd_nmi_n,
+    input        [ 7:0] syt_dout_z80,
+
+    // Z80 bus exposed back to SYT
+    output       [15:0] z80_addr,
+    output       [ 7:0] z80_dout,
+    output              z80_mreq_n,
+    output              z80_rd_n,
+    output              z80_wr_n,
+
+    // Z80 sound ROM (SDRAM `snd` bus, 64 KB)
+    output       [15:0] rom_addr,
+    output reg          rom_cs,
+    input        [ 7:0] rom_data,
+    input               rom_ok,
+
+    // YM2610 ADPCM-A (SDRAM `adpcma` bus, 512 KB)
+    output       [18:0] adpcma_addr,
+    output              adpcma_cs,
+    input        [ 7:0] adpcma_data,
+    input               adpcma_ok,
+
+    // YM2610 ADPCM-B / Delta-T (SDRAM `adpcmb` bus, 512 KB)
+    output       [18:0] adpcmb_addr,
+    output              adpcmb_cs,
+    input        [ 7:0] adpcmb_data,
+    input               adpcmb_ok,
+
+    // Audio output
+    output signed [15:0] fm_l,
+    output signed [15:0] fm_r,
+
+    input        [ 7:0] debug_bus,
+    output       [ 7:0] st_dout
+);
+
+`ifndef NOSOUND
+
+wire        z80_int_n;
+wire        z80_m1_n, z80_iorq_n, z80_rfsh_n;
+wire [ 7:0] z80_din;
+wire        z80_cpu_cen;
+
+wire [ 7:0] ym_dout;
+wire [19:0] ym_adpcma_addr;
+wire [ 3:0] ym_adpcma_bank;     // jt10's external port is 4 bits; the
+                                // upstream WIDTHEXPAND warning inside
+                                // jt10.v is a jt10-internal issue
+                                // (same warning in Superman/etc.).
+wire        ym_adpcma_roe_n;
+wire [23:0] ym_adpcmb_addr;
+wire        ym_adpcmb_roe_n;
+
+wire [ 7:0] sram_dout;
+wire        snd_rstn = ~rst & ~snd_rst_soft;
+
+// ─── Z80 ROM address mapping (banked window @ 0x4000-0x7FFF) ──────────────
+wire in_bank = z80_addr[15:14] == 2'b01;
+assign rom_addr = in_bank
+    ? {snd_rom_a16, z80_addr[13:0]}
+    : {2'b00,       z80_addr[13:0]};
+always @(posedge clk) rom_cs <= snd_rom_cs;
+
+// ─── ADPCM-A address mapping ──────────────────────────────────────────────
+assign adpcma_addr = ym_adpcma_addr[18:0];
+assign adpcma_cs   = ~ym_adpcma_roe_n;
+
+// ─── ADPCM-B (Delta-T) address mapping ────────────────────────────────────
+assign adpcmb_addr = ym_adpcmb_addr[18:0];
+assign adpcmb_cs   = ~ym_adpcmb_roe_n;
+
+// ─── Z80 data mux ─────────────────────────────────────────────────────────
+assign z80_din = snd_rom_cs  ? rom_data            :
+                 snd_ram_cs  ? sram_dout           :
+                 snd_ym_cs   ? ym_dout             :
+                 snd_syt_sel ? syt_dout_z80        :
+                 8'hFF;
+
+// Suppress lint warning on currently-unused inputs (kept for future use).
+// ym_adpcmb_addr is 24-bit; only [18:0] address the 512 KB region, so the
+// top bits [23:19] are intentionally unused.
+/* verilator lint_off UNUSED */
+wire _unused_z80 = z80_iorq_n | z80_rfsh_n | z80_cpu_cen | adpcma_ok | adpcmb_ok |
+                   |ym_adpcma_bank | |ym_adpcmb_addr[23:19] | |debug_bus;
+/* verilator lint_on UNUSED */
+
+// ─── SIM Z80 PC tracker — first-hit log at key boot landmarks ─────────────
+`ifdef SIMULATION
+reg [10:0] z80_pc_seen = 11'd0;
+wire z80_m1_active = ~z80_m1_n & ~z80_mreq_n;
+// Z80 activity counter — fires for ANY M1 fetch. If this stays 0,
+// the Z80 isn't executing at all (held in reset, halted, etc.).
+integer z80_m1_total = 0;
+reg z80_first_logged = 1'b0;
+// Log EVERY M1 fetch for the first 200 cycles after Z80 released.
+// Include rom_cs / rom_ok so we can see if Z80 is stalled in WAIT
+// (rom_ok never asserts → Z80 keeps re-trying same fetch).
+integer z80_m1_log_count = 0;
+always @(posedge clk) if (snd_rstn && z80_m1_active && z80_m1_log_count < 200) begin
+    z80_m1_log_count <= z80_m1_log_count + 1;
+    $display("[%0t] Z80 M1#%0d: PC=0x%h nmi_n=%b int_n=%b rom_cs=%b rom_ok=%b rom_data=0x%02x snd_rom_cs=%b",
+             $time, z80_m1_log_count, z80_addr, snd_nmi_n, z80_int_n,
+             rom_cs, rom_ok, rom_data, snd_rom_cs);
+end
+// Track snd_rstn transitions (initialized to avoid X-prop issues)
+reg snd_rstn_d = 1'b0;
+always @(posedge clk) begin
+    snd_rstn_d <= snd_rstn;
+    if (snd_rstn_d !== snd_rstn) begin
+        $display("[%0t] Z80 reset_n: %b → %b (rst=%b snd_rst_soft=%b)",
+                 $time, snd_rstn_d, snd_rstn, rst, snd_rst_soft);
+    end
+end
+// Periodic state dump (every 1M clk after release)
+integer rstn_print_ctr = 0;
+initial $display("[INIT] jttaitob_snd debug block compiled in");
+always @(posedge clk) begin
+    rstn_print_ctr <= rstn_print_ctr + 1;
+    if ((rstn_print_ctr & 32'h000FFFFF) == 32'h0) begin
+        $display("[%0t] Z80 state @ctr=%0d: snd_rstn=%b rst=%b snd_rst_soft=%b z80_addr=0x%h",
+                 $time, rstn_print_ctr, snd_rstn, rst, snd_rst_soft, z80_addr);
+    end
+end
+always @(posedge clk) if (z80_m1_active) begin
+    z80_m1_total <= z80_m1_total + 1;
+    if (!z80_first_logged) begin
+        $display("[%0t] Z80 FIRST M1 fetch — Z80 IS ALIVE  addr=0x%h",
+                 $time, z80_addr);
+        z80_first_logged <= 1'b1;
+    end
+end
+always @(posedge clk) if (snd_rstn && z80_m1_active) begin
+    case (z80_addr)
+        16'h0000: if (!z80_pc_seen[ 0]) begin z80_pc_seen[ 0] <= 1; $display("[%0t] Z80 PC=0000  (boot entry: DI)",            $time); end
+        16'h0001: if (!z80_pc_seen[ 1]) begin z80_pc_seen[ 1] <= 1; $display("[%0t] Z80 PC=0001  (IM 1)",                       $time); end
+        16'h0003: if (!z80_pc_seen[ 2]) begin z80_pc_seen[ 2] <= 1; $display("[%0t] Z80 PC=0003  (LD A,#$05)",                  $time); end
+        16'h0005: if (!z80_pc_seen[ 3]) begin z80_pc_seen[ 3] <= 1; $display("[%0t] Z80 PC=0005  (LD (E200),A — port_w #5)",   $time); end
+        16'h0008: if (!z80_pc_seen[ 4]) begin z80_pc_seen[ 4] <= 1; $display("[%0t] Z80 PC=0008  (LD (E201),A — comm_w #5)",   $time); end
+        16'h000B: if (!z80_pc_seen[ 5]) begin z80_pc_seen[ 5] <= 1; $display("[%0t] Z80 PC=000B  (JP $01AA)",                   $time); end
+        16'h01AA: if (!z80_pc_seen[ 6]) begin z80_pc_seen[ 6] <= 1; $display("[%0t] Z80 PC=01AA  (main init)",                  $time); end
+        16'h01B5: if (!z80_pc_seen[ 7]) begin z80_pc_seen[ 7] <= 1; $display("[%0t] Z80 PC=01B5  (LD SP,$E000)",                $time); end
+        16'h01C4: if (!z80_pc_seen[ 8]) begin z80_pc_seen[ 8] <= 1; $display("[%0t] Z80 PC=01C4  (post-RAM-clear)",             $time); end
+        16'h02D6: if (!z80_pc_seen[ 9]) begin z80_pc_seen[ 9] <= 1; $display("[%0t] Z80 PC=02D6  (NMI ENABLE point #1)",        $time); end
+        16'h04CE: if (!z80_pc_seen[10]) begin z80_pc_seen[10] <= 1; $display("[%0t] Z80 PC=04CE  (NMI ENABLE point #2)",        $time); end
+        default: ;
+    endcase
+end
+`endif
+
+// ─── jtframe_sysz80 (Z80 @ 4 MHz, internal 8 KB RAM) ──────────────────────
+jtframe_sysz80 #(.RECOVERY(0), .RAM_AW(13)) u_z80(
+    .rst_n      ( snd_rstn      ),
+    .clk        ( clk           ),
+    .cen        ( cen_z80       ),
+    .cpu_cen    ( z80_cpu_cen   ),
+    .int_n      ( z80_int_n     ),
+    .nmi_n      ( snd_nmi_n     ),
+    .busrq_n    ( 1'b1          ),
+    .m1_n       ( z80_m1_n      ),
+    .mreq_n     ( z80_mreq_n    ),
+    .iorq_n     ( z80_iorq_n    ),
+    .rd_n       ( z80_rd_n      ),
+    .wr_n       ( z80_wr_n      ),
+    .rfsh_n     ( z80_rfsh_n    ),
+    .halt_n     (               ),
+    .busak_n    (               ),
+    .A          ( z80_addr      ),
+    .cpu_din    ( z80_din       ),
+    .cpu_dout   ( z80_dout      ),
+    .ram_dout   ( sram_dout     ),
+    .ram_cs     ( snd_ram_cs    ),
+    .rom_cs     ( snd_rom_cs    ),
+    .rom_ok     ( rom_ok        )
+);
+
+// ─── YM2610 (jt10) ────────────────────────────────────────────────────────
+jt10 u_jt10(
+    .rst            ( ~snd_rstn         ),
+    .clk            ( clk               ),
+    .cen            ( cen_ym            ),
+    .din            ( z80_dout          ),
+    .addr           ( z80_addr[1:0]     ),
+    .cs_n           ( ~snd_ym_cs        ),
+    .wr_n           ( z80_wr_n          ),
+
+    .dout           ( ym_dout           ),
+    .irq_n          ( z80_int_n         ),
+
+    .adpcma_addr    ( ym_adpcma_addr    ),
+    .adpcma_bank    ( ym_adpcma_bank    ),
+    .adpcma_roe_n   ( ym_adpcma_roe_n   ),
+    .adpcma_data    ( adpcma_data       ),
+    // ADPCM-B (Delta-T) — reads b81-01.1 from SDRAM bank 3 (`adpcmb`).
+    .adpcmb_addr    ( ym_adpcmb_addr    ),
+    .adpcmb_roe_n   ( ym_adpcmb_roe_n   ),
+    .adpcmb_data    ( adpcmb_data       ),
+
+    .psg_A          (                   ),
+    .psg_B          (                   ),
+    .psg_C          (                   ),
+    .fm_snd         (                   ),
+    .psg_snd        (                   ),
+    .snd_right      ( fm_r              ),
+    .snd_left       ( fm_l              ),
+    .snd_sample     (                   ),
+    .ch_enable      ( 6'b111111         )
+);
+
+assign st_dout = { 6'd0, snd_ram_cs, snd_rom_cs };
+
+`else  // NOSOUND
+assign z80_addr   = 16'h0;
+assign z80_dout   = 8'h0;
+assign z80_mreq_n = 1'b1;
+assign z80_rd_n   = 1'b1;
+assign z80_wr_n   = 1'b1;
+assign rom_addr   = 16'h0;
+assign adpcma_addr= 19'h0;
+assign adpcma_cs  = 1'b0;
+assign adpcmb_addr= 19'h0;
+assign adpcmb_cs  = 1'b0;
+assign fm_l       = 16'h0;
+assign fm_r       = 16'h0;
+assign st_dout    = 8'h0;
+initial rom_cs    = 1'b0;
+`endif
+
+endmodule
diff --git a/cores/taitob/hdl/jttaitob_syt.v b/cores/taitob/hdl/jttaitob_syt.v
new file mode 100644
index 000000000..ae46565fc
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_syt.v
@@ -0,0 +1,350 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Date: 5-2026
+
+    Reference for protocol semantics:
+      - MAME taito/taitosnd.cpp  (mirrored in cores/taitob/doc/)
+      - Arcade-TaitoF2_MiSTer rtl/tc0140syt.sv (read-only reference).
+        Written fresh here; no verbatim copy of GPLv2 code into this
+        GPLv3 file.
+
+    Ported into the taitob core verbatim from
+    cores/superman/hdl/jtsuperman_syt.v (Andrea Bogazzi, 5-2026).
+    The TC0140SYT silicon is identical between the Taito X System
+    (Superman) and the Taito B System (Rastan Saga 2 / Nastar) —
+    same chip mask, same protocol, same Z80 memory decoder.
+*/
+
+// Taito TC0140SYT — sound communication chip between 68000 main CPU and
+// Z80 sound CPU. The real silicon also owns the Z80 memory decoder
+// (ROM/RAM/YM CS signals) and a 3-bit ROM bank register written at 0xF200.
+//
+// Master (68k) side is 4-bit data, register-port at A0=0, data-port at A0=1.
+// Slave  (Z80) side is 8-bit data, memory-mapped at 0xE200-0xE201
+// (register-port at A0=0, data-port at A0=1) and 0xF200 (bank register).
+//
+// Index semantics — verified against MAME src/mame/shared/taitosnd.cpp:
+//
+//   MASTER (68k) side (master_port_w sets mainmode; only 0..4 valid):
+//     idx 0..3 : nibbles of slave_data (master->slave) word.
+//                comm_w at idx 1 sets status[0] = PORT01_FULL (NMI source).
+//                comm_w at idx 3 sets status[1] = PORT23_FULL (NMI source).
+//                comm_r at idx 1 clears status[2] = PORT01_FULL_MASTER.
+//                comm_r at idx 3 clears status[3] = PORT23_FULL_MASTER.
+//     idx 4    : comm_w drives slave (Z80) reset:
+//                  hi-lo transition releases Z80. data!=0 asserts reset,
+//                  data==0 clears it. comm_r returns the 4-bit status:
+//                    bit 0 PORT01_FULL        (slave rx pending — NMI src)
+//                    bit 1 PORT23_FULL        (slave rx pending — NMI src)
+//                    bit 2 PORT01_FULL_MASTER (master rx pending)
+//                    bit 3 PORT23_FULL_MASTER (master rx pending)
+//
+//   SLAVE  (Z80) side (slave_port_w sets submode; only 0..6 valid):
+//     idx 0..3 : nibbles of master_data (slave->master) word.
+//                comm_w at idx 1 sets status[2] = PORT01_FULL_MASTER.
+//                comm_w at idx 3 sets status[3] = PORT23_FULL_MASTER.
+//                comm_r at idx 1 clears status[0] = PORT01_FULL.
+//                comm_r at idx 3 clears status[1] = PORT23_FULL.
+//     idx 4    : status read on comm_r (same 4 bits as master idx 4 read).
+//                comm_w at idx 4 is a NOP in MAME.
+//     idx 5    : comm_w disables NMI.
+//     idx 6    : comm_w enables  NMI.
+//
+// NMI to Z80 is asserted iff nmi_enabled && (status[1:0] != 0).
+
+module jttaitob_syt(
+    input               rst,
+    input               clk,
+
+    // 68k master interface — main CPU sound port (e.g. 0x800000-0x800003)
+    input               main_cs,      // decoded externally
+    input               main_addr,    // 68k A1 (selects register vs data port)
+    input         [3:0] main_dout,    // low nibble of main data bus
+    output        [3:0] main_din,
+    input               main_we,      // active high: 68k is writing
+
+    // Z80 slave interface — full Z80 address space (chip owns the decode)
+    input        [15:0] snd_addr,
+    input         [7:0] snd_dout,
+    output        [7:0] snd_din,      // 4 nibbles + status in low bits, hi=0
+    input               snd_mreq_n,
+    input               snd_rd_n,
+    input               snd_wr_n,
+
+    // Z80 memory decode (real chip emits these)
+    output              snd_rom_cs,   // 0x0000-0x7FFF, banked at 0x4000+
+    output reg    [1:0] snd_rom_a16,  // extra ROM address bits when in bank window
+    output              snd_ram_cs,   // 0xC000-0xDFFF
+    output              snd_ym_cs,    // 0xE000-0xE0FF (-> YM2610)
+    output              snd_syt_sel,  // exposed for debug / external bus mux
+
+    // Slave control
+    output              snd_rst,      // software reset (idx 7 write)
+    output              snd_nmi_n     // NMI to Z80 (active low)
+);
+
+    // ----------------------------------------------------------------
+    // Z80 memory decoder — replicated from the real chip
+    // ----------------------------------------------------------------
+    wire       in_bank   = snd_addr[15:14] == 2'b01;        // 0x4000-0x7FFF
+    wire       in_lowrom = snd_addr[15]    == 1'b0;         // 0x0000-0x7FFF
+    wire       in_ram    = snd_addr[15:13] == 3'b110;       // 0xC000-0xDFFF
+    wire       in_ym     = snd_addr[15:8]  == 8'hE0;        // 0xE000-0xE0FF
+    wire       in_self   = snd_addr[15:8]  == 8'hE2;        // 0xE200-0xE2FF
+    wire       in_bankw  = snd_addr[15:8]  == 8'hF2;        // 0xF200 bank reg
+
+    // TC0140SYT is purely memory-mapped, so only MREQ matters.
+    wire       z80_mem    = ~snd_mreq_n;
+    // z80_rd was declared for symmetry but no state changes on read;
+    // dropped to silence Quartus warning 10036.
+    wire       z80_wr     = z80_mem & ~snd_wr_n;
+
+    assign snd_rom_cs = z80_mem & in_lowrom;
+    assign snd_ram_cs = z80_mem & in_ram;
+    assign snd_ym_cs  = z80_mem & in_ym;
+    assign snd_syt_sel = z80_mem & in_self;
+
+    // ----------------------------------------------------------------
+    // ROM bank register at 0xF200 (write any value, low 3 bits matter)
+    //   bit[2]: when set, the 0x4000-0x7FFF window selects the ROM region
+    //           beyond 32KB (vs reading the static low half)
+    //   bit[1:0]: A14/A15 of the external ROM during the banked window
+    // ----------------------------------------------------------------
+    reg  [2:0] rom_bank;
+    always @(posedge clk) begin
+        if (rst) begin
+            rom_bank    <= 3'd0;
+            snd_rom_a16 <= 2'd0;
+        end else begin
+            if (z80_wr & in_bankw)
+                rom_bank <= snd_dout[2:0];
+            // Drive A14/A15 only when reading the banked window
+            snd_rom_a16 <= in_bank ? rom_bank[1:0] : 2'b00;
+        end
+    end
+
+    // ----------------------------------------------------------------
+    // Shared state — two 16-bit data words + 4-bit status + control flags
+    // ----------------------------------------------------------------
+    reg [15:0] master_data;  // slave -> master  (read by 68k, written by Z80)
+    reg [15:0] slave_data;   // master -> slave  (written by 68k, read by Z80)
+    reg [ 3:0] master_idx;   // 68k-side auto-incrementing index pointer
+    reg [ 3:0] slave_idx;    // Z80-side auto-incrementing index pointer
+    reg [ 3:0] status_reg;
+    reg        nmi_en;
+    reg        reset_reg;    // captured at idx 7 write
+
+    assign snd_rst   = reset_reg;
+    // NMI to Z80 asserts when nmi_en is set AND any slave-rx-pending bit
+    // is set in status (bit 0 = PORT01_FULL, bit 1 = PORT23_FULL).
+    // MAME's update_nmi() uses the same predicate.
+    assign snd_nmi_n = ~(nmi_en & (status_reg[0] | status_reg[1]));
+
+    // Data outputs — COMBINATIONAL so the 68k / Z80 see the correct
+    // nibble DURING their read cycle.  Earlier (registered) version
+    // updated on the falling edge of *_cs, by which point the CPU had
+    // already sampled the bus → reads consistently returned the
+    // previous bus cycle's value.  This is the rastan pattern
+    // (cores/rastan/hdl/jtrastan_pc060.v: `main_din = main_ptr[2] ? status : main_ram`).
+    assign main_din = (master_idx == 4'd0) ? master_data[ 3: 0] :
+                      (master_idx == 4'd1) ? master_data[ 7: 4] :
+                      (master_idx == 4'd2) ? master_data[11: 8] :
+                      (master_idx == 4'd3) ? master_data[15:12] :
+                      (master_idx == 4'd4) ? status_reg          :
+                                             4'h0;
+    assign snd_din  = (slave_idx == 4'd0) ? {4'h0, slave_data[ 3: 0]} :
+                      (slave_idx == 4'd1) ? {4'h0, slave_data[ 7: 4]} :
+                      (slave_idx == 4'd2) ? {4'h0, slave_data[11: 8]} :
+                      (slave_idx == 4'd3) ? {4'h0, slave_data[15:12]} :
+                      (slave_idx == 4'd4) ? {4'h0, status_reg}         :
+                                            8'h00;
+
+    // Edge detection — FALLING edge on both sides, modelled after Jose's
+    // jtrastan_pc060_unit (cores/rastan/hdl/jtrastan_pc060.v lines 170-198).
+    // We act when the bus cycle ENDS: all of we, addr, data are guaranteed
+    // stable by then.  Detecting on the rising edge of the chip-select
+    // is unsafe because:
+    //   * 68k bus: ASn (→ main_cs) goes low in S2 but LDSn (gating
+    //     main_we) doesn't go low until S4.  Sampling at the rising
+    //     main_cs edge sees main_we==0 on a real write → the code
+    //     takes the read branch and fires a phantom master_comm_r
+    //     that auto-increments master_idx and clears status_reg[2]
+    //     right after the Z80 has set it.
+    //   * Z80 bus: MREQ (→ snd_syt_sel) goes low in T1 but WR doesn't
+    //     go low until T2.  Same problem in reverse — slave writes can
+    //     be missed entirely because snd_wr_n is still high at the
+    //     rising slave-select edge.
+    // Latching we/addr/data inside the chip-select-high window and
+    // acting on the falling edge sidesteps both races.
+    reg main_cs_d, snd_syt_sel_d;
+    reg main_we_d, main_addr_d;
+    reg [3:0] main_dout_d;
+    reg snd_wr_n_d, snd_rd_n_d, snd_addr0_d;
+    reg [7:0] snd_dout_d;
+
+    wire main_edge  =  ~main_cs    &  main_cs_d;       // 68k bus cycle ENDING
+    wire slave_edge =  ~snd_syt_sel & snd_syt_sel_d;   // Z80 bus cycle ENDING
+
+    always @(posedge clk) begin
+        main_cs_d     <= main_cs;
+        snd_syt_sel_d <= snd_syt_sel;
+        // Latch the bus-side inputs while the cycle is in progress so
+        // they're stable at the falling edge.
+        if (main_cs) begin
+            main_we_d   <= main_we;
+            main_addr_d <= main_addr;
+            main_dout_d <= main_dout;
+        end
+        if (snd_syt_sel) begin
+            snd_wr_n_d  <= snd_wr_n;
+            snd_rd_n_d  <= snd_rd_n;
+            snd_addr0_d <= snd_addr[0];
+            snd_dout_d  <= snd_dout;
+        end
+    end
+
+    // ----------------------------------------------------------------
+    // Unified state-update block — single driver for every reg.
+    // 68k master events take priority over Z80 slave events on the same
+    // cycle (in practice they never collide because edge detection makes
+    // each one a one-cycle pulse, but priority is defined explicitly).
+    //
+    // Master (68k) side: main_addr=0 selects index port, =1 selects data.
+    // Slave  (Z80) side: snd_addr[0]=0 selects index port, =1 selects data.
+    // ----------------------------------------------------------------
+    always @(posedge clk) begin
+        if (rst) begin
+            master_idx  <= 4'd0;
+            slave_idx   <= 4'd0;
+            master_data <= 16'h0;
+            slave_data  <= 16'h0;
+            status_reg  <= 4'h0;
+            nmi_en      <= 1'b0;
+            reset_reg   <= 1'b0;
+            // main_din / snd_din are now combinational — no reset needed.
+        end else begin
+            // ---- 68k master access ----
+            // Acts on falling main_cs edge using the latched main_we_d /
+            // main_addr_d / main_dout_d snapshots so the 68k's LDSn vs ASn
+            // timing skew can't fire a phantom read in the address-setup
+            // phase of a write.
+            if (main_edge) begin
+                if (main_we_d) begin
+                    if (!main_addr_d) begin
+                        master_idx <= main_dout_d;            // load pointer
+`ifdef SIMULATION
+                        $display("[%0t] MASTER PORT_W data=%01x  master_idx<=%0d",
+                                 $time, main_dout_d, main_dout_d);
+`endif
+                    end else begin
+                        case (master_idx)
+                            4'd0: begin slave_data[3:0]   <= main_dout_d; master_idx <= master_idx + 4'd1; end
+                            4'd1: begin slave_data[7:4]   <= main_dout_d; master_idx <= master_idx + 4'd1;
+                                        status_reg[0] <= 1'b1;            end
+                            4'd2: begin slave_data[11:8]  <= main_dout_d; master_idx <= master_idx + 4'd1; end
+                            4'd3: begin slave_data[15:12] <= main_dout_d; master_idx <= master_idx + 4'd1;
+                                        status_reg[1] <= 1'b1;            end
+                            // Slave (Z80) reset — hi-lo transition releases.
+                            // MAME: m_reset_cb(data ? ASSERT_LINE : CLEAR_LINE).
+                            // Index does NOT auto-increment on this access.
+                            4'd4: begin
+                                reset_reg <= (main_dout_d != 4'd0);
+`ifdef SIMULATION
+                                $display("[%0t] SYT reset_cb: data=%01x → reset_reg=%b",
+                                         $time, main_dout_d, (main_dout_d != 4'd0));
+`endif
+                            end
+                            default: ;
+                        endcase
+`ifdef SIMULATION
+                        $display("[%0t] MASTER COMM_W mainmode=%0d data=%01x",
+                                 $time, master_idx, main_dout_d);
+`endif
+                    end
+                end else if (main_addr_d) begin
+                    // Data output is COMBINATIONAL (see main_din assign
+                    // below) so the 68k sees the right nibble DURING
+                    // the read cycle.  Here we only update the side
+                    // effects of the read: pointer advance + status
+                    // clears, latched on the falling main_cs edge.
+                    case (master_idx)
+                        4'd0: master_idx <= master_idx + 4'd1;
+                        4'd1: begin master_idx <= master_idx + 4'd1;
+                                    status_reg[2] <= 1'b0;          end
+                        4'd2: master_idx <= master_idx + 4'd1;
+                        4'd3: begin master_idx <= master_idx + 4'd1;
+                                    status_reg[3] <= 1'b0;          end
+                        default: ;  // idx 4 + others: no auto-increment
+                    endcase
+`ifdef SIMULATION
+                    $display("[%0t] MASTER COMM_R  mainmode=%0d  master_data=%04x  status=%01x  -> data=%01x",
+                             $time, master_idx, master_data, status_reg,
+                             (master_idx==4'd0) ? master_data[3:0] :
+                             (master_idx==4'd1) ? master_data[7:4] :
+                             (master_idx==4'd2) ? master_data[11:8] :
+                             (master_idx==4'd3) ? master_data[15:12] :
+                             (master_idx==4'd4) ? status_reg : 4'h0);
+`endif
+                end
+            end
+
+            // ---- Z80 slave access ----
+            // Falling-edge + latched snapshots, same rationale as the 68k
+            // side: Z80 MREQ goes low before WR, so detecting on the
+            // rising chip-select edge can miss the write entirely.
+            if (slave_edge) begin
+                if (~snd_wr_n_d) begin
+                    if (snd_addr0_d == 1'b0) begin
+                        slave_idx <= snd_dout_d[3:0];
+`ifdef SIMULATION
+                        $display("[%0t] SLAVE PORT_W  data=%02x  submode<=%0d", $time, snd_dout_d, snd_dout_d[3:0]);
+`endif
+                    end else begin
+                        case (slave_idx)
+                            4'd0: begin master_data[3:0]   <= snd_dout_d[3:0]; slave_idx <= slave_idx + 4'd1; end
+                            4'd1: begin master_data[7:4]   <= snd_dout_d[3:0]; slave_idx <= slave_idx + 4'd1;
+                                        status_reg[2] <= 1'b1;                 end
+                            4'd2: begin master_data[11:8]  <= snd_dout_d[3:0]; slave_idx <= slave_idx + 4'd1; end
+                            4'd3: begin master_data[15:12] <= snd_dout_d[3:0]; slave_idx <= slave_idx + 4'd1;
+                                        status_reg[3] <= 1'b1;                 end
+                            4'd5: nmi_en <= 1'b0;
+                            4'd6: nmi_en <= 1'b1;
+                            default: ;
+                        endcase
+`ifdef SIMULATION
+                        $display("[%0t] SLAVE COMM_W  submode=%0d  data=%02x", $time, slave_idx, snd_dout_d);
+`endif
+                    end
+                end
+                if (~snd_rd_n_d && snd_addr0_d == 1'b1) begin
+                    // Same fix as master side: snd_din is COMBINATIONAL,
+                    // we only update side effects (pointer + status
+                    // clears) here.
+                    case (slave_idx)
+                        4'd0: slave_idx <= slave_idx + 4'd1;
+                        4'd1: begin slave_idx <= slave_idx + 4'd1;
+                                    status_reg[0] <= 1'b0;                end
+                        4'd2: slave_idx <= slave_idx + 4'd1;
+                        4'd3: begin slave_idx <= slave_idx + 4'd1;
+                                    status_reg[1] <= 1'b0;                end
+                        default: ;
+                    endcase
+                end
+            end
+        end
+    end
+
+endmodule
diff --git a/cores/taitob/hdl/jttaitob_video.v b/cores/taitob/hdl/jttaitob_video.v
new file mode 100644
index 000000000..2b2fc651f
--- /dev/null
+++ b/cores/taitob/hdl/jttaitob_video.v
@@ -0,0 +1,694 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    Author: Andrea Bogazzi.
+    Date: 5-2026 */
+
+// ============================================================================
+// jttaitob_video — TC0180VCU pipeline (Phase 3b: BG + FG + TX planes)
+// ============================================================================
+//
+// Three tile planes share the same gfx ROM (SDRAM bank 2, 1 MB):
+//
+//   BG : 64x64 of 16x16 tiles, opaque,        color_base 0xC0, ctrl[1] banks
+//   FG : 64x64 of 16x16 tiles, transparent pen 0, color_base 0x80, ctrl[0]
+//   TX : 64x32 of 8x8  tiles,  transparent pen 0, color_base 0x00,
+//        bank from ctrl[6] high byte, tile-code high bits from ctrl[4]/[5]
+//
+// VRAM port-B is time-shared with an 8-phase counter (3-bit) covering the
+// five fetches each cycle:
+//
+//   0 → BG code addr        4 → TX code addr
+//   1 → BG attr addr        5 → idle (slot for sprite list reads in 3d)
+//   2 → FG code addr        6 → idle
+//   3 → FG attr addr        7 → idle
+//
+// Each phase needs 1 clk of BRAM latency, so capture lands on phase+1.
+//
+// SDRAM bank-2 buses:
+//   bg  → BG plane gfx fetches
+//   obj → FG plane gfx fetches (sprites take this in Phase 3d)
+//   tx  → text plane gfx fetches
+//
+// Three independent slice-fetch FSMs run in parallel, each with its own
+// double-buffer (fetch/render).  At each slice boundary all three buffers
+// snap atomically.
+//
+// Pixel priority (Phase 3b, fixed): TX > FG > BG.  No sprites yet, no
+// per-frame priority mode (ctrl[7] bit 3) — Phase 4 wires that.
+//
+// Tile addressing math:
+//
+//   BG/FG (16x16, chartsize 64*8 bits per ROM half):
+//     byte_offset = {y[3], x[3], y[2:0], 1'b0}
+//     word_addr_01 = {tile_code[13:0], y[3], x[3], y[2:0]}
+//     word_addr_23 = word_addr_01 + 0x40000
+//     bit_idx within byte = x[2:0]
+//
+//   TX (8x8, chartsize 16*8 bits per ROM half):
+//     byte_offset = 2 * y
+//     word_addr_01 = {tile_code[11:0], y[2:0]}    (15 bits)
+//     word_addr_23 = word_addr_01 + 0x40000
+//     bit_idx within byte = x[2:0]
+//
+// Text tile word layout (read from VRAM at {tx_bank, text_idx}):
+//   bits[10:0]  = tile-code low
+//   bit [11]    = selects high-bank: 0 → ctrl[4], 1 → ctrl[5]
+//   bits[15:12] = palette base offset (added to color_base 0x00)
+// Effective tile-code for Nastar's 1 MB TC0180VCU ROM region is
+// {high_bank[3:0], tile[10:0]} = 15 bits total.  MAME exposes a wider
+// generic bank field because other Taito B sets ship larger gfx regions,
+// but this core currently wires a 1 MB bank-2 ROM and must preserve the
+// full 15-bit character index within that space.
+//
+// ============================================================================
+
+module jttaitob_video(
+    input               rst,
+    input               clk,
+    input               pxl_cen,
+
+    input               LHBL,
+    input               LVBL,
+    input        [ 8:0] vdump,
+    input        [ 8:0] vrender,                 // = vdump+1; BG line-buffer fills this line during HBLANK
+    input        [ 8:0] hdump,
+
+    input        [127:0] vcu_ctrl,
+
+    // VRAM port-B (shared between BG, FG, TX via 8-phase)
+    output reg   [15:0] vram_addr_b,
+    input        [15:0] vram_dout_b,
+
+    // Sprite/scroll RAM port-B (Phase 3c: scroll reads at vblank,
+    // Phase 3d: sprite-list reads during HBLANK)
+    output reg   [12:0] oram_addr_b,
+    input        [15:0] oram_dout_b,
+
+    // SDRAM bank-2 buses
+    output reg   [18:0] bg_addr,
+    output reg          bg_cs,
+    input        [15:0] bg_data,
+    input               bg_ok,
+    output reg   [18:0] obj_addr,
+    output reg          obj_cs,
+    input        [15:0] obj_data,
+    input               obj_ok,
+    output reg   [18:0] tx_addr,
+    output reg          tx_cs,
+    input        [15:0] tx_data,
+    input               tx_ok,
+    // SDRAM bank-3 bus — FG plane's dedicated gfx copy (interleaves with BG)
+    output reg   [18:0] fg_addr,
+    output reg          fg_cs,
+    input        [15:0] fg_data,
+    input               fg_ok,
+
+    output reg   [11:0] pal_idx
+);
+
+// ─── Unpack ctrl registers ─────────────────────────────────────────────────
+wire [15:0] ctrl0 = vcu_ctrl[ 15:  0];           // FG bank pair
+wire [15:0] ctrl1 = vcu_ctrl[ 31: 16];           // BG bank pair
+wire [15:0] ctrl4 = vcu_ctrl[ 79: 64];           // TX tile bank 0
+wire [15:0] ctrl5 = vcu_ctrl[ 95: 80];           // TX tile bank 1
+wire [15:0] ctrl6 = vcu_ctrl[111: 96];           // TX ram page
+wire [15:0] ctrl7 = vcu_ctrl[127:112];           // video_control
+
+wire [ 3:0] bg_bank_codes = ctrl1[11: 8];
+wire [ 3:0] bg_bank_attrs = ctrl1[15:12];
+wire [ 3:0] fg_bank_codes = ctrl0[11: 8];
+wire [ 3:0] fg_bank_attrs = ctrl0[15:12];
+wire [ 3:0] tx_ram_bank   = ctrl6[11: 8];
+wire [ 5:0] tx_high_bank0 = ctrl4[13: 8];        // raw generic TC0180VCU bank field
+wire [ 5:0] tx_high_bank1 = ctrl5[13: 8];
+
+// ─── ctrl[7] video_control decode (Phase 4) ───────────────────────────────
+//
+// Per tc0180vcu.cpp::video_control comments at line 195:
+//   bit 0 = don't erase sprite framebuffer "after the beam"
+//   bit 3 = sprite-to-foreground priority
+//             1 = bg, fg, obj, tx
+//             0 = bg, obj1, fg, obj0, tx  (obj selected by tile-color bit 0)
+//   bit 4 = screen flip (active HI)
+//   bit 5 = global video enable (Hit-the-Ice toggles this around vram clears)
+//   bit 6 = framebuffer page to show when bit 7 set
+//   bit 7 = don't flip framebuffer every vblank
+//
+// All operate on the HIGH byte of ctrl[7] (the 68k writes them as byte
+// stores to even addresses).
+wire        vc_sprite_pri    = ctrl7[11];        // bit 3
+wire        vc_screen_flip   = ctrl7[12];        // bit 4
+wire        vc_video_enable  = ctrl7[13];        // bit 5
+
+/* verilator lint_off UNUSED */
+wire _unused_video = rst | |ctrl0[7:0] | |ctrl1[7:0] | |ctrl4[7:0] |
+                     |ctrl5[7:0] | |ctrl6[7:0] |
+                     ctrl7[8] | ctrl7[9] | ctrl7[10] |
+                     ctrl7[14] | ctrl7[15] | |ctrl7[7:0] |
+                     vc_sprite_pri | vc_screen_flip;
+/* verilator lint_on UNUSED */
+
+// ─── Scroll RAM read FSM (Phase 3c) ────────────────────────────────────────
+//
+// At each LVBL falling edge (vblank start) we burst-read 4 words from
+// oram-side scroll RAM and latch them:
+//
+//   oram word 0x1C00 (= byte 0x413800) → fg_scrollx
+//   oram word 0x1C01                    → fg_scrolly
+//   oram word 0x1E00 (= byte 0x413C00) → bg_scrollx
+//   oram word 0x1E01                    → bg_scrolly
+//
+// This implements the lines_per_block = 256 case (ctrl[2] = ctrl[3] = 0,
+// which is exactly what nastar writes at boot).  Per-line scrolling
+// (lines_per_block < 256) would require re-reading scrollram during
+// the visible scan — Phase 3c+ enhancement.
+//
+// Each scroll word is treated as signed; the bottom bits wrap naturally
+// over the 64-tile (1024 px) plane.
+
+reg [15:0] bg_scrollx, bg_scrolly, fg_scrollx, fg_scrolly;
+reg [ 2:0] scroll_fsm;                            // 0=idle, 1..4 = reading
+reg [12:0] scr_oram_addr;                         // scroll FSM's oram address
+reg        LVBL_d;
+
+always @(posedge clk) begin
+    if (rst) begin
+        bg_scrollx <= 16'h0; bg_scrolly <= 16'h0;
+        fg_scrollx <= 16'h0; fg_scrolly <= 16'h0;
+        scroll_fsm <= 3'd0;
+        scr_oram_addr <= 13'd0;
+        LVBL_d     <= 1'b1;
+    end else begin
+        LVBL_d <= LVBL;
+        // Fix 6: the oram BRAM has a 1-clk read latency (q1 at clk T+1 =
+        // mem[addr1 at clk T]).  The old FSM latched each scroll value in
+        // the same state it set the address, so it read one address too
+        // early — fg_scrollx in particular latched the uninitialised
+        // pre-sequence bus value and scrolled FG off-screen into empty
+        // tilemap (FG rendered tile 0 everywhere = invisible).  Add one
+        // wait state so each value is latched the cycle AFTER its address
+        // has settled on the BRAM output.
+        case (scroll_fsm)
+            3'd0: begin
+                scr_oram_addr <= 13'd0;
+                // Trigger on vblank entry (LVBL high→low transition)
+                if (LVBL_d & ~LVBL) begin
+                    scr_oram_addr <= 13'h1C00;     // request FG scrollx
+                    scroll_fsm  <= 3'd1;
+                end
+            end
+            3'd1: begin                          // FG scrollx in flight; queue FG scrolly
+                scr_oram_addr <= 13'h1C01;
+                scroll_fsm  <= 3'd2;
+            end
+            3'd2: begin                          // latch FG scrollx (= mem[0x1C00])
+                fg_scrollx  <= oram_dout_b;
+                scr_oram_addr <= 13'h1E00;
+                scroll_fsm  <= 3'd3;
+            end
+            3'd3: begin                          // latch FG scrolly (= mem[0x1C01])
+                fg_scrolly  <= oram_dout_b;
+                scr_oram_addr <= 13'h1E01;
+                scroll_fsm  <= 3'd4;
+            end
+            3'd4: begin                          // latch BG scrollx (= mem[0x1E00])
+                bg_scrollx  <= oram_dout_b;
+                scr_oram_addr <= 13'd0;
+                scroll_fsm  <= 3'd5;
+            end
+            3'd5: begin                          // latch BG scrolly (= mem[0x1E01])
+                bg_scrolly  <= oram_dout_b;
+                scr_oram_addr <= 13'd0;
+                scroll_fsm  <= 3'd0;
+            end
+            default: scroll_fsm <= 3'd0;
+        endcase
+    end
+end
+
+// ─── Sprite engine (Phase 3d) + oram port arbitration ──────────────────────
+// The sprite scanner and the scroll FSM share oram port-B.  They never
+// overlap (scroll = vblank entry, scanner = visible active lines), so a
+// simple priority mux suffices: scanner owns the port while obj_sc_cs is high.
+wire [12:0] obj_sc_addr;
+wire        obj_sc_cs;
+wire [18:0] obj_gfx_addr;
+wire        obj_gfx_cs;
+wire [11:0] obj_pixel;
+wire        obj_visible;
+
+always @* oram_addr_b = obj_sc_cs ? obj_sc_addr : scr_oram_addr;
+
+// obj gfx bus: sprites only. FG used to share this bus (muxed here); it now
+// has its own dedicated bus/bank (`fg`, bank 3), so the sprite engine owns
+// the obj bus outright — no mux, no FG-vs-sprite contention.
+always @* begin
+    obj_cs   = obj_gfx_cs;
+    obj_addr = obj_gfx_addr;
+end
+
+jttaitob_obj u_obj(
+    .rst       ( rst         ),
+    .clk       ( clk         ),
+    .pxl_cen   ( pxl_cen     ),
+    .LHBL      ( LHBL        ),
+    .LVBL      ( LVBL        ),
+    .hdump     ( hdump       ),
+    .vrender   ( vrender     ),
+    .sc_addr   ( obj_sc_addr ),
+    .sc_cs     ( obj_sc_cs   ),
+    .sc_data   ( oram_dout_b ),
+    .gfx_addr  ( obj_gfx_addr),
+    .gfx_cs    ( obj_gfx_cs  ),
+    .gfx_data  ( obj_data    ),
+    .gfx_ok    ( obj_ok      ),
+    .obj_pixel ( obj_pixel   ),
+    .obj_visible( obj_visible )
+);
+
+// ─── Plane scroll convention ───────────────────────────────────────────────
+// Per-plane scrolled coordinates.  The BG/FG planes are 64x64 tiles of
+// 16x16 pixels = 1024×1024 px wrap.  Only the bottom 10 bits matter
+// (the rest wraps over the 1024-px plane).
+//
+// MAME applies scroll with set_scrollx(0,-scrollx)/set_scrolly(0,-scrolly)
+// (tc0180vcu.cpp tilemap_draw): screen pixel maps to tilemap (pixel -
+// scrollram).  So we SUBTRACT the scroll register from the screen
+// position; adding it (the old code) scrolled both planes the wrong way.
+// scroll values are in pixel units, signed in the chip; wrap is natural.
+// (All three planes — BG, FG, TX — are rendered by line-buffer rings filled
+// during HBLANK; there is no per-slice look-ahead any more.)
+
+// ─── VRAM port-B arbitration ─────────────────────────────────────────────────
+// The three HBLANK ring fills share VRAM port-B in priority order BG -> FG ->
+// TX (they run back-to-back inside HBLANK; none of them render during it).
+always @* begin
+    if      (bg_fill_busy) vram_addr_b = bg_fill_vaddr;
+    else if (fg_fill_busy) vram_addr_b = fg_fill_vaddr;
+    else if (tx_fill_busy) vram_addr_b = tx_fill_vaddr;
+    else                   vram_addr_b = 16'd0;
+end
+
+// ─── gfx_sort address swap ──────────────────────────────────────────────────
+// mem.yaml applies gfx_sort=hvvvx (mode gfx4, b0=1) to the gfx region: it
+// rotates gfx-word address bits [3:0] as {b3->b0, b0->b1, b1->b2, b2->b3},
+// i.e. the tilelayout L/R-8px-half bit (px3, word bit 3) becomes the LSB so a
+// tile-row's two halves sit at adjacent addresses (read-cache hit on the 2nd).
+// Every gfx address the HDL generates must therefore be remapped the same way:
+//   sorted = {A[18:4], A[2:0], A[3]}
+// The 0x40000 plane-pair offset is bit 18 (outside the swapped window), so it
+// is added AFTER the swap and is unaffected.  Word data is untouched → decode
+// is unchanged.  TX (8x8) doesn't gain from the swap but must use it to read
+// the (now reordered) shared region correctly.
+function [18:0] gsort;
+    input [18:0] a;
+    gsort = {a[18:4], a[2:0], a[3]};
+endfunction
+
+// ════════════════════════════════════════════════════════════════════════
+// BG plane — full-line decoded-pixel buffer (jttaitob_shifter ring)
+// ════════════════════════════════════════════════════════════════════════
+// During HBLANK the upcoming scanline's BG tile-row is decoded into a 32-slot
+// ring (one 16-px tile per slot; slot = plane tile-col mod 32, a 512-px
+// window that covers the 320-px line with no slot aliasing).  During active
+// the renderer reads it with tap = (hdump - bg_scrollx), so sub-tile (fine)
+// horizontal scroll and tile-boundary straddles need no per-slice handling.
+// The fill borrows the VRAM port for code/attr (FG/TX don't render in HBLANK)
+// and reads gfx from the dedicated bg bus.  vrender (= vdump+1) is the line.
+localparam [5:0] BG_NTILES = 6'd22;     // tiles per line (320px + margin)
+
+// Fill line is LATCHED once at fill-kick (fill_line) and frozen for the
+// whole fill.  The fill runs during line N's HBLANK and is read on the next
+// active line (N+1); at kick vdump==N so we latch vrender (= N+1).  Latching
+// is essential, not cosmetic: vdump increments mid-HBLANK (at HS_START=340,
+// inside the gfx_sort-shortened fill window hdump 321..367), so a combinational
+// vrender flips N+1->N+2 partway through and fills early columns one row off
+// from late columns — the "first 19 cols 1px, last col 1px the other way"
+// symptom.  Freezing the line at kick makes every column use the same row.
+reg  [ 7:0] fill_line;
+wire [ 9:0] bg_fill_eff_y = {2'b0, fill_line} - bg_scrolly[9:0];
+wire [ 5:0] bg_fill_ty    = bg_fill_eff_y[9:4];
+wire [ 3:0] bg_fill_row   = bg_fill_eff_y[3:0];
+wire [ 9:0] bg_col0       = 10'd0 - bg_scrollx[9:0];   // leftmost visible tile @hdump=0
+
+reg  [ 3:0] bg_fst;                     // fill sub-state
+reg  [ 5:0] bg_fcnt;                    // tiles loaded this line
+reg  [ 5:0] bg_fcol;                    // plane tile-column being filled (0..63)
+reg  [15:0] bg_fcode, bg_fattr;
+reg  [15:0] bg_w01l, bg_w23l, bg_w01r;
+reg         bg_fill_busy;               // owns VRAM port while high
+reg         bg_ring_load;
+reg  [ 4:0] bg_ring_lidx;
+reg  [63:0] bg_ring_pix;
+reg  [11:0] bg_ring_pal;
+reg         bg_ring_flip;
+reg         LHBL_dly;
+
+wire        bg_fflipx = bg_fattr[6];
+wire        bg_fflipy = bg_fattr[7];
+wire [ 3:0] bg_frow_e = bg_fflipy ? ~bg_fill_row : bg_fill_row;
+wire [11:0] bg_fpal   = {(8'hC0 + {2'b00, bg_fattr[5:0]}), 4'b0000};
+wire [18:0] bg_fw01l  = gsort({bg_fcode[13:0], bg_frow_e[3], 1'b0, bg_frow_e[2:0]});
+wire [18:0] bg_fw01r  = gsort({bg_fcode[13:0], bg_frow_e[3], 1'b1, bg_frow_e[2:0]});
+wire [18:0] bg_fw23l  = bg_fw01l + 19'h40000;
+wire [18:0] bg_fw23r  = bg_fw01r + 19'h40000;
+wire [15:0] bg_fcode_addr = { bg_bank_codes[3:0], {bg_fill_ty, bg_fcol} };
+wire [15:0] bg_fattr_addr = { bg_bank_attrs[3:0], {bg_fill_ty, bg_fcol} };
+// VRAM address this FSM drives (code, then attr); arbitrated into vram_addr_b.
+wire [15:0] bg_fill_vaddr = (bg_fst==4'd2) ? bg_fattr_addr : bg_fcode_addr;
+wire        bg_fill_kick  = LHBL_dly & ~LHBL;          // enter HBLANK
+
+// One 4bpp pen of the current fill tile (normal order; flipX applied at load).
+// pen p: half=p[3], bit=~p[2:0]; pen = {w01lo,w01hi,w23lo,w23hi}[bit] — the
+// verified plane/byte order from the per-slice renderer.
+function [3:0] bg_pen;
+    input [ 3:0] p;
+    input [15:0] w01l, w23l, w01r, w23r;
+    reg   [ 3:0] b;
+    reg   [15:0] w01, w23;
+    begin
+        b   = {1'b0, ~p[2:0]};            // 0..7, 4-bit index into the 16-bit word
+        w01 = p[3] ? w01r : w01l;
+        w23 = p[3] ? w23r : w23l;
+        bg_pen = { w01[b], w01[b+4'd8], w23[b], w23[b+4'd8] };
+    end
+endfunction
+
+integer bp;
+always @(posedge clk) begin
+    if (rst) begin
+        bg_fst <= 4'd0; bg_fcnt <= 6'd0; bg_fcol <= 6'd0;
+        bg_cs <= 1'b0; bg_addr <= 19'd0;
+        bg_fill_busy <= 1'b0; bg_ring_load <= 1'b0; LHBL_dly <= 1'b1;
+        fill_line <= 8'd0;
+    end else begin
+        LHBL_dly     <= LHBL;
+        bg_ring_load <= 1'b0;
+        case (bg_fst)
+        4'd0: begin                                     // idle until HBLANK
+            bg_cs <= 1'b0; bg_fill_busy <= 1'b0;
+            if (bg_fill_kick) begin
+                bg_fcnt <= 6'd0; bg_fcol <= bg_col0[9:4];
+                fill_line <= vrender[7:0];           // freeze fill line (N+1) for the whole fill
+                bg_fill_busy <= 1'b1; bg_fst <= 4'd1;
+            end
+        end
+        4'd1: bg_fst <= 4'd2;                            // code addr on bus, settling
+        4'd2: begin bg_fcode <= vram_dout_b; bg_fst <= 4'd3; end // capture code; attr addr now driven
+        4'd3: begin bg_fattr <= vram_dout_b; bg_fst <= 4'd4; end // capture attr
+        4'd4: begin bg_cs <= 1'b1; bg_addr <= bg_fw01l; bg_fst <= 4'd5; end
+        4'd5: if (bg_ok) begin bg_w01l <= bg_data; bg_addr <= bg_fw23l; bg_fst <= 4'd6; end
+        4'd6: if (bg_ok) begin bg_w23l <= bg_data; bg_addr <= bg_fw01r; bg_fst <= 4'd7; end
+        4'd7: if (bg_ok) begin bg_w01r <= bg_data; bg_addr <= bg_fw23r; bg_fst <= 4'd8; end
+        4'd8: if (bg_ok) begin                          // bg_data = w23r
+            for (bp = 0; bp < 16; bp = bp + 1)
+                bg_ring_pix[4*bp +: 4] <= bg_pen(bp[3:0], bg_w01l, bg_w23l, bg_w01r, bg_data);
+            bg_ring_pal  <= bg_fpal;
+            bg_ring_flip <= bg_fflipx;
+            bg_ring_lidx <= bg_fcol[4:0];
+            bg_ring_load <= 1'b1;
+            bg_cs   <= 1'b0;
+            bg_fcol <= bg_fcol + 6'd1;
+            bg_fcnt <= bg_fcnt + 6'd1;
+            bg_fst  <= ((bg_fcnt + 6'd1) >= BG_NTILES) ? 4'd0 : 4'd1;
+        end
+        default: bg_fst <= 4'd0;
+        endcase
+    end
+end
+
+// BG ring + fine-scroll read tap.
+// +1: the shifter registers pen_out/pal_out on pxl_cen, so the BG read-out
+// carries one extra pixel of latency that the (combinational) FG path does
+// not.  With FG verified pixel-aligned to MAME, BG was landing 1px to the
+// right; advancing the tap by one pixel cancels that register delay.
+//
+// During HBLANK clamp the tap's hdump to 0 so it stays on the leftmost
+// visible tile instead of walking off into unfilled ring slots.  The shifter
+// then has the leftmost pixel registered by the first active pixel, priming
+// pal_idx@hdump0 — otherwise the registered read-out carried a 0 from an
+// unfilled slot into the first pixel (the 1px black left-edge artifact).
+// Active region (hdump 0..319) is unaffected.
+wire [ 8:0] bg_draw_hd = (hdump < 9'd320) ? hdump[8:0] : 9'd0;
+wire [ 9:0] bg_draw_x  = {1'b0, bg_draw_hd} - bg_scrollx[9:0] + 10'd1;
+wire [11:0] bg_idx;
+wire [ 3:0] bg_pen_out;
+jttaitob_shifter #(.TW(16), .LEN(32)) u_bg_ring(
+    .clk        ( clk          ),
+    .ce         ( pxl_cen      ),
+    .load       ( bg_ring_load ),
+    .load_index ( bg_ring_lidx ),
+    .load_pal   ( bg_ring_pal  ),
+    .load_pix   ( bg_ring_pix  ),
+    .load_flip  ( bg_ring_flip ),
+    .tap        ( bg_draw_x[8:0] ),
+    .pal_out    ( bg_idx       ),
+    .pen_out    ( bg_pen_out   )
+);
+wire [11:0] bg_pix_idx = bg_idx | {8'h0, bg_pen_out};
+
+// ════════════════════════════════════════════════════════════════════════
+// FG plane — full-line ring (Step 2: was per-slice).  Same structure as BG.
+// ════════════════════════════════════════════════════════════════════════
+// Fills the upcoming line's FG tile-row into u_fg_ring during HBLANK, AFTER
+// the BG fill finishes (they serialize on the shared VRAM port; FG gfx comes
+// from the obj bus).  Read during active with tap = hdump - fg_scrollx, so
+// fine (mod-8) horizontal scroll is handled for free — this deletes the
+// per-slice fetch_start / copy-pending band-aids.  Uses the SAME frozen
+// fill_line as BG (latched at bg_fill_kick) so the mid-HBLANK vdump increment
+// can't split the fill across columns.
+wire [ 9:0] fg_fill_eff_y = {2'b0, fill_line} - fg_scrolly[9:0];
+wire [ 5:0] fg_fill_ty    = fg_fill_eff_y[9:4];
+wire [ 3:0] fg_fill_row   = fg_fill_eff_y[3:0];
+wire [ 9:0] fg_col0       = 10'd0 - fg_scrollx[9:0];
+
+reg  [ 3:0] fg_fst;
+reg  [ 5:0] fg_fcnt;
+reg  [ 5:0] fg_fcol;
+reg  [15:0] fg_fcode, fg_fattr;
+reg  [15:0] fg_w01l, fg_w23l, fg_w01r;
+reg         fg_fill_busy;
+reg         fg_ring_load;
+reg  [ 4:0] fg_ring_lidx;
+reg  [63:0] fg_ring_pix;
+reg  [11:0] fg_ring_pal;
+reg         fg_ring_flip;
+reg         bg_busy_q;
+// FG fill drives the dedicated `fg` bus (bank 3) — fg_addr/fg_cs are module
+// output ports now, no longer muxed onto the obj bus.
+
+wire        fg_fflipx = fg_fattr[6];
+wire        fg_fflipy = fg_fattr[7];
+wire [ 3:0] fg_frow_e = fg_fflipy ? ~fg_fill_row : fg_fill_row;
+wire [11:0] fg_fpal   = {(8'h80 + {2'b00, fg_fattr[5:0]}), 4'b0000};
+wire [18:0] fg_fw01l  = gsort({fg_fcode[13:0], fg_frow_e[3], 1'b0, fg_frow_e[2:0]});
+wire [18:0] fg_fw01r  = gsort({fg_fcode[13:0], fg_frow_e[3], 1'b1, fg_frow_e[2:0]});
+wire [18:0] fg_fw23l  = fg_fw01l + 19'h40000;
+wire [18:0] fg_fw23r  = fg_fw01r + 19'h40000;
+wire [15:0] fg_fcode_addr = { fg_bank_codes[3:0], {fg_fill_ty, fg_fcol} };
+wire [15:0] fg_fattr_addr = { fg_bank_attrs[3:0], {fg_fill_ty, fg_fcol} };
+wire [15:0] fg_fill_vaddr = (fg_fst==4'd2) ? fg_fattr_addr : fg_fcode_addr;
+wire        fg_fill_kick  = bg_busy_q & ~bg_fill_busy;   // BG fill just finished
+
+integer fp;
+always @(posedge clk) begin
+    if (rst) begin
+        fg_fst <= 4'd0; fg_fcnt <= 6'd0; fg_fcol <= 6'd0;
+        fg_cs <= 1'b0; fg_addr <= 19'd0;
+        fg_fill_busy <= 1'b0; fg_ring_load <= 1'b0; bg_busy_q <= 1'b0;
+    end else begin
+        bg_busy_q    <= bg_fill_busy;
+        fg_ring_load <= 1'b0;
+        case (fg_fst)
+        4'd0: begin
+            fg_cs <= 1'b0; fg_fill_busy <= 1'b0;
+            if (fg_fill_kick) begin
+                fg_fcnt <= 6'd0; fg_fcol <= fg_col0[9:4];
+                fg_fill_busy <= 1'b1; fg_fst <= 4'd1;
+            end
+        end
+        4'd1: fg_fst <= 4'd2;
+        4'd2: begin fg_fcode <= vram_dout_b; fg_fst <= 4'd3; end
+        4'd3: begin fg_fattr <= vram_dout_b; fg_fst <= 4'd4; end
+        4'd4: begin fg_cs <= 1'b1; fg_addr <= fg_fw01l; fg_fst <= 4'd5; end
+        4'd5: if (fg_ok) begin fg_w01l <= fg_data; fg_addr <= fg_fw23l; fg_fst <= 4'd6; end
+        4'd6: if (fg_ok) begin fg_w23l <= fg_data; fg_addr <= fg_fw01r; fg_fst <= 4'd7; end
+        4'd7: if (fg_ok) begin fg_w01r <= fg_data; fg_addr <= fg_fw23r; fg_fst <= 4'd8; end
+        4'd8: if (fg_ok) begin                          // fg_data = w23r
+            for (fp = 0; fp < 16; fp = fp + 1)
+                fg_ring_pix[4*fp +: 4] <= bg_pen(fp[3:0], fg_w01l, fg_w23l, fg_w01r, fg_data);
+            fg_ring_pal  <= fg_fpal;
+            fg_ring_flip <= fg_fflipx;
+            fg_ring_lidx <= fg_fcol[4:0];
+            fg_ring_load <= 1'b1;
+            fg_cs  <= 1'b0;
+            fg_fcol <= fg_fcol + 6'd1;
+            fg_fcnt <= fg_fcnt + 6'd1;
+            fg_fst  <= ((fg_fcnt + 6'd1) >= BG_NTILES) ? 4'd0 : 4'd1;
+        end
+        default: fg_fst <= 4'd0;
+        endcase
+    end
+end
+
+// FG ring + fine-scroll read tap (same clamp/+1 as BG).
+wire [ 8:0] fg_draw_hd = (hdump < 9'd320) ? hdump[8:0] : 9'd0;
+wire [ 9:0] fg_draw_x  = {1'b0, fg_draw_hd} - fg_scrollx[9:0] + 10'd1;
+wire [11:0] fg_idx;
+wire [ 3:0] fg_pen_out;
+jttaitob_shifter #(.TW(16), .LEN(32)) u_fg_ring(
+    .clk        ( clk          ),
+    .ce         ( pxl_cen      ),
+    .load       ( fg_ring_load ),
+    .load_index ( fg_ring_lidx ),
+    .load_pal   ( fg_ring_pal  ),
+    .load_pix   ( fg_ring_pix  ),
+    .load_flip  ( fg_ring_flip ),
+    .tap        ( fg_draw_x[8:0] ),
+    .pal_out    ( fg_idx       ),
+    .pen_out    ( fg_pen_out   )
+);
+wire        fg_visible = |fg_pen_out;
+wire [11:0] fg_pix_idx = fg_idx | {8'h0, fg_pen_out};
+
+// ════════════════════════════════════════════════════════════════════════
+// TX plane — full-line ring (8x8 tiles).  Same approach as BG/FG.
+// ════════════════════════════════════════════════════════════════════════
+// 8x8 text tiles, no scroll, no flip.  ONE VRAM word per tile carries
+// {pal[15:12], hi[11], code[10:0]}.  Filled during HBLANK after the FG fill;
+// gfx on the tx bus.  TW=8, LEN=64 (full plane width; tap = hdump indexes it).
+// Reuses gsort + bg_pen + the shared frozen fill_line.  No scroll, so col0=0.
+localparam [6:0] TX_NTILES = 7'd42;     // 8px tiles to cover 320px + margin
+
+wire [ 4:0] tx_fill_ty  = fill_line[7:3];
+wire [ 2:0] tx_fill_row = fill_line[2:0];
+
+reg  [ 3:0] tx_fst;
+reg  [ 6:0] tx_fcnt;
+reg  [ 5:0] tx_fcol;                    // plane tile-column (0..63)
+reg  [15:0] tx_fword;                   // captured VRAM word (pal/hi/code)
+reg  [15:0] tx_w01;
+reg         tx_fill_busy;
+reg         tx_ring_load;
+reg  [ 5:0] tx_ring_lidx;
+reg  [31:0] tx_ring_pix;                // 8 px * 4bpp
+reg  [11:0] tx_ring_pal;
+reg         fg_busy_q;
+
+wire [ 3:0] tx_fhigh = tx_fword[11] ? tx_high_bank1[3:0] : tx_high_bank0[3:0];
+wire [14:0] tx_fcode = {tx_fhigh, tx_fword[10:0]};
+wire [11:0] tx_fpal  = {(8'h00 + {4'b0000, tx_fword[15:12]}), 4'b0000};
+wire [18:0] tx_fw01  = gsort({1'b0, tx_fcode, tx_fill_row});
+wire [18:0] tx_fw23  = tx_fw01 + 19'h40000;
+wire [15:0] tx_fill_vaddr = { 1'b0, tx_ram_bank[3:0], tx_fill_ty, tx_fcol };
+wire        tx_fill_kick  = fg_busy_q & ~fg_fill_busy;   // FG fill just finished
+
+integer tp;
+always @(posedge clk) begin
+    if (rst) begin
+        tx_fst <= 4'd0; tx_fcnt <= 7'd0; tx_fcol <= 6'd0;
+        tx_cs <= 1'b0; tx_addr <= 19'd0;
+        tx_fill_busy <= 1'b0; tx_ring_load <= 1'b0; fg_busy_q <= 1'b0;
+    end else begin
+        fg_busy_q    <= fg_fill_busy;
+        tx_ring_load <= 1'b0;
+        case (tx_fst)
+        4'd0: begin
+            tx_cs <= 1'b0; tx_fill_busy <= 1'b0;
+            if (tx_fill_kick) begin
+                tx_fcnt <= 7'd0; tx_fcol <= 6'd0;       // no scroll → start at col 0
+                tx_fill_busy <= 1'b1; tx_fst <= 4'd1;
+            end
+        end
+        4'd1: tx_fst <= 4'd2;                            // tx_word addr settling
+        4'd2: begin tx_fword <= vram_dout_b; tx_fst <= 4'd3; end   // capture tx_word
+        4'd3: begin tx_cs <= 1'b1; tx_addr <= tx_fw01; tx_fst <= 4'd4; end
+        4'd4: if (tx_ok) begin tx_w01 <= tx_data; tx_addr <= tx_fw23; tx_fst <= 4'd5; end
+        4'd5: if (tx_ok) begin                          // tx_data = w23
+            for (tp = 0; tp < 8; tp = tp + 1)
+                tx_ring_pix[4*tp +: 4] <= bg_pen({1'b0, tp[2:0]}, tx_w01, tx_data, tx_w01, tx_data);
+            tx_ring_pal  <= tx_fpal;
+            tx_ring_lidx <= tx_fcol;
+            tx_ring_load <= 1'b1;
+            tx_cs   <= 1'b0;
+            tx_fcol <= tx_fcol + 6'd1;
+            tx_fcnt <= tx_fcnt + 7'd1;
+            tx_fst  <= ((tx_fcnt + 7'd1) >= TX_NTILES) ? 4'd0 : 4'd1;
+        end
+        default: tx_fst <= 4'd0;
+        endcase
+    end
+end
+
+// ─── SIM: HBLANK fill-budget overrun detector ─────────────────────────────
+// The BG→FG→TX ring fills run sequentially during HBLANK. If any is still
+// busy when active resumes (LHBL rising), the fill overran the blank — the
+// tell-tale of a too-short H-blank (e.g. after dropping PXLCLK 8→6).
+`ifdef SIMULATION
+reg lhbl_q2;
+integer fill_overruns = 0;
+always @(posedge clk) begin
+    lhbl_q2 <= LHBL;
+    if (LHBL & ~lhbl_q2 && LVBL) begin           // HBLANK→active edge, visible field
+        if (bg_fill_busy | fg_fill_busy | tx_fill_busy) begin
+            fill_overruns = fill_overruns + 1;
+            $display("[FILL-OVERRUN #%0d] vrender=%0d at active start: bg=%b fg=%b tx=%b",
+                     fill_overruns, vrender, bg_fill_busy, fg_fill_busy, tx_fill_busy);
+        end
+    end
+end
+final $display("[FILL-OVERRUN] total overrunning lines = %0d", fill_overruns);
+`endif
+
+// TX ring + read tap (no scroll; +1 cancels the shifter register, HBLANK clamp).
+wire [ 8:0] tx_draw_hd = (hdump < 9'd320) ? hdump[8:0] : 9'd0;
+wire [ 8:0] tx_draw_x  = tx_draw_hd + 9'd1;
+wire [11:0] tx_idx;
+wire [ 3:0] tx_pen_out;
+jttaitob_shifter #(.TW(8), .LEN(64)) u_tx_ring(
+    .clk        ( clk          ),
+    .ce         ( pxl_cen      ),
+    .load       ( tx_ring_load ),
+    .load_index ( tx_ring_lidx ),
+    .load_pal   ( tx_ring_pal  ),
+    .load_pix   ( tx_ring_pix  ),
+    .load_flip  ( 1'b0         ),
+    .tap        ( tx_draw_x    ),
+    .pal_out    ( tx_idx       ),
+    .pen_out    ( tx_pen_out   )
+);
+wire        tx_visible = |tx_pen_out;
+wire [11:0] tx_pix_idx = tx_idx | {8'h0, tx_pen_out};
+
+// ─── Priority MUX (Phase 3b fixed order: TX > FG > BG) ─────────────────────
+// Emit the 12-bit palette INDEX.  Colmix owns the palette-RAM lookup AND the
+// LHBL/LVBL blanking, so we do NOT blank pal_idx here: gating it on the raw
+// (1px-lagging) LHBL added a redundant register stage that forced the first
+// active pixels to 0 even though bg_pix_idx was already valid — the 1-2px
+// black left-edge artifact.  Always emit the real pixel; colmix blanks.
+always @(posedge clk) begin
+    if (pxl_cen) begin
+        pal_idx <= tx_visible  ? tx_pix_idx :
+                   obj_visible ? obj_pixel  :       // Phase 3d: sprites (mode 1: bg<fg<obj<tx)
+                   fg_visible  ? fg_pix_idx :
+                                 bg_pix_idx;
+    end
+end
+
+/* verilator lint_off UNUSED */
+wire _unused_p3b = |vdump |
+                   |bg_scrollx[15:10] | |bg_scrolly[15:10] |
+                   |fg_scrollx[15:10] | |fg_scrolly[15:10] |
+                   |bg_col0[3:0] | |fg_col0[3:0] | vrender[8];
+/* verilator lint_on UNUSED */
+
+endmodule