From bd4d042f4f645c24f397ce1280215cd46e24cf54 Mon Sep 17 00:00:00 2001
From: Miki Saito <miki.saito@jotego.es>
Date: Wed, 1 Jul 2026 16:29:29 +0200
Subject: [PATCH] fix(simson): restore Vendetta audio balance

---
 cores/simson/cfg/mem.yaml               |  6 ++----
 cores/simson/hdl/jtsimson_sound.v       |  2 +-
 modules/jt053260/hdl/jt053260.v         | 12 ++++++------
 modules/jt053260/hdl/jt053260_channel.v |  4 ++--
 4 files changed, 11 insertions(+), 13 deletions(-)

diff --git a/cores/simson/cfg/mem.yaml b/cores/simson/cfg/mem.yaml
index d99f5e799d..780f89b895 100644
--- a/cores/simson/cfg/mem.yaml
+++ b/cores/simson/cfg/mem.yaml
@@ -11,14 +11,12 @@ clocks:
         - cen_fm
         - cen_fm2
 audio:
+  gain: 0.97
   rsum: 50k
   channels:
     # both FM and PCM are mixed inside K053260, then converted with the same YM3012 DAC
     # the 0.033MM capacitor in sch. has a 333K mark (physical device). 33nF must be right
-    # but 985 Ohm and 33nF is just too heavy damping, especially for the FM part that does
-    # not need an antialising filter. So I am using a much lighter 1nF instead that will
-    # let users hear the FM music better
-    - { name: snd, module: jt053260, rsum: 50k, rc: [ { r: 1rout, c: 2.2n }, { r: 985, c: 1n } ]}
+    - { name: snd, module: jt053260, rsum: 50k, rc: [ { r: 1rout, c: 2.2n }, { r: 985, c: 33n } ]}
 sdram:
   banks:
     - buses:
diff --git a/cores/simson/hdl/jtsimson_sound.v b/cores/simson/hdl/jtsimson_sound.v
index d861234d12..d282168e80 100644
--- a/cores/simson/hdl/jtsimson_sound.v
+++ b/cores/simson/hdl/jtsimson_sound.v
@@ -198,7 +198,7 @@ jt51 u_jt51(
     .xright     (           )
 );
 /* verilator tracing_off */
-jt053260 u_pcm(
+jt053260 #(.ADPCM_SAT(4'b0000),.AUX_MODE_EN(0)) u_pcm(
     .rst        ( rst_z80   ),
     .clk        ( clk       ),
     .cen        ( cen_fm    ),
diff --git a/modules/jt053260/hdl/jt053260.v b/modules/jt053260/hdl/jt053260.v
index bb273a8475..699ea0ecee 100644
--- a/modules/jt053260/hdl/jt053260.v
+++ b/modules/jt053260/hdl/jt053260.v
@@ -16,7 +16,7 @@
     Version: 1.0
     Date: 14-4-2023 */
 
-module jt053260(
+module jt053260#(parameter [3:0] ADPCM_SAT=4'hF, parameter AUX_MODE_EN=1)(
     input                    rst,
     input                    clk,
     input                    cen,
@@ -95,7 +95,7 @@ assign mmr_we  = {4{ cs & ~wr_n & mmr_en }} &
 assign tst_nx  = tst_rd & ~tst_rdl;
 assign left_en = sum_en[4:0];
 assign right_en={sum_en[5],sum_en[3:0]};
-assign aux_en  = mode[3:2];
+assign aux_en  = AUX_MODE_EN ? mode[3:2] : 2'b11;
 `ifdef SIMULATION
 assign tim2_enb= test_2b[3]; // it should disable tim2 when high. Not connected for now
 wire any_wr = cs & ~wr_n;
@@ -234,7 +234,7 @@ always @* begin
     pan3_r = pan_dec_r( ch3_pan );
 end
 
-jt053260_channel #(.TESTRD(1)) u_ch0(
+jt053260_channel #(.TESTRD(1),.ADPCM_SAT(ADPCM_SAT[0])) u_ch0(
     .rst      ( rst         ),
     .clk      ( clk         ),
     .cen      ( cen         ),
@@ -263,7 +263,7 @@ jt053260_channel #(.TESTRD(1)) u_ch0(
     .snd_r    ( ch0_snd_r   )
 );
 
-jt053260_channel u_ch1(
+jt053260_channel #(.ADPCM_SAT(ADPCM_SAT[1])) u_ch1(
     .rst      ( rst         ),
     .clk      ( clk         ),
     .cen      ( cen         ),
@@ -292,7 +292,7 @@ jt053260_channel u_ch1(
     .snd_r    ( ch1_snd_r   )
 );
 
-jt053260_channel u_ch2(
+jt053260_channel #(.ADPCM_SAT(ADPCM_SAT[2])) u_ch2(
     .rst      ( rst         ),
     .clk      ( clk         ),
     .cen      ( cen         ),
@@ -321,7 +321,7 @@ jt053260_channel u_ch2(
     .snd_r    ( ch2_snd_r   )
 );
 
-jt053260_channel u_ch3(
+jt053260_channel #(.ADPCM_SAT(ADPCM_SAT[3])) u_ch3(
     .rst      ( rst         ),
     .clk      ( clk         ),
     .cen      ( cen         ),
diff --git a/modules/jt053260/hdl/jt053260_channel.v b/modules/jt053260/hdl/jt053260_channel.v
index d2ded227c2..01a46df7c6 100644
--- a/modules/jt053260/hdl/jt053260_channel.v
+++ b/modules/jt053260/hdl/jt053260_channel.v
@@ -16,7 +16,7 @@
     Version: 1.0
     Date: 14-4-2023 */
 
-module jt053260_channel#(parameter TESTRD=0)(
+module jt053260_channel#(parameter TESTRD=0, parameter ADPCM_SAT=1)(
     input                    rst,
     input                    clk,
     input                    cen,
@@ -168,7 +168,7 @@ always @(posedge clk) begin
                             end
                         end
                     end
-                    pre_snd <= adpcm_en ? adpcm_lim : rom_data;
+                    pre_snd <= adpcm_en ? (ADPCM_SAT ? adpcm_lim : pre_snd + kadpcm) : rom_data;
                 end
             end
         end