From ce147e44ca2cf19d67cb78e3bee57348ea63e263 Mon Sep 17 00:00:00 2001 From: Leigh Oliver Date: Fri, 3 Apr 2026 08:19:54 +1100 Subject: [PATCH 1/4] Fixup Peripherals::take() API to align with esp-hal, ran cargo-fmt --- esp32s2-ulp/build.rs | 5 +---- esp32s2-ulp/src/interrupt.rs | 16 ++++++++-------- esp32s2-ulp/src/lib.rs | 16 ++++++++-------- esp32s3-ulp/build.rs | 5 +---- esp32s3-ulp/src/interrupt.rs | 22 +++++++++++----------- esp32s3-ulp/src/lib.rs | 16 ++++++++-------- 6 files changed, 37 insertions(+), 43 deletions(-) diff --git a/esp32s2-ulp/build.rs b/esp32s2-ulp/build.rs index d0781acdb6..a742427679 100644 --- a/esp32s2-ulp/build.rs +++ b/esp32s2-ulp/build.rs @@ -1,8 +1,5 @@ #![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; +use std::{env, fs::File, io::Write, path::PathBuf}; fn main() { if env::var_os("CARGO_FEATURE_RT").is_some() { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); diff --git a/esp32s2-ulp/src/interrupt.rs b/esp32s2-ulp/src/interrupt.rs index 466ccbb684..23d6556133 100644 --- a/esp32s2-ulp/src/interrupt.rs +++ b/esp32s2-ulp/src/interrupt.rs @@ -4,23 +4,23 @@ #[repr(u16)] pub enum Interrupt { #[doc = "0 - TOUCH_DONE_INT"] - TOUCH_DONE_INT = 0, + TOUCH_DONE_INT = 0, #[doc = "1 - TOUCH_INACTIVE_INT"] TOUCH_INACTIVE_INT = 1, #[doc = "2 - TOUCH_ACTIVE_INT"] - TOUCH_ACTIVE_INT = 2, + TOUCH_ACTIVE_INT = 2, #[doc = "3 - SARADC1_DONE_INT"] - SARADC1_DONE_INT = 3, + SARADC1_DONE_INT = 3, #[doc = "4 - SARADC2_DONE_INT"] - SARADC2_DONE_INT = 4, + SARADC2_DONE_INT = 4, #[doc = "5 - TSENS_DONE_INT"] - TSENS_DONE_INT = 5, + TSENS_DONE_INT = 5, #[doc = "6 - RISCV_START_INT"] - RISCV_START_INT = 6, + RISCV_START_INT = 6, #[doc = "7 - SW_INT"] - SW_INT = 7, + SW_INT = 7, #[doc = "8 - SWD_INT"] - SWD_INT = 8, + SWD_INT = 8, } #[doc = r" TryFromInterruptError"] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/esp32s2-ulp/src/lib.rs b/esp32s2-ulp/src/lib.rs index 829ed6b15b..f56aa31296 100644 --- a/esp32s2-ulp/src/lib.rs +++ b/esp32s2-ulp/src/lib.rs @@ -96,8 +96,6 @@ impl core::fmt::Debug for SENS { } #[doc = "SENS Peripheral"] pub mod sens; -#[no_mangle] -static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] #[allow(non_snake_case)] pub struct Peripherals { @@ -114,12 +112,15 @@ impl Peripherals { #[doc = r" Returns all the peripherals *once*."] #[cfg(feature = "critical-section")] #[inline] - pub fn take() -> Option { - critical_section::with(|_| { - if unsafe { DEVICE_PERIPHERALS } { - return None; + pub fn take() -> Self { + #[no_mangle] + static mut DEVICE_PERIPHERALS: bool = false; + + critical_section::with(|_| unsafe { + if DEVICE_PERIPHERALS { + core::panic!("Peripheral was taken more than once!"); } - Some(unsafe { Peripherals::steal() }) + Self::steal() }) } #[doc = r" Unchecked version of `Peripherals::take`."] @@ -129,7 +130,6 @@ impl Peripherals { #[doc = r" Each of the returned peripherals must be used at most once."] #[inline] pub unsafe fn steal() -> Self { - DEVICE_PERIPHERALS = true; Peripherals { RTC_IO: RTC_IO::steal(), RTC_CNTL: RTC_CNTL::steal(), diff --git a/esp32s3-ulp/build.rs b/esp32s3-ulp/build.rs index d0781acdb6..a742427679 100644 --- a/esp32s3-ulp/build.rs +++ b/esp32s3-ulp/build.rs @@ -1,8 +1,5 @@ #![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; +use std::{env, fs::File, io::Write, path::PathBuf}; fn main() { if env::var_os("CARGO_FEATURE_RT").is_some() { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); diff --git a/esp32s3-ulp/src/interrupt.rs b/esp32s3-ulp/src/interrupt.rs index d986a2c4fe..1be010bec5 100644 --- a/esp32s3-ulp/src/interrupt.rs +++ b/esp32s3-ulp/src/interrupt.rs @@ -4,29 +4,29 @@ #[repr(u16)] pub enum Interrupt { #[doc = "0 - TOUCH_DONE_INT"] - TOUCH_DONE_INT = 0, + TOUCH_DONE_INT = 0, #[doc = "1 - TOUCH_INACTIVE_INT"] - TOUCH_INACTIVE_INT = 1, + TOUCH_INACTIVE_INT = 1, #[doc = "2 - TOUCH_ACTIVE_INT"] - TOUCH_ACTIVE_INT = 2, + TOUCH_ACTIVE_INT = 2, #[doc = "3 - SARADC1_DONE_INT"] - SARADC1_DONE_INT = 3, + SARADC1_DONE_INT = 3, #[doc = "4 - SARADC2_DONE_INT"] - SARADC2_DONE_INT = 4, + SARADC2_DONE_INT = 4, #[doc = "5 - TSENS_DONE_INT"] - TSENS_DONE_INT = 5, + TSENS_DONE_INT = 5, #[doc = "6 - RISCV_START_INT"] - RISCV_START_INT = 6, + RISCV_START_INT = 6, #[doc = "7 - SW_INT"] - SW_INT = 7, + SW_INT = 7, #[doc = "8 - SWD_INT"] - SWD_INT = 8, + SWD_INT = 8, #[doc = "9 - TOUCH_TIME_OUT_INT"] - TOUCH_TIME_OUT_INT = 9, + TOUCH_TIME_OUT_INT = 9, #[doc = "10 - TOUCH_APPROACH_LOOP_DONE_INT"] TOUCH_APPROACH_LOOP_DONE_INT = 10, #[doc = "11 - TOUCH_SCAN_DONE_INT"] - TOUCH_SCAN_DONE_INT = 11, + TOUCH_SCAN_DONE_INT = 11, } #[doc = r" TryFromInterruptError"] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/esp32s3-ulp/src/lib.rs b/esp32s3-ulp/src/lib.rs index d21fbbfd61..a122b82976 100644 --- a/esp32s3-ulp/src/lib.rs +++ b/esp32s3-ulp/src/lib.rs @@ -108,8 +108,6 @@ impl core::fmt::Debug for SENS { } #[doc = "SENS Peripheral"] pub mod sens; -#[no_mangle] -static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] #[allow(non_snake_case)] pub struct Peripherals { @@ -126,12 +124,15 @@ impl Peripherals { #[doc = r" Returns all the peripherals *once*."] #[cfg(feature = "critical-section")] #[inline] - pub fn take() -> Option { - critical_section::with(|_| { - if unsafe { DEVICE_PERIPHERALS } { - return None; + pub fn take() -> Self { + #[no_mangle] + static mut DEVICE_PERIPHERALS: bool = false; + + critical_section::with(|_| unsafe { + if DEVICE_PERIPHERALS { + core::panic!("Peripheral was taken more than once!"); } - Some(unsafe { Peripherals::steal() }) + Self::steal() }) } #[doc = r" Unchecked version of `Peripherals::take`."] @@ -141,7 +142,6 @@ impl Peripherals { #[doc = r" Each of the returned peripherals must be used at most once."] #[inline] pub unsafe fn steal() -> Self { - DEVICE_PERIPHERALS = true; Peripherals { RTC_CNTL: RTC_CNTL::steal(), RTC_I2C: RTC_I2C::steal(), From 5ff8e30e2ad103415490381635f471ccaae24d67 Mon Sep 17 00:00:00 2001 From: Leigh Oliver Date: Fri, 3 Apr 2026 08:23:18 +1100 Subject: [PATCH 2/4] Add GPIO interrupt entry --- esp32s2-ulp/build.rs | 5 ++++- esp32s2-ulp/device.x | 1 + esp32s2-ulp/src/interrupt.rs | 19 +++++++++++-------- esp32s2-ulp/src/lib.rs | 20 +++++++++++--------- esp32s2-ulp/svd/esp32s2-ulp.base.svd | 4 ++++ esp32s3-ulp/build.rs | 5 ++++- esp32s3-ulp/device.x | 1 + esp32s3-ulp/src/interrupt.rs | 25 ++++++++++++++----------- esp32s3-ulp/src/lib.rs | 20 +++++++++++--------- esp32s3-ulp/svd/esp32s3-ulp.base.svd | 4 ++++ 10 files changed, 65 insertions(+), 39 deletions(-) diff --git a/esp32s2-ulp/build.rs b/esp32s2-ulp/build.rs index a742427679..d0781acdb6 100644 --- a/esp32s2-ulp/build.rs +++ b/esp32s2-ulp/build.rs @@ -1,5 +1,8 @@ #![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::{env, fs::File, io::Write, path::PathBuf}; +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; fn main() { if env::var_os("CARGO_FEATURE_RT").is_some() { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); diff --git a/esp32s2-ulp/device.x b/esp32s2-ulp/device.x index feac5af20d..5193c56bab 100644 --- a/esp32s2-ulp/device.x +++ b/esp32s2-ulp/device.x @@ -7,4 +7,5 @@ PROVIDE(TSENS_DONE_INT = DefaultHandler); PROVIDE(RISCV_START_INT = DefaultHandler); PROVIDE(SW_INT = DefaultHandler); PROVIDE(SWD_INT = DefaultHandler); +PROVIDE(GPIO_INT = DefaultHandler); diff --git a/esp32s2-ulp/src/interrupt.rs b/esp32s2-ulp/src/interrupt.rs index 23d6556133..eccc9291e0 100644 --- a/esp32s2-ulp/src/interrupt.rs +++ b/esp32s2-ulp/src/interrupt.rs @@ -4,23 +4,25 @@ #[repr(u16)] pub enum Interrupt { #[doc = "0 - TOUCH_DONE_INT"] - TOUCH_DONE_INT = 0, + TOUCH_DONE_INT = 0, #[doc = "1 - TOUCH_INACTIVE_INT"] TOUCH_INACTIVE_INT = 1, #[doc = "2 - TOUCH_ACTIVE_INT"] - TOUCH_ACTIVE_INT = 2, + TOUCH_ACTIVE_INT = 2, #[doc = "3 - SARADC1_DONE_INT"] - SARADC1_DONE_INT = 3, + SARADC1_DONE_INT = 3, #[doc = "4 - SARADC2_DONE_INT"] - SARADC2_DONE_INT = 4, + SARADC2_DONE_INT = 4, #[doc = "5 - TSENS_DONE_INT"] - TSENS_DONE_INT = 5, + TSENS_DONE_INT = 5, #[doc = "6 - RISCV_START_INT"] - RISCV_START_INT = 6, + RISCV_START_INT = 6, #[doc = "7 - SW_INT"] - SW_INT = 7, + SW_INT = 7, #[doc = "8 - SWD_INT"] - SWD_INT = 8, + SWD_INT = 8, + #[doc = "9 - GPIO_INT"] + GPIO_INT = 9, } #[doc = r" TryFromInterruptError"] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -40,6 +42,7 @@ impl Interrupt { 6 => Ok(Interrupt::RISCV_START_INT), 7 => Ok(Interrupt::SW_INT), 8 => Ok(Interrupt::SWD_INT), + 9 => Ok(Interrupt::GPIO_INT), _ => Err(TryFromInterruptError(())), } } diff --git a/esp32s2-ulp/src/lib.rs b/esp32s2-ulp/src/lib.rs index f56aa31296..e09162ea94 100644 --- a/esp32s2-ulp/src/lib.rs +++ b/esp32s2-ulp/src/lib.rs @@ -21,6 +21,7 @@ extern "C" { fn RISCV_START_INT(); fn SW_INT(); fn SWD_INT(); + fn GPIO_INT(); } #[doc(hidden)] #[repr(C)] @@ -32,7 +33,7 @@ pub union Vector { #[doc(hidden)] #[link_section = ".rwtext"] #[no_mangle] -pub static __EXTERNAL_INTERRUPTS: [Vector; 9] = [ +pub static __EXTERNAL_INTERRUPTS: [Vector; 10] = [ Vector { _handler: TOUCH_DONE_INT, }, @@ -56,6 +57,7 @@ pub static __EXTERNAL_INTERRUPTS: [Vector; 9] = [ }, Vector { _handler: SW_INT }, Vector { _handler: SWD_INT }, + Vector { _handler: GPIO_INT }, ]; #[doc(hidden)] pub mod interrupt; @@ -96,6 +98,8 @@ impl core::fmt::Debug for SENS { } #[doc = "SENS Peripheral"] pub mod sens; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] #[allow(non_snake_case)] pub struct Peripherals { @@ -112,15 +116,12 @@ impl Peripherals { #[doc = r" Returns all the peripherals *once*."] #[cfg(feature = "critical-section")] #[inline] - pub fn take() -> Self { - #[no_mangle] - static mut DEVICE_PERIPHERALS: bool = false; - - critical_section::with(|_| unsafe { - if DEVICE_PERIPHERALS { - core::panic!("Peripheral was taken more than once!"); + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; } - Self::steal() + Some(unsafe { Peripherals::steal() }) }) } #[doc = r" Unchecked version of `Peripherals::take`."] @@ -130,6 +131,7 @@ impl Peripherals { #[doc = r" Each of the returned peripherals must be used at most once."] #[inline] pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; Peripherals { RTC_IO: RTC_IO::steal(), RTC_CNTL: RTC_CNTL::steal(), diff --git a/esp32s2-ulp/svd/esp32s2-ulp.base.svd b/esp32s2-ulp/svd/esp32s2-ulp.base.svd index ff6bdeae4f..534182b6f1 100644 --- a/esp32s2-ulp/svd/esp32s2-ulp.base.svd +++ b/esp32s2-ulp/svd/esp32s2-ulp.base.svd @@ -43,6 +43,10 @@ 0xF0 registers + + GPIO_INT + 9 + RTC_GPIO_OUT diff --git a/esp32s3-ulp/build.rs b/esp32s3-ulp/build.rs index a742427679..d0781acdb6 100644 --- a/esp32s3-ulp/build.rs +++ b/esp32s3-ulp/build.rs @@ -1,5 +1,8 @@ #![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::{env, fs::File, io::Write, path::PathBuf}; +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; fn main() { if env::var_os("CARGO_FEATURE_RT").is_some() { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); diff --git a/esp32s3-ulp/device.x b/esp32s3-ulp/device.x index f4c05be9c5..33a42d0c48 100644 --- a/esp32s3-ulp/device.x +++ b/esp32s3-ulp/device.x @@ -10,4 +10,5 @@ PROVIDE(SWD_INT = DefaultHandler); PROVIDE(TOUCH_TIME_OUT_INT = DefaultHandler); PROVIDE(TOUCH_APPROACH_LOOP_DONE_INT = DefaultHandler); PROVIDE(TOUCH_SCAN_DONE_INT = DefaultHandler); +PROVIDE(GPIO_INT = DefaultHandler); diff --git a/esp32s3-ulp/src/interrupt.rs b/esp32s3-ulp/src/interrupt.rs index 1be010bec5..fe35e49a44 100644 --- a/esp32s3-ulp/src/interrupt.rs +++ b/esp32s3-ulp/src/interrupt.rs @@ -4,29 +4,31 @@ #[repr(u16)] pub enum Interrupt { #[doc = "0 - TOUCH_DONE_INT"] - TOUCH_DONE_INT = 0, + TOUCH_DONE_INT = 0, #[doc = "1 - TOUCH_INACTIVE_INT"] - TOUCH_INACTIVE_INT = 1, + TOUCH_INACTIVE_INT = 1, #[doc = "2 - TOUCH_ACTIVE_INT"] - TOUCH_ACTIVE_INT = 2, + TOUCH_ACTIVE_INT = 2, #[doc = "3 - SARADC1_DONE_INT"] - SARADC1_DONE_INT = 3, + SARADC1_DONE_INT = 3, #[doc = "4 - SARADC2_DONE_INT"] - SARADC2_DONE_INT = 4, + SARADC2_DONE_INT = 4, #[doc = "5 - TSENS_DONE_INT"] - TSENS_DONE_INT = 5, + TSENS_DONE_INT = 5, #[doc = "6 - RISCV_START_INT"] - RISCV_START_INT = 6, + RISCV_START_INT = 6, #[doc = "7 - SW_INT"] - SW_INT = 7, + SW_INT = 7, #[doc = "8 - SWD_INT"] - SWD_INT = 8, + SWD_INT = 8, #[doc = "9 - TOUCH_TIME_OUT_INT"] - TOUCH_TIME_OUT_INT = 9, + TOUCH_TIME_OUT_INT = 9, #[doc = "10 - TOUCH_APPROACH_LOOP_DONE_INT"] TOUCH_APPROACH_LOOP_DONE_INT = 10, #[doc = "11 - TOUCH_SCAN_DONE_INT"] - TOUCH_SCAN_DONE_INT = 11, + TOUCH_SCAN_DONE_INT = 11, + #[doc = "12 - GPIO_INT"] + GPIO_INT = 12, } #[doc = r" TryFromInterruptError"] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -49,6 +51,7 @@ impl Interrupt { 9 => Ok(Interrupt::TOUCH_TIME_OUT_INT), 10 => Ok(Interrupt::TOUCH_APPROACH_LOOP_DONE_INT), 11 => Ok(Interrupt::TOUCH_SCAN_DONE_INT), + 12 => Ok(Interrupt::GPIO_INT), _ => Err(TryFromInterruptError(())), } } diff --git a/esp32s3-ulp/src/lib.rs b/esp32s3-ulp/src/lib.rs index a122b82976..25402e5e58 100644 --- a/esp32s3-ulp/src/lib.rs +++ b/esp32s3-ulp/src/lib.rs @@ -24,6 +24,7 @@ extern "C" { fn TOUCH_TIME_OUT_INT(); fn TOUCH_APPROACH_LOOP_DONE_INT(); fn TOUCH_SCAN_DONE_INT(); + fn GPIO_INT(); } #[doc(hidden)] #[repr(C)] @@ -35,7 +36,7 @@ pub union Vector { #[doc(hidden)] #[link_section = ".rwtext"] #[no_mangle] -pub static __EXTERNAL_INTERRUPTS: [Vector; 12] = [ +pub static __EXTERNAL_INTERRUPTS: [Vector; 13] = [ Vector { _handler: TOUCH_DONE_INT, }, @@ -68,6 +69,7 @@ pub static __EXTERNAL_INTERRUPTS: [Vector; 12] = [ Vector { _handler: TOUCH_SCAN_DONE_INT, }, + Vector { _handler: GPIO_INT }, ]; #[doc(hidden)] pub mod interrupt; @@ -108,6 +110,8 @@ impl core::fmt::Debug for SENS { } #[doc = "SENS Peripheral"] pub mod sens; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; #[doc = r" All the peripherals."] #[allow(non_snake_case)] pub struct Peripherals { @@ -124,15 +128,12 @@ impl Peripherals { #[doc = r" Returns all the peripherals *once*."] #[cfg(feature = "critical-section")] #[inline] - pub fn take() -> Self { - #[no_mangle] - static mut DEVICE_PERIPHERALS: bool = false; - - critical_section::with(|_| unsafe { - if DEVICE_PERIPHERALS { - core::panic!("Peripheral was taken more than once!"); + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; } - Self::steal() + Some(unsafe { Peripherals::steal() }) }) } #[doc = r" Unchecked version of `Peripherals::take`."] @@ -142,6 +143,7 @@ impl Peripherals { #[doc = r" Each of the returned peripherals must be used at most once."] #[inline] pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; Peripherals { RTC_CNTL: RTC_CNTL::steal(), RTC_I2C: RTC_I2C::steal(), diff --git a/esp32s3-ulp/svd/esp32s3-ulp.base.svd b/esp32s3-ulp/svd/esp32s3-ulp.base.svd index 84b003baca..b5a22076ce 100644 --- a/esp32s3-ulp/svd/esp32s3-ulp.base.svd +++ b/esp32s3-ulp/svd/esp32s3-ulp.base.svd @@ -5834,6 +5834,10 @@ 0xF0 registers + + GPIO_INT + 12 + RTC_GPIO_OUT From 523bb7917924427042f0e84853351758b66fb76b Mon Sep 17 00:00:00 2001 From: Leigh Oliver Date: Tue, 14 Apr 2026 07:58:06 +1000 Subject: [PATCH 3/4] Collect S3-ULP pins into an array, update S2-ULP pin method prefix (#1) --- esp32s2-ulp/src/rtc_io/pin.rs | 54 ++--- esp32s2-ulp/svd/esp32s2-ulp.base.svd | 1 + esp32s2-ulp/svd/patches/esp32s2-ulp.yaml | 4 +- esp32s3-ulp/src/rtc_io.rs | 230 ++------------------- esp32s3-ulp/src/rtc_io/{pin0.rs => pin.rs} | 34 +-- esp32s3-ulp/src/rtc_io/pin1.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin10.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin11.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin12.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin13.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin14.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin15.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin16.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin17.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin18.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin19.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin2.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin20.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin21.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin3.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin4.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin5.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin6.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin7.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin8.rs | 73 ------- esp32s3-ulp/src/rtc_io/pin9.rs | 73 ------- esp32s3-ulp/svd/patches/esp32s3-ulp.yaml | 4 +- 27 files changed, 62 insertions(+), 1798 deletions(-) rename esp32s3-ulp/src/rtc_io/{pin0.rs => pin.rs} (73%) delete mode 100644 esp32s3-ulp/src/rtc_io/pin1.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin10.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin11.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin12.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin13.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin14.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin15.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin16.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin17.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin18.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin19.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin2.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin20.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin21.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin3.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin4.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin5.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin6.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin7.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin8.rs delete mode 100644 esp32s3-ulp/src/rtc_io/pin9.rs diff --git a/esp32s2-ulp/src/rtc_io/pin.rs b/esp32s2-ulp/src/rtc_io/pin.rs index ba9c5cc07f..fbabc1081f 100644 --- a/esp32s2-ulp/src/rtc_io/pin.rs +++ b/esp32s2-ulp/src/rtc_io/pin.rs @@ -2,60 +2,60 @@ pub type R = crate::R; #[doc = "Register `PIN%s` writer"] pub type W = crate::W; -#[doc = "Field `GPIO_PIN_PAD_DRIVER` reader - Pad driver selection. 0: normal output. 1: open drain."] -pub type GPIO_PIN_PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `GPIO_PIN_PAD_DRIVER` writer - Pad driver selection. 0: normal output. 1: open drain."] -pub type GPIO_PIN_PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `GPIO_PIN_INT_TYPE` reader - GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger."] -pub type GPIO_PIN_INT_TYPE_R = crate::FieldReader; -#[doc = "Field `GPIO_PIN_INT_TYPE` writer - GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger."] -pub type GPIO_PIN_INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `GPIO_PIN_WAKEUP_ENABLE` reader - GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep."] -pub type GPIO_PIN_WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `GPIO_PIN_WAKEUP_ENABLE` writer - GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep."] -pub type GPIO_PIN_WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `PAD_DRIVER` reader - Pad driver selection. 0: normal output. 1: open drain."] +pub type PAD_DRIVER_R = crate::BitReader; +#[doc = "Field `PAD_DRIVER` writer - Pad driver selection. 0: normal output. 1: open drain."] +pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; +#[doc = "Field `INT_TYPE` reader - GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger."] +pub type INT_TYPE_R = crate::FieldReader; +#[doc = "Field `INT_TYPE` writer - GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger."] +pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; +#[doc = "Field `WAKEUP_ENABLE` reader - GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep."] +pub type WAKEUP_ENABLE_R = crate::BitReader; +#[doc = "Field `WAKEUP_ENABLE` writer - GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep."] +pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; impl R { #[doc = "Bit 2 - Pad driver selection. 0: normal output. 1: open drain."] #[inline(always)] - pub fn gpio_pin_pad_driver(&self) -> GPIO_PIN_PAD_DRIVER_R { - GPIO_PIN_PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) + pub fn pad_driver(&self) -> PAD_DRIVER_R { + PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) } #[doc = "Bits 7:9 - GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger."] #[inline(always)] - pub fn gpio_pin_int_type(&self) -> GPIO_PIN_INT_TYPE_R { - GPIO_PIN_INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) + pub fn int_type(&self) -> INT_TYPE_R { + INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) } #[doc = "Bit 10 - GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep."] #[inline(always)] - pub fn gpio_pin_wakeup_enable(&self) -> GPIO_PIN_WAKEUP_ENABLE_R { - GPIO_PIN_WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) + pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { + WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) } } #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.debug_struct("PIN") - .field("gpio_pin_pad_driver", &self.gpio_pin_pad_driver()) - .field("gpio_pin_int_type", &self.gpio_pin_int_type()) - .field("gpio_pin_wakeup_enable", &self.gpio_pin_wakeup_enable()) + .field("pad_driver", &self.pad_driver()) + .field("int_type", &self.int_type()) + .field("wakeup_enable", &self.wakeup_enable()) .finish() } } impl W { #[doc = "Bit 2 - Pad driver selection. 0: normal output. 1: open drain."] #[inline(always)] - pub fn gpio_pin_pad_driver(&mut self) -> GPIO_PIN_PAD_DRIVER_W<'_, PIN_SPEC> { - GPIO_PIN_PAD_DRIVER_W::new(self, 2) + pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN_SPEC> { + PAD_DRIVER_W::new(self, 2) } #[doc = "Bits 7:9 - GPIO interrupt type selection. 0: GPIO interrupt disabled. 1: rising edge trigger. 2: falling edge trigger. 3: any edge trigger. 4: low level trigger. 5: high level trigger."] #[inline(always)] - pub fn gpio_pin_int_type(&mut self) -> GPIO_PIN_INT_TYPE_W<'_, PIN_SPEC> { - GPIO_PIN_INT_TYPE_W::new(self, 7) + pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN_SPEC> { + INT_TYPE_W::new(self, 7) } #[doc = "Bit 10 - GPIO wake-up enable. This will only wake up ESP32-S2 from Light-sleep."] #[inline(always)] - pub fn gpio_pin_wakeup_enable(&mut self) -> GPIO_PIN_WAKEUP_ENABLE_W<'_, PIN_SPEC> { - GPIO_PIN_WAKEUP_ENABLE_W::new(self, 10) + pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN_SPEC> { + WAKEUP_ENABLE_W::new(self, 10) } } #[doc = "RTC configuration for pin %s\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] diff --git a/esp32s2-ulp/svd/esp32s2-ulp.base.svd b/esp32s2-ulp/svd/esp32s2-ulp.base.svd index 534182b6f1..6a62932e75 100644 --- a/esp32s2-ulp/svd/esp32s2-ulp.base.svd +++ b/esp32s2-ulp/svd/esp32s2-ulp.base.svd @@ -201,6 +201,7 @@ 22 0x4 + 0-21 RTC_GPIO_PIN%s RTC configuration for pin %s 0x28 diff --git a/esp32s2-ulp/svd/patches/esp32s2-ulp.yaml b/esp32s2-ulp/svd/patches/esp32s2-ulp.yaml index 0642ed9346..ae181f168e 100644 --- a/esp32s2-ulp/svd/patches/esp32s2-ulp.yaml +++ b/esp32s2-ulp/svd/patches/esp32s2-ulp.yaml @@ -6,14 +6,14 @@ _include: RTC_IO: _strip: "RTC_GPIO_" - "*": _strip: "RTC_" - OUT_W1TC: _strip: "GPIO_" OUT_W1TS: _strip: "GPIO_" + PIN*: + _strip: "GPIO_PIN_" RTC_I2C: CMD*: diff --git a/esp32s3-ulp/src/rtc_io.rs b/esp32s3-ulp/src/rtc_io.rs index 35c5ab2ab6..0f84c07985 100644 --- a/esp32s3-ulp/src/rtc_io.rs +++ b/esp32s3-ulp/src/rtc_io.rs @@ -12,28 +12,7 @@ pub struct RegisterBlock { status_w1ts: STATUS_W1TS, status_w1tc: STATUS_W1TC, in_: IN, - pin0: PIN0, - pin1: PIN1, - pin2: PIN2, - pin3: PIN3, - pin4: PIN4, - pin5: PIN5, - pin6: PIN6, - pin7: PIN7, - pin8: PIN8, - pin9: PIN9, - pin10: PIN10, - pin11: PIN11, - pin12: PIN12, - pin13: PIN13, - pin14: PIN14, - pin15: PIN15, - pin16: PIN16, - pin17: PIN17, - pin18: PIN18, - pin19: PIN19, - pin20: PIN20, - pin21: PIN21, + pin: [PIN; 22], rtc_debug_sel: RTC_DEBUG_SEL, touch_pad0: TOUCH_PAD0, touch_pad1: TOUCH_PAD1, @@ -61,7 +40,7 @@ pub struct RegisterBlock { xtl_ext_ctr: XTL_EXT_CTR, sar_i2c_io: SAR_I2C_IO, touch_ctrl: TOUCH_CTRL, - _reserved59: [u8; 0x0110], + _reserved38: [u8; 0x0110], date: DATE, } impl RegisterBlock { @@ -115,115 +94,16 @@ impl RegisterBlock { pub const fn in_(&self) -> &IN { &self.in_ } - #[doc = "0x28 - configure RTC GPIO0"] + #[doc = "0x28..0x80 - configure RTC GPIO%s"] #[inline(always)] - pub const fn pin0(&self) -> &PIN0 { - &self.pin0 + pub const fn pin(&self, n: usize) -> &PIN { + &self.pin[n] } - #[doc = "0x2c - configure RTC GPIO1"] + #[doc = "Iterator for array of:"] + #[doc = "0x28..0x80 - configure RTC GPIO%s"] #[inline(always)] - pub const fn pin1(&self) -> &PIN1 { - &self.pin1 - } - #[doc = "0x30 - configure RTC GPIO2"] - #[inline(always)] - pub const fn pin2(&self) -> &PIN2 { - &self.pin2 - } - #[doc = "0x34 - configure RTC GPIO3"] - #[inline(always)] - pub const fn pin3(&self) -> &PIN3 { - &self.pin3 - } - #[doc = "0x38 - configure RTC GPIO4"] - #[inline(always)] - pub const fn pin4(&self) -> &PIN4 { - &self.pin4 - } - #[doc = "0x3c - configure RTC GPIO5"] - #[inline(always)] - pub const fn pin5(&self) -> &PIN5 { - &self.pin5 - } - #[doc = "0x40 - configure RTC GPIO6"] - #[inline(always)] - pub const fn pin6(&self) -> &PIN6 { - &self.pin6 - } - #[doc = "0x44 - configure RTC GPIO7"] - #[inline(always)] - pub const fn pin7(&self) -> &PIN7 { - &self.pin7 - } - #[doc = "0x48 - configure RTC GPIO8"] - #[inline(always)] - pub const fn pin8(&self) -> &PIN8 { - &self.pin8 - } - #[doc = "0x4c - configure RTC GPIO9"] - #[inline(always)] - pub const fn pin9(&self) -> &PIN9 { - &self.pin9 - } - #[doc = "0x50 - configure RTC GPIO10"] - #[inline(always)] - pub const fn pin10(&self) -> &PIN10 { - &self.pin10 - } - #[doc = "0x54 - configure RTC GPIO11"] - #[inline(always)] - pub const fn pin11(&self) -> &PIN11 { - &self.pin11 - } - #[doc = "0x58 - configure RTC GPIO12"] - #[inline(always)] - pub const fn pin12(&self) -> &PIN12 { - &self.pin12 - } - #[doc = "0x5c - configure RTC GPIO13"] - #[inline(always)] - pub const fn pin13(&self) -> &PIN13 { - &self.pin13 - } - #[doc = "0x60 - configure RTC GPIO14"] - #[inline(always)] - pub const fn pin14(&self) -> &PIN14 { - &self.pin14 - } - #[doc = "0x64 - configure RTC GPIO15"] - #[inline(always)] - pub const fn pin15(&self) -> &PIN15 { - &self.pin15 - } - #[doc = "0x68 - configure RTC GPIO16"] - #[inline(always)] - pub const fn pin16(&self) -> &PIN16 { - &self.pin16 - } - #[doc = "0x6c - configure RTC GPIO17"] - #[inline(always)] - pub const fn pin17(&self) -> &PIN17 { - &self.pin17 - } - #[doc = "0x70 - configure RTC GPIO18"] - #[inline(always)] - pub const fn pin18(&self) -> &PIN18 { - &self.pin18 - } - #[doc = "0x74 - configure RTC GPIO19"] - #[inline(always)] - pub const fn pin19(&self) -> &PIN19 { - &self.pin19 - } - #[doc = "0x78 - configure RTC GPIO20"] - #[inline(always)] - pub const fn pin20(&self) -> &PIN20 { - &self.pin20 - } - #[doc = "0x7c - configure RTC GPIO21"] - #[inline(always)] - pub const fn pin21(&self) -> &PIN21 { - &self.pin21 + pub fn pin_iter(&self) -> impl Iterator { + self.pin.iter() } #[doc = "0x80 - configure rtc debug"] #[inline(always)] @@ -406,94 +286,10 @@ pub mod status_w1tc; pub type IN = crate::Reg; #[doc = "RTC GPIO input data"] pub mod in_; -#[doc = "PIN0 (rw) register accessor: configure RTC GPIO0\n\nYou can [`read`](crate::Reg::read) this register and get [`pin0::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin0::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin0`] module"] -pub type PIN0 = crate::Reg; -#[doc = "configure RTC GPIO0"] -pub mod pin0; -#[doc = "PIN1 (rw) register accessor: configure RTC GPIO1\n\nYou can [`read`](crate::Reg::read) this register and get [`pin1::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin1::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin1`] module"] -pub type PIN1 = crate::Reg; -#[doc = "configure RTC GPIO1"] -pub mod pin1; -#[doc = "PIN2 (rw) register accessor: configure RTC GPIO2\n\nYou can [`read`](crate::Reg::read) this register and get [`pin2::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin2::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin2`] module"] -pub type PIN2 = crate::Reg; -#[doc = "configure RTC GPIO2"] -pub mod pin2; -#[doc = "PIN3 (rw) register accessor: configure RTC GPIO3\n\nYou can [`read`](crate::Reg::read) this register and get [`pin3::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin3::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin3`] module"] -pub type PIN3 = crate::Reg; -#[doc = "configure RTC GPIO3"] -pub mod pin3; -#[doc = "PIN4 (rw) register accessor: configure RTC GPIO4\n\nYou can [`read`](crate::Reg::read) this register and get [`pin4::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin4::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin4`] module"] -pub type PIN4 = crate::Reg; -#[doc = "configure RTC GPIO4"] -pub mod pin4; -#[doc = "PIN5 (rw) register accessor: configure RTC GPIO5\n\nYou can [`read`](crate::Reg::read) this register and get [`pin5::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin5::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin5`] module"] -pub type PIN5 = crate::Reg; -#[doc = "configure RTC GPIO5"] -pub mod pin5; -#[doc = "PIN6 (rw) register accessor: configure RTC GPIO6\n\nYou can [`read`](crate::Reg::read) this register and get [`pin6::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin6::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin6`] module"] -pub type PIN6 = crate::Reg; -#[doc = "configure RTC GPIO6"] -pub mod pin6; -#[doc = "PIN7 (rw) register accessor: configure RTC GPIO7\n\nYou can [`read`](crate::Reg::read) this register and get [`pin7::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin7::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin7`] module"] -pub type PIN7 = crate::Reg; -#[doc = "configure RTC GPIO7"] -pub mod pin7; -#[doc = "PIN8 (rw) register accessor: configure RTC GPIO8\n\nYou can [`read`](crate::Reg::read) this register and get [`pin8::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin8::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin8`] module"] -pub type PIN8 = crate::Reg; -#[doc = "configure RTC GPIO8"] -pub mod pin8; -#[doc = "PIN9 (rw) register accessor: configure RTC GPIO9\n\nYou can [`read`](crate::Reg::read) this register and get [`pin9::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin9::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin9`] module"] -pub type PIN9 = crate::Reg; -#[doc = "configure RTC GPIO9"] -pub mod pin9; -#[doc = "PIN10 (rw) register accessor: configure RTC GPIO10\n\nYou can [`read`](crate::Reg::read) this register and get [`pin10::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin10::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin10`] module"] -pub type PIN10 = crate::Reg; -#[doc = "configure RTC GPIO10"] -pub mod pin10; -#[doc = "PIN11 (rw) register accessor: configure RTC GPIO11\n\nYou can [`read`](crate::Reg::read) this register and get [`pin11::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin11::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin11`] module"] -pub type PIN11 = crate::Reg; -#[doc = "configure RTC GPIO11"] -pub mod pin11; -#[doc = "PIN12 (rw) register accessor: configure RTC GPIO12\n\nYou can [`read`](crate::Reg::read) this register and get [`pin12::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin12::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin12`] module"] -pub type PIN12 = crate::Reg; -#[doc = "configure RTC GPIO12"] -pub mod pin12; -#[doc = "PIN13 (rw) register accessor: configure RTC GPIO13\n\nYou can [`read`](crate::Reg::read) this register and get [`pin13::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin13::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin13`] module"] -pub type PIN13 = crate::Reg; -#[doc = "configure RTC GPIO13"] -pub mod pin13; -#[doc = "PIN14 (rw) register accessor: configure RTC GPIO14\n\nYou can [`read`](crate::Reg::read) this register and get [`pin14::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin14::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin14`] module"] -pub type PIN14 = crate::Reg; -#[doc = "configure RTC GPIO14"] -pub mod pin14; -#[doc = "PIN15 (rw) register accessor: configure RTC GPIO15\n\nYou can [`read`](crate::Reg::read) this register and get [`pin15::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin15::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin15`] module"] -pub type PIN15 = crate::Reg; -#[doc = "configure RTC GPIO15"] -pub mod pin15; -#[doc = "PIN16 (rw) register accessor: configure RTC GPIO16\n\nYou can [`read`](crate::Reg::read) this register and get [`pin16::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin16::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin16`] module"] -pub type PIN16 = crate::Reg; -#[doc = "configure RTC GPIO16"] -pub mod pin16; -#[doc = "PIN17 (rw) register accessor: configure RTC GPIO17\n\nYou can [`read`](crate::Reg::read) this register and get [`pin17::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin17::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin17`] module"] -pub type PIN17 = crate::Reg; -#[doc = "configure RTC GPIO17"] -pub mod pin17; -#[doc = "PIN18 (rw) register accessor: configure RTC GPIO18\n\nYou can [`read`](crate::Reg::read) this register and get [`pin18::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin18::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin18`] module"] -pub type PIN18 = crate::Reg; -#[doc = "configure RTC GPIO18"] -pub mod pin18; -#[doc = "PIN19 (rw) register accessor: configure RTC GPIO19\n\nYou can [`read`](crate::Reg::read) this register and get [`pin19::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin19::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin19`] module"] -pub type PIN19 = crate::Reg; -#[doc = "configure RTC GPIO19"] -pub mod pin19; -#[doc = "PIN20 (rw) register accessor: configure RTC GPIO20\n\nYou can [`read`](crate::Reg::read) this register and get [`pin20::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin20::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin20`] module"] -pub type PIN20 = crate::Reg; -#[doc = "configure RTC GPIO20"] -pub mod pin20; -#[doc = "PIN21 (rw) register accessor: configure RTC GPIO21\n\nYou can [`read`](crate::Reg::read) this register and get [`pin21::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin21::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin21`] module"] -pub type PIN21 = crate::Reg; -#[doc = "configure RTC GPIO21"] -pub mod pin21; +#[doc = "PIN (rw) register accessor: configure RTC GPIO%s\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pin`] module"] +pub type PIN = crate::Reg; +#[doc = "configure RTC GPIO%s"] +pub mod pin; #[doc = "RTC_DEBUG_SEL (rw) register accessor: configure rtc debug\n\nYou can [`read`](crate::Reg::read) this register and get [`rtc_debug_sel::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rtc_debug_sel::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@rtc_debug_sel`] module"] pub type RTC_DEBUG_SEL = crate::Reg; #[doc = "configure rtc debug"] diff --git a/esp32s3-ulp/src/rtc_io/pin0.rs b/esp32s3-ulp/src/rtc_io/pin.rs similarity index 73% rename from esp32s3-ulp/src/rtc_io/pin0.rs rename to esp32s3-ulp/src/rtc_io/pin.rs index 1de2c50985..135c9e52b6 100644 --- a/esp32s3-ulp/src/rtc_io/pin0.rs +++ b/esp32s3-ulp/src/rtc_io/pin.rs @@ -1,7 +1,7 @@ -#[doc = "Register `PIN0` reader"] -pub type R = crate::R; -#[doc = "Register `PIN0` writer"] -pub type W = crate::W; +#[doc = "Register `PIN%s` reader"] +pub type R = crate::R; +#[doc = "Register `PIN%s` writer"] +pub type W = crate::W; #[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] pub type PAD_DRIVER_R = crate::BitReader; #[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] @@ -34,7 +34,7 @@ impl R { #[cfg(feature = "impl-register-debug")] impl core::fmt::Debug for R { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN0") + f.debug_struct("PIN") .field("pad_driver", &self.pad_driver()) .field("int_type", &self.int_type()) .field("wakeup_enable", &self.wakeup_enable()) @@ -44,30 +44,30 @@ impl core::fmt::Debug for R { impl W { #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN0_SPEC> { + pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN_SPEC> { PAD_DRIVER_W::new(self, 2) } #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN0_SPEC> { + pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN_SPEC> { INT_TYPE_W::new(self, 7) } #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN0_SPEC> { + pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN_SPEC> { WAKEUP_ENABLE_W::new(self, 10) } } -#[doc = "configure RTC GPIO0\n\nYou can [`read`](crate::Reg::read) this register and get [`pin0::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin0::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN0_SPEC; -impl crate::RegisterSpec for PIN0_SPEC { +#[doc = "configure RTC GPIO%s\n\nYou can [`read`](crate::Reg::read) this register and get [`pin::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] +pub struct PIN_SPEC; +impl crate::RegisterSpec for PIN_SPEC { type Ux = u32; } -#[doc = "`read()` method returns [`pin0::R`](R) reader structure"] -impl crate::Readable for PIN0_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin0::W`](W) writer structure"] -impl crate::Writable for PIN0_SPEC { +#[doc = "`read()` method returns [`pin::R`](R) reader structure"] +impl crate::Readable for PIN_SPEC {} +#[doc = "`write(|w| ..)` method takes [`pin::W`](W) writer structure"] +impl crate::Writable for PIN_SPEC { type Safety = crate::Unsafe; } -#[doc = "`reset()` method sets PIN0 to value 0"] -impl crate::Resettable for PIN0_SPEC {} +#[doc = "`reset()` method sets PIN%s to value 0"] +impl crate::Resettable for PIN_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin1.rs b/esp32s3-ulp/src/rtc_io/pin1.rs deleted file mode 100644 index f462c54762..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin1.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN1` reader"] -pub type R = crate::R; -#[doc = "Register `PIN1` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN1") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN1_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN1_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN1_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO1\n\nYou can [`read`](crate::Reg::read) this register and get [`pin1::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin1::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN1_SPEC; -impl crate::RegisterSpec for PIN1_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin1::R`](R) reader structure"] -impl crate::Readable for PIN1_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin1::W`](W) writer structure"] -impl crate::Writable for PIN1_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN1 to value 0"] -impl crate::Resettable for PIN1_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin10.rs b/esp32s3-ulp/src/rtc_io/pin10.rs deleted file mode 100644 index 211d1bfaf0..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin10.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN10` reader"] -pub type R = crate::R; -#[doc = "Register `PIN10` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN10") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN10_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN10_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN10_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO10\n\nYou can [`read`](crate::Reg::read) this register and get [`pin10::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin10::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN10_SPEC; -impl crate::RegisterSpec for PIN10_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin10::R`](R) reader structure"] -impl crate::Readable for PIN10_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin10::W`](W) writer structure"] -impl crate::Writable for PIN10_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN10 to value 0"] -impl crate::Resettable for PIN10_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin11.rs b/esp32s3-ulp/src/rtc_io/pin11.rs deleted file mode 100644 index 87cc9e69cb..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin11.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN11` reader"] -pub type R = crate::R; -#[doc = "Register `PIN11` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN11") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN11_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN11_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN11_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO11\n\nYou can [`read`](crate::Reg::read) this register and get [`pin11::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin11::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN11_SPEC; -impl crate::RegisterSpec for PIN11_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin11::R`](R) reader structure"] -impl crate::Readable for PIN11_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin11::W`](W) writer structure"] -impl crate::Writable for PIN11_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN11 to value 0"] -impl crate::Resettable for PIN11_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin12.rs b/esp32s3-ulp/src/rtc_io/pin12.rs deleted file mode 100644 index 9a0168e5a3..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin12.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN12` reader"] -pub type R = crate::R; -#[doc = "Register `PIN12` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN12") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN12_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN12_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN12_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO12\n\nYou can [`read`](crate::Reg::read) this register and get [`pin12::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin12::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN12_SPEC; -impl crate::RegisterSpec for PIN12_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin12::R`](R) reader structure"] -impl crate::Readable for PIN12_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin12::W`](W) writer structure"] -impl crate::Writable for PIN12_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN12 to value 0"] -impl crate::Resettable for PIN12_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin13.rs b/esp32s3-ulp/src/rtc_io/pin13.rs deleted file mode 100644 index 969aabb2e3..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin13.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN13` reader"] -pub type R = crate::R; -#[doc = "Register `PIN13` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN13") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN13_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN13_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN13_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO13\n\nYou can [`read`](crate::Reg::read) this register and get [`pin13::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin13::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN13_SPEC; -impl crate::RegisterSpec for PIN13_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin13::R`](R) reader structure"] -impl crate::Readable for PIN13_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin13::W`](W) writer structure"] -impl crate::Writable for PIN13_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN13 to value 0"] -impl crate::Resettable for PIN13_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin14.rs b/esp32s3-ulp/src/rtc_io/pin14.rs deleted file mode 100644 index 0f7299e62d..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin14.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN14` reader"] -pub type R = crate::R; -#[doc = "Register `PIN14` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN14") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN14_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN14_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN14_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO14\n\nYou can [`read`](crate::Reg::read) this register and get [`pin14::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin14::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN14_SPEC; -impl crate::RegisterSpec for PIN14_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin14::R`](R) reader structure"] -impl crate::Readable for PIN14_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin14::W`](W) writer structure"] -impl crate::Writable for PIN14_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN14 to value 0"] -impl crate::Resettable for PIN14_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin15.rs b/esp32s3-ulp/src/rtc_io/pin15.rs deleted file mode 100644 index 591c7d704f..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin15.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN15` reader"] -pub type R = crate::R; -#[doc = "Register `PIN15` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN15") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN15_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN15_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN15_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO15\n\nYou can [`read`](crate::Reg::read) this register and get [`pin15::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin15::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN15_SPEC; -impl crate::RegisterSpec for PIN15_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin15::R`](R) reader structure"] -impl crate::Readable for PIN15_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin15::W`](W) writer structure"] -impl crate::Writable for PIN15_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN15 to value 0"] -impl crate::Resettable for PIN15_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin16.rs b/esp32s3-ulp/src/rtc_io/pin16.rs deleted file mode 100644 index c552522b4d..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin16.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN16` reader"] -pub type R = crate::R; -#[doc = "Register `PIN16` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN16") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN16_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN16_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN16_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO16\n\nYou can [`read`](crate::Reg::read) this register and get [`pin16::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin16::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN16_SPEC; -impl crate::RegisterSpec for PIN16_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin16::R`](R) reader structure"] -impl crate::Readable for PIN16_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin16::W`](W) writer structure"] -impl crate::Writable for PIN16_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN16 to value 0"] -impl crate::Resettable for PIN16_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin17.rs b/esp32s3-ulp/src/rtc_io/pin17.rs deleted file mode 100644 index 669160df36..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin17.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN17` reader"] -pub type R = crate::R; -#[doc = "Register `PIN17` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN17") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN17_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN17_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN17_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO17\n\nYou can [`read`](crate::Reg::read) this register and get [`pin17::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin17::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN17_SPEC; -impl crate::RegisterSpec for PIN17_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin17::R`](R) reader structure"] -impl crate::Readable for PIN17_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin17::W`](W) writer structure"] -impl crate::Writable for PIN17_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN17 to value 0"] -impl crate::Resettable for PIN17_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin18.rs b/esp32s3-ulp/src/rtc_io/pin18.rs deleted file mode 100644 index 56c5c06732..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin18.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN18` reader"] -pub type R = crate::R; -#[doc = "Register `PIN18` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN18") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN18_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN18_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN18_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO18\n\nYou can [`read`](crate::Reg::read) this register and get [`pin18::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin18::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN18_SPEC; -impl crate::RegisterSpec for PIN18_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin18::R`](R) reader structure"] -impl crate::Readable for PIN18_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin18::W`](W) writer structure"] -impl crate::Writable for PIN18_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN18 to value 0"] -impl crate::Resettable for PIN18_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin19.rs b/esp32s3-ulp/src/rtc_io/pin19.rs deleted file mode 100644 index 8eb4a20b6d..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin19.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN19` reader"] -pub type R = crate::R; -#[doc = "Register `PIN19` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN19") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN19_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN19_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN19_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO19\n\nYou can [`read`](crate::Reg::read) this register and get [`pin19::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin19::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN19_SPEC; -impl crate::RegisterSpec for PIN19_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin19::R`](R) reader structure"] -impl crate::Readable for PIN19_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin19::W`](W) writer structure"] -impl crate::Writable for PIN19_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN19 to value 0"] -impl crate::Resettable for PIN19_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin2.rs b/esp32s3-ulp/src/rtc_io/pin2.rs deleted file mode 100644 index 5da67045b8..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin2.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN2` reader"] -pub type R = crate::R; -#[doc = "Register `PIN2` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN2") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN2_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN2_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN2_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO2\n\nYou can [`read`](crate::Reg::read) this register and get [`pin2::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin2::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN2_SPEC; -impl crate::RegisterSpec for PIN2_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin2::R`](R) reader structure"] -impl crate::Readable for PIN2_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin2::W`](W) writer structure"] -impl crate::Writable for PIN2_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN2 to value 0"] -impl crate::Resettable for PIN2_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin20.rs b/esp32s3-ulp/src/rtc_io/pin20.rs deleted file mode 100644 index 046a25c12c..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin20.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN20` reader"] -pub type R = crate::R; -#[doc = "Register `PIN20` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN20") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN20_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN20_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN20_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO20\n\nYou can [`read`](crate::Reg::read) this register and get [`pin20::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin20::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN20_SPEC; -impl crate::RegisterSpec for PIN20_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin20::R`](R) reader structure"] -impl crate::Readable for PIN20_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin20::W`](W) writer structure"] -impl crate::Writable for PIN20_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN20 to value 0"] -impl crate::Resettable for PIN20_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin21.rs b/esp32s3-ulp/src/rtc_io/pin21.rs deleted file mode 100644 index 524571f663..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin21.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN21` reader"] -pub type R = crate::R; -#[doc = "Register `PIN21` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN21") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN21_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN21_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN21_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO21\n\nYou can [`read`](crate::Reg::read) this register and get [`pin21::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin21::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN21_SPEC; -impl crate::RegisterSpec for PIN21_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin21::R`](R) reader structure"] -impl crate::Readable for PIN21_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin21::W`](W) writer structure"] -impl crate::Writable for PIN21_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN21 to value 0"] -impl crate::Resettable for PIN21_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin3.rs b/esp32s3-ulp/src/rtc_io/pin3.rs deleted file mode 100644 index f757e82500..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin3.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN3` reader"] -pub type R = crate::R; -#[doc = "Register `PIN3` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN3") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN3_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN3_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN3_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO3\n\nYou can [`read`](crate::Reg::read) this register and get [`pin3::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin3::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN3_SPEC; -impl crate::RegisterSpec for PIN3_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin3::R`](R) reader structure"] -impl crate::Readable for PIN3_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin3::W`](W) writer structure"] -impl crate::Writable for PIN3_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN3 to value 0"] -impl crate::Resettable for PIN3_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin4.rs b/esp32s3-ulp/src/rtc_io/pin4.rs deleted file mode 100644 index 32dd2d6adb..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin4.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN4` reader"] -pub type R = crate::R; -#[doc = "Register `PIN4` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN4") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN4_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN4_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN4_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO4\n\nYou can [`read`](crate::Reg::read) this register and get [`pin4::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin4::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN4_SPEC; -impl crate::RegisterSpec for PIN4_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin4::R`](R) reader structure"] -impl crate::Readable for PIN4_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin4::W`](W) writer structure"] -impl crate::Writable for PIN4_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN4 to value 0"] -impl crate::Resettable for PIN4_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin5.rs b/esp32s3-ulp/src/rtc_io/pin5.rs deleted file mode 100644 index f7e154449c..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin5.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN5` reader"] -pub type R = crate::R; -#[doc = "Register `PIN5` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN5") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN5_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN5_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN5_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO5\n\nYou can [`read`](crate::Reg::read) this register and get [`pin5::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin5::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN5_SPEC; -impl crate::RegisterSpec for PIN5_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin5::R`](R) reader structure"] -impl crate::Readable for PIN5_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin5::W`](W) writer structure"] -impl crate::Writable for PIN5_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN5 to value 0"] -impl crate::Resettable for PIN5_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin6.rs b/esp32s3-ulp/src/rtc_io/pin6.rs deleted file mode 100644 index 36f93f2a8a..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin6.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN6` reader"] -pub type R = crate::R; -#[doc = "Register `PIN6` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN6") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN6_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN6_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN6_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO6\n\nYou can [`read`](crate::Reg::read) this register and get [`pin6::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin6::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN6_SPEC; -impl crate::RegisterSpec for PIN6_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin6::R`](R) reader structure"] -impl crate::Readable for PIN6_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin6::W`](W) writer structure"] -impl crate::Writable for PIN6_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN6 to value 0"] -impl crate::Resettable for PIN6_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin7.rs b/esp32s3-ulp/src/rtc_io/pin7.rs deleted file mode 100644 index f3cb22f2e2..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin7.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN7` reader"] -pub type R = crate::R; -#[doc = "Register `PIN7` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN7") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN7_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN7_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN7_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO7\n\nYou can [`read`](crate::Reg::read) this register and get [`pin7::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin7::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN7_SPEC; -impl crate::RegisterSpec for PIN7_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin7::R`](R) reader structure"] -impl crate::Readable for PIN7_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin7::W`](W) writer structure"] -impl crate::Writable for PIN7_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN7 to value 0"] -impl crate::Resettable for PIN7_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin8.rs b/esp32s3-ulp/src/rtc_io/pin8.rs deleted file mode 100644 index 2c26d026ba..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin8.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN8` reader"] -pub type R = crate::R; -#[doc = "Register `PIN8` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN8") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN8_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN8_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN8_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO8\n\nYou can [`read`](crate::Reg::read) this register and get [`pin8::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin8::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN8_SPEC; -impl crate::RegisterSpec for PIN8_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin8::R`](R) reader structure"] -impl crate::Readable for PIN8_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin8::W`](W) writer structure"] -impl crate::Writable for PIN8_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN8 to value 0"] -impl crate::Resettable for PIN8_SPEC {} diff --git a/esp32s3-ulp/src/rtc_io/pin9.rs b/esp32s3-ulp/src/rtc_io/pin9.rs deleted file mode 100644 index afc50e76b6..0000000000 --- a/esp32s3-ulp/src/rtc_io/pin9.rs +++ /dev/null @@ -1,73 +0,0 @@ -#[doc = "Register `PIN9` reader"] -pub type R = crate::R; -#[doc = "Register `PIN9` writer"] -pub type W = crate::W; -#[doc = "Field `PAD_DRIVER` reader - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_R = crate::BitReader; -#[doc = "Field `PAD_DRIVER` writer - if set to 0: normal output, if set to 1: open drain"] -pub type PAD_DRIVER_W<'a, REG> = crate::BitWriter<'a, REG>; -#[doc = "Field `INT_TYPE` reader - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_R = crate::FieldReader; -#[doc = "Field `INT_TYPE` writer - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] -pub type INT_TYPE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>; -#[doc = "Field `WAKEUP_ENABLE` reader - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_R = crate::BitReader; -#[doc = "Field `WAKEUP_ENABLE` writer - RTC GPIO wakeup enable bit"] -pub type WAKEUP_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG>; -impl R { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&self) -> PAD_DRIVER_R { - PAD_DRIVER_R::new(((self.bits >> 2) & 1) != 0) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&self) -> INT_TYPE_R { - INT_TYPE_R::new(((self.bits >> 7) & 7) as u8) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&self) -> WAKEUP_ENABLE_R { - WAKEUP_ENABLE_R::new(((self.bits >> 10) & 1) != 0) - } -} -#[cfg(feature = "impl-register-debug")] -impl core::fmt::Debug for R { - fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { - f.debug_struct("PIN9") - .field("pad_driver", &self.pad_driver()) - .field("int_type", &self.int_type()) - .field("wakeup_enable", &self.wakeup_enable()) - .finish() - } -} -impl W { - #[doc = "Bit 2 - if set to 0: normal output, if set to 1: open drain"] - #[inline(always)] - pub fn pad_driver(&mut self) -> PAD_DRIVER_W<'_, PIN9_SPEC> { - PAD_DRIVER_W::new(self, 2) - } - #[doc = "Bits 7:9 - if set to 0: GPIO interrupt disable, if set to 1: rising edge trigger, if set to 2: falling edge trigger, if set to 3: any edge trigger, if set to 4: low level trigger, if set to 5: high level trigger"] - #[inline(always)] - pub fn int_type(&mut self) -> INT_TYPE_W<'_, PIN9_SPEC> { - INT_TYPE_W::new(self, 7) - } - #[doc = "Bit 10 - RTC GPIO wakeup enable bit"] - #[inline(always)] - pub fn wakeup_enable(&mut self) -> WAKEUP_ENABLE_W<'_, PIN9_SPEC> { - WAKEUP_ENABLE_W::new(self, 10) - } -} -#[doc = "configure RTC GPIO9\n\nYou can [`read`](crate::Reg::read) this register and get [`pin9::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pin9::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."] -pub struct PIN9_SPEC; -impl crate::RegisterSpec for PIN9_SPEC { - type Ux = u32; -} -#[doc = "`read()` method returns [`pin9::R`](R) reader structure"] -impl crate::Readable for PIN9_SPEC {} -#[doc = "`write(|w| ..)` method takes [`pin9::W`](W) writer structure"] -impl crate::Writable for PIN9_SPEC { - type Safety = crate::Unsafe; -} -#[doc = "`reset()` method sets PIN9 to value 0"] -impl crate::Resettable for PIN9_SPEC {} diff --git a/esp32s3-ulp/svd/patches/esp32s3-ulp.yaml b/esp32s3-ulp/svd/patches/esp32s3-ulp.yaml index d9a8e381a9..9b307672a4 100644 --- a/esp32s3-ulp/svd/patches/esp32s3-ulp.yaml +++ b/esp32s3-ulp/svd/patches/esp32s3-ulp.yaml @@ -11,14 +11,14 @@ RTC_CNTL: RTC_IO: _strip: "RTC_GPIO_" - "*": _strip: "RTC_" - OUT_W1TC: _strip: "GPIO_" OUT_W1TS: _strip: "GPIO_" + _array: + PIN*: {} RTC_I2C: CMD*: From cba62523183b82fc4460c704bb361ff9ba7c3496 Mon Sep 17 00:00:00 2001 From: Leigh Oliver Date: Sun, 26 Apr 2026 11:56:35 +1000 Subject: [PATCH 4/4] Work-around skip_peripherals_struct config for LP cores. Fixup ESP32C6-LP interrupt numbers to match TRM --- esp32c6-lp/build.rs | 5 +-- esp32c6-lp/device.x | 13 +++----- esp32c6-lp/src/interrupt.rs | 39 +++++++++------------- esp32c6-lp/src/lib.rs | 49 ++++++++++------------------ esp32c6-lp/src/lp_tee/m_mode_ctrl.rs | 2 +- esp32c6-lp/svd/esp32c6-lp.base.svd | 34 +++++++------------ esp32c6-lp/svd/patches/_pmu.yml | 6 ++++ esp32s2-ulp/build.rs | 5 +-- esp32s2-ulp/src/interrupt.rs | 18 +++++----- esp32s2-ulp/src/lib.rs | 2 +- esp32s3-ulp/build.rs | 5 +-- esp32s3-ulp/src/interrupt.rs | 24 +++++++------- esp32s3-ulp/src/lib.rs | 2 +- xtask/src/main.rs | 5 ++- 14 files changed, 85 insertions(+), 124 deletions(-) diff --git a/esp32c6-lp/build.rs b/esp32c6-lp/build.rs index d0781acdb6..a742427679 100644 --- a/esp32c6-lp/build.rs +++ b/esp32c6-lp/build.rs @@ -1,8 +1,5 @@ #![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; +use std::{env, fs::File, io::Write, path::PathBuf}; fn main() { if env::var_os("CARGO_FEATURE_RT").is_some() { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); diff --git a/esp32c6-lp/device.x b/esp32c6-lp/device.x index 431ccd05ea..d162c48439 100644 --- a/esp32c6-lp/device.x +++ b/esp32c6-lp/device.x @@ -1,9 +1,6 @@ -PROVIDE(LP_TIMER = DefaultHandler); -PROVIDE(PMU = DefaultHandler); -PROVIDE(LP_UART = DefaultHandler); -PROVIDE(LP_I2C = DefaultHandler); -PROVIDE(LP_WDT = DefaultHandler); -PROVIDE(LP_PERI_TIMEOUT = DefaultHandler); -PROVIDE(LP_APM_M0 = DefaultHandler); -PROVIDE(LP_APM_M1 = DefaultHandler); +PROVIDE(LP_IO_INT = DefaultHandler); +PROVIDE(LP_I2C_INT = DefaultHandler); +PROVIDE(LP_UART_INT = DefaultHandler); +PROVIDE(LP_TIMER_INT = DefaultHandler); +PROVIDE(PMU_LP_INT = DefaultHandler); diff --git a/esp32c6-lp/src/interrupt.rs b/esp32c6-lp/src/interrupt.rs index f810fadc60..e75689f38e 100644 --- a/esp32c6-lp/src/interrupt.rs +++ b/esp32c6-lp/src/interrupt.rs @@ -3,22 +3,16 @@ #[derive(Copy, Clone, Debug, PartialEq, Eq)] #[repr(u16)] pub enum Interrupt { - #[doc = "7 - LP_TIMER"] - LP_TIMER = 7, - #[doc = "13 - PMU"] - PMU = 13, - #[doc = "16 - LP_UART"] - LP_UART = 16, - #[doc = "17 - LP_I2C"] - LP_I2C = 17, - #[doc = "18 - LP_WDT"] - LP_WDT = 18, - #[doc = "19 - LP_PERI_TIMEOUT"] - LP_PERI_TIMEOUT = 19, - #[doc = "20 - LP_APM_M0"] - LP_APM_M0 = 20, - #[doc = "21 - LP_APM_M1"] - LP_APM_M1 = 21, + #[doc = "0 - LP_IO_INT"] + LP_IO_INT = 0, + #[doc = "1 - LP_I2C_INT"] + LP_I2C_INT = 1, + #[doc = "2 - LP_UART_INT"] + LP_UART_INT = 2, + #[doc = "3 - LP_TIMER_INT"] + LP_TIMER_INT = 3, + #[doc = "5 - PMU_LP_INT"] + PMU_LP_INT = 5, } #[doc = r" TryFromInterruptError"] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -29,14 +23,11 @@ impl Interrupt { #[inline] pub fn try_from(value: u8) -> Result { match value { - 7 => Ok(Interrupt::LP_TIMER), - 13 => Ok(Interrupt::PMU), - 16 => Ok(Interrupt::LP_UART), - 17 => Ok(Interrupt::LP_I2C), - 18 => Ok(Interrupt::LP_WDT), - 19 => Ok(Interrupt::LP_PERI_TIMEOUT), - 20 => Ok(Interrupt::LP_APM_M0), - 21 => Ok(Interrupt::LP_APM_M1), + 0 => Ok(Interrupt::LP_IO_INT), + 1 => Ok(Interrupt::LP_I2C_INT), + 2 => Ok(Interrupt::LP_UART_INT), + 3 => Ok(Interrupt::LP_TIMER_INT), + 5 => Ok(Interrupt::PMU_LP_INT), _ => Err(TryFromInterruptError(())), } } diff --git a/esp32c6-lp/src/lib.rs b/esp32c6-lp/src/lib.rs index 7e494b41b7..973ce56286 100644 --- a/esp32c6-lp/src/lib.rs +++ b/esp32c6-lp/src/lib.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API for ESP32-C6-LP microcontrollers (generated using svd2rust v0.37.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![doc = "Peripheral access API for ESP32-C6-LP microcontrollers (generated using svd2rust v0.37.1 (f74f0b3 2026-04-17))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![allow(non_camel_case_types)] #![allow(non_snake_case)] #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] @@ -12,14 +12,11 @@ use generic::*; pub mod generic; #[cfg(feature = "rt")] extern "C" { - fn LP_TIMER(); - fn PMU(); - fn LP_UART(); - fn LP_I2C(); - fn LP_WDT(); - fn LP_PERI_TIMEOUT(); - fn LP_APM_M0(); - fn LP_APM_M1(); + fn LP_IO_INT(); + fn LP_I2C_INT(); + fn LP_UART_INT(); + fn LP_TIMER_INT(); + fn PMU_LP_INT(); } #[doc(hidden)] #[repr(C)] @@ -31,34 +28,22 @@ pub union Vector { #[doc(hidden)] #[link_section = ".rwtext"] #[no_mangle] -pub static __EXTERNAL_INTERRUPTS: [Vector; 22] = [ - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: LP_TIMER }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: PMU }, - Vector { _reserved: 0 }, - Vector { _reserved: 0 }, - Vector { _handler: LP_UART }, - Vector { _handler: LP_I2C }, - Vector { _handler: LP_WDT }, +pub static __EXTERNAL_INTERRUPTS: [Vector; 6] = [ Vector { - _handler: LP_PERI_TIMEOUT, + _handler: LP_IO_INT, }, Vector { - _handler: LP_APM_M0, + _handler: LP_I2C_INT, }, Vector { - _handler: LP_APM_M1, + _handler: LP_UART_INT, + }, + Vector { + _handler: LP_TIMER_INT, + }, + Vector { _reserved: 0 }, + Vector { + _handler: PMU_LP_INT, }, ]; #[doc(hidden)] diff --git a/esp32c6-lp/src/lp_tee/m_mode_ctrl.rs b/esp32c6-lp/src/lp_tee/m_mode_ctrl.rs index 70815000fa..c9f435368d 100644 --- a/esp32c6-lp/src/lp_tee/m_mode_ctrl.rs +++ b/esp32c6-lp/src/lp_tee/m_mode_ctrl.rs @@ -8,7 +8,7 @@ pub type W = crate::W; #[repr(u8)] pub enum SECURITY_MODE { #[doc = "0: Tee mode"] - Tee = 0, + Tee = 0, #[doc = "1: Ree0 mode"] Ree0 = 1, #[doc = "2: Ree1 mode"] diff --git a/esp32c6-lp/svd/esp32c6-lp.base.svd b/esp32c6-lp/svd/esp32c6-lp.base.svd index 84bf13a487..637fdd5034 100644 --- a/esp32c6-lp/svd/esp32c6-lp.base.svd +++ b/esp32c6-lp/svd/esp32c6-lp.base.svd @@ -44,8 +44,8 @@ registers - LP_I2C - 17 + LP_I2C_INT + 1 @@ -1368,10 +1368,6 @@ Information. 0x28 registers - - LP_PERI_TIMEOUT - 19 - CLK_EN @@ -2456,14 +2452,6 @@ Information. 0x64 registers - - LP_APM_M0 - 20 - - - LP_APM_M1 - 21 - REGION_FILTER_EN @@ -3709,6 +3697,10 @@ Information. 0x7C registers + + LP_IO_INT + 0 + OUT_DATA @@ -5141,8 +5133,8 @@ Information. registers - LP_TIMER - 7 + LP_TIMER_INT + 3 @@ -5542,8 +5534,8 @@ Information. registers - LP_UART - 16 + LP_UART_INT + 2 @@ -6998,10 +6990,6 @@ Information. 0x38 registers - - LP_WDT - 18 - CONFIG0 @@ -7377,4 +7365,4 @@ Information. - \ No newline at end of file + diff --git a/esp32c6-lp/svd/patches/_pmu.yml b/esp32c6-lp/svd/patches/_pmu.yml index a8340b85e3..0bb2a84dec 100644 --- a/esp32c6-lp/svd/patches/_pmu.yml +++ b/esp32c6-lp/svd/patches/_pmu.yml @@ -9,3 +9,9 @@ PMU: size: 0x20 access: read-write resetValue: 0x0 + + _modify: + _interrupts: + PMU: + name: PMU_LP_INT + value: 5 diff --git a/esp32s2-ulp/build.rs b/esp32s2-ulp/build.rs index d0781acdb6..a742427679 100644 --- a/esp32s2-ulp/build.rs +++ b/esp32s2-ulp/build.rs @@ -1,8 +1,5 @@ #![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; +use std::{env, fs::File, io::Write, path::PathBuf}; fn main() { if env::var_os("CARGO_FEATURE_RT").is_some() { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); diff --git a/esp32s2-ulp/src/interrupt.rs b/esp32s2-ulp/src/interrupt.rs index eccc9291e0..5d84af9463 100644 --- a/esp32s2-ulp/src/interrupt.rs +++ b/esp32s2-ulp/src/interrupt.rs @@ -4,25 +4,25 @@ #[repr(u16)] pub enum Interrupt { #[doc = "0 - TOUCH_DONE_INT"] - TOUCH_DONE_INT = 0, + TOUCH_DONE_INT = 0, #[doc = "1 - TOUCH_INACTIVE_INT"] TOUCH_INACTIVE_INT = 1, #[doc = "2 - TOUCH_ACTIVE_INT"] - TOUCH_ACTIVE_INT = 2, + TOUCH_ACTIVE_INT = 2, #[doc = "3 - SARADC1_DONE_INT"] - SARADC1_DONE_INT = 3, + SARADC1_DONE_INT = 3, #[doc = "4 - SARADC2_DONE_INT"] - SARADC2_DONE_INT = 4, + SARADC2_DONE_INT = 4, #[doc = "5 - TSENS_DONE_INT"] - TSENS_DONE_INT = 5, + TSENS_DONE_INT = 5, #[doc = "6 - RISCV_START_INT"] - RISCV_START_INT = 6, + RISCV_START_INT = 6, #[doc = "7 - SW_INT"] - SW_INT = 7, + SW_INT = 7, #[doc = "8 - SWD_INT"] - SWD_INT = 8, + SWD_INT = 8, #[doc = "9 - GPIO_INT"] - GPIO_INT = 9, + GPIO_INT = 9, } #[doc = r" TryFromInterruptError"] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/esp32s2-ulp/src/lib.rs b/esp32s2-ulp/src/lib.rs index e09162ea94..63af02b384 100644 --- a/esp32s2-ulp/src/lib.rs +++ b/esp32s2-ulp/src/lib.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API for ESP32-S2-ULP microcontrollers (generated using svd2rust v0.37.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![doc = "Peripheral access API for ESP32-S2-ULP microcontrollers (generated using svd2rust v0.37.1 (f74f0b3 2026-04-17))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![allow(non_camel_case_types)] #![allow(non_snake_case)] #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] diff --git a/esp32s3-ulp/build.rs b/esp32s3-ulp/build.rs index d0781acdb6..a742427679 100644 --- a/esp32s3-ulp/build.rs +++ b/esp32s3-ulp/build.rs @@ -1,8 +1,5 @@ #![doc = r" Builder file for Peripheral access crate generated by svd2rust tool"] -use std::env; -use std::fs::File; -use std::io::Write; -use std::path::PathBuf; +use std::{env, fs::File, io::Write, path::PathBuf}; fn main() { if env::var_os("CARGO_FEATURE_RT").is_some() { let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); diff --git a/esp32s3-ulp/src/interrupt.rs b/esp32s3-ulp/src/interrupt.rs index fe35e49a44..740c97d245 100644 --- a/esp32s3-ulp/src/interrupt.rs +++ b/esp32s3-ulp/src/interrupt.rs @@ -4,31 +4,31 @@ #[repr(u16)] pub enum Interrupt { #[doc = "0 - TOUCH_DONE_INT"] - TOUCH_DONE_INT = 0, + TOUCH_DONE_INT = 0, #[doc = "1 - TOUCH_INACTIVE_INT"] - TOUCH_INACTIVE_INT = 1, + TOUCH_INACTIVE_INT = 1, #[doc = "2 - TOUCH_ACTIVE_INT"] - TOUCH_ACTIVE_INT = 2, + TOUCH_ACTIVE_INT = 2, #[doc = "3 - SARADC1_DONE_INT"] - SARADC1_DONE_INT = 3, + SARADC1_DONE_INT = 3, #[doc = "4 - SARADC2_DONE_INT"] - SARADC2_DONE_INT = 4, + SARADC2_DONE_INT = 4, #[doc = "5 - TSENS_DONE_INT"] - TSENS_DONE_INT = 5, + TSENS_DONE_INT = 5, #[doc = "6 - RISCV_START_INT"] - RISCV_START_INT = 6, + RISCV_START_INT = 6, #[doc = "7 - SW_INT"] - SW_INT = 7, + SW_INT = 7, #[doc = "8 - SWD_INT"] - SWD_INT = 8, + SWD_INT = 8, #[doc = "9 - TOUCH_TIME_OUT_INT"] - TOUCH_TIME_OUT_INT = 9, + TOUCH_TIME_OUT_INT = 9, #[doc = "10 - TOUCH_APPROACH_LOOP_DONE_INT"] TOUCH_APPROACH_LOOP_DONE_INT = 10, #[doc = "11 - TOUCH_SCAN_DONE_INT"] - TOUCH_SCAN_DONE_INT = 11, + TOUCH_SCAN_DONE_INT = 11, #[doc = "12 - GPIO_INT"] - GPIO_INT = 12, + GPIO_INT = 12, } #[doc = r" TryFromInterruptError"] #[cfg_attr(feature = "defmt", derive(defmt::Format))] diff --git a/esp32s3-ulp/src/lib.rs b/esp32s3-ulp/src/lib.rs index 25402e5e58..09f73209dc 100644 --- a/esp32s3-ulp/src/lib.rs +++ b/esp32s3-ulp/src/lib.rs @@ -1,4 +1,4 @@ -#![doc = "Peripheral access API for ESP32-S3-ULP microcontrollers (generated using svd2rust v0.37.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![doc = "Peripheral access API for ESP32-S3-ULP microcontrollers (generated using svd2rust v0.37.1 (f74f0b3 2026-04-17))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] #![allow(non_camel_case_types)] #![allow(non_snake_case)] #![doc(html_logo_url = "https://avatars.githubusercontent.com/u/46717278")] diff --git a/xtask/src/main.rs b/xtask/src/main.rs index f30c271dce..4c13e1e5b3 100644 --- a/xtask/src/main.rs +++ b/xtask/src/main.rs @@ -218,7 +218,10 @@ fn generate_package(workspace: &Path, chip: &Chip) -> Result<()> { config.ident_formats_theme = Some(IdentFormatsTheme::Legacy); config.max_cluster_size = true; config.impl_defmt = Some("defmt".into()); - config.skip_peripherals_struct = true; + config.skip_peripherals_struct = match chip { + Chip::Esp32s3Ulp | Chip::Esp32s2Ulp | Chip::Esp32c6Lp => false, + _ => true + }; let input = fs::read_to_string(svd_file)?; let device = svd2rust::load_from(&input, &config)?;