diff --git a/esp-hal/src/gpio/dedicated/low_level/esp32s2.rs b/esp-hal/src/gpio/dedicated/low_level/esp32s2.rs new file mode 100644 index 00000000000..7760fe766a2 --- /dev/null +++ b/esp-hal/src/gpio/dedicated/low_level/esp32s2.rs @@ -0,0 +1,31 @@ +#[inline(always)] +pub(super) fn initialize() { + // Allow instruction access, which has better performance than register access. + let regs = unsafe { esp32s2::DEDICATED_GPIO::steal() }; + regs.out_cpu() + .write(|w| unsafe { w.bits((1 << property!("dedicated_gpio.channel_count")) - 1) }); +} + +#[inline(always)] +pub(super) fn set_output_enabled(_mask: u32, _en: bool) { + // Nothing to do. +} + +#[inline(always)] +pub(super) fn read_in() -> u32 { + let val; + unsafe { core::arch::asm!("get_gpio_in {0}", out(reg) val) }; + val +} + +#[inline(always)] +pub(super) fn read_out() -> u32 { + let val; + unsafe { core::arch::asm!("rur.gpio_out {0}", out(reg) val) }; + val +} + +#[inline(always)] +pub(super) fn write(mask: u32, value: u32) { + unsafe { core::arch::asm!("wr_mask_gpio_out {0}, {1}", in(reg) mask, in(reg) value) } +} diff --git a/esp-hal/src/gpio/dedicated/low_level/esp32s3.rs b/esp-hal/src/gpio/dedicated/low_level/esp32s3.rs new file mode 100644 index 00000000000..c033f3cc285 --- /dev/null +++ b/esp-hal/src/gpio/dedicated/low_level/esp32s3.rs @@ -0,0 +1,19 @@ +#[inline(always)] +pub(super) fn initialize() {} + +#[inline(always)] +pub(super) fn set_output_enabled(_mask: u32, _en: bool) { + // Nothing to do. +} + +#[inline(always)] +pub(super) fn read_in() -> u32 { + let val; + unsafe { core::arch::asm!("ee.get_gpio_in {0}", out(reg) val) }; + val +} + +#[inline(always)] +pub(super) fn write(mask: u32, value: u32) { + unsafe { core::arch::asm!("ee.wr_mask_gpio_out {0}, {1}", in(reg) mask, in(reg) value) } +} diff --git a/esp-hal/src/gpio/dedicated/low_level/riscv_v1.rs b/esp-hal/src/gpio/dedicated/low_level/riscv_v1.rs new file mode 100644 index 00000000000..1e1d7a2772b --- /dev/null +++ b/esp-hal/src/gpio/dedicated/low_level/riscv_v1.rs @@ -0,0 +1,40 @@ +// CSR_GPIO_OEN_USER 0x803 +// CSR_GPIO_IN_USER 0x804 +// CSR_GPIO_OUT_USER 0x805 + +#[inline(always)] +pub(super) fn set_output_enabled(mask: u32, en: bool) { + riscv::read_csr!(0x803); + riscv::write_csr!(0x803); + + unsafe { + let bits = _read(); + if en { + _write(bits | mask as usize) + } else { + _write(bits & !mask as usize) + } + } +} + +#[inline(always)] +pub(super) fn read_in() -> u32 { + riscv::read_csr!(0x804); + unsafe { _read() as u32 } +} + +#[inline(always)] +pub(super) fn read_out() -> u32 { + riscv::read_csr!(0x805); + unsafe { _read() as u32 } +} + +#[inline(always)] +pub(super) fn write(mask: u32, value: u32) { + riscv::set!(0x805); + riscv::clear!(0x805); + unsafe { + _set((mask & value) as usize); + _clear((mask & !value) as usize); + } +} diff --git a/esp-hal/src/gpio/dedicated.rs b/esp-hal/src/gpio/dedicated/mod.rs similarity index 93% rename from esp-hal/src/gpio/dedicated.rs rename to esp-hal/src/gpio/dedicated/mod.rs index 34479693690..2de6fb3b811 100644 --- a/esp-hal/src/gpio/dedicated.rs +++ b/esp-hal/src/gpio/dedicated/mod.rs @@ -43,11 +43,11 @@ //! - [`write_ll`]: write output levels for a selected set of channels in one operation //! - [`read_all_ll`]: read the current input levels of all channels #![cfg_attr( - not(esp32s3), + not(dedicated_gpio_version = "esp32s3"), doc = r#"- [`output_levels_ll`]: read the current output levels of all channels"# )] #![cfg_attr( - esp32s3, + dedicated_gpio_version = "esp32s3", doc = r#"- `output_levels_ll`: read the current output levels of all channels (not available on ESP32-S3 due to an LLVM bug, see )"# )] //! These functions operate purely on channel bitmasks (bit 0 -> channel 0, bit 1 -> channel 1, ...) @@ -129,6 +129,11 @@ use core::{convert::Infallible, marker::PhantomData}; use procmacros::doc_replace; use strum::EnumCount as _; +#[cfg_attr(dedicated_gpio_version = "esp32s2", path = "low_level/esp32s2.rs")] +#[cfg_attr(dedicated_gpio_version = "esp32s3", path = "low_level/esp32s3.rs")] +#[cfg_attr(dedicated_gpio_version = "riscv_v1", path = "low_level/riscv_v1.rs")] +mod low_level; + use crate::{ gpio::{ AnyPin, @@ -186,13 +191,7 @@ impl DedicatedGpio<'_> { PeripheralClockControl::disable(Peripheral::DedicatedGpio); } - #[cfg(esp32s2)] - { - // Allow instruction access, which has better performance than register access. - let regs = unsafe { esp32s2::DEDICATED_GPIO::steal() }; - regs.out_cpu() - .write(|w| unsafe { w.bits((1 << property!("dedicated_gpio.channel_count")) - 1) }); - } + low_level::initialize(); } } @@ -549,7 +548,7 @@ impl<'lt> DedicatedGpioInput<'lt> { "Dedicated GPIO used on a different CPU core than it was created on" ); - let bits = ll::read_in(); + let bits = low_level::read_in(); Level::from(bits & self.mask != 0) } } @@ -577,7 +576,7 @@ impl embedded_hal::digital::InputPin for DedicatedGpioInput<'_> { /// create a driver, you can use the [`DedicatedGpioOutput::new`] method, then /// [`DedicatedGpioOutput::with_pin`] to add output drivers. #[cfg_attr( - esp32s3, + dedicated_gpio_version = "esp32s3", doc = r#"
@@ -640,7 +639,7 @@ impl<'lt> DedicatedGpioOutput<'lt> { where CH: OutputChannel + 'lt, { - ll::set_output_enabled(channel.mask(), true); + low_level::set_output_enabled(channel.mask(), true); Self { mask: channel.mask(), signal: channel.output_signal(), @@ -677,16 +676,16 @@ impl<'lt> DedicatedGpioOutput<'lt> { ); if level == Level::High { - ll::write(self.mask, self.mask); + low_level::write(self.mask, self.mask); } else { - ll::write(self.mask, 0); + low_level::write(self.mask, 0); } } /// Returns the current output state of the GPIO pins. /// /// Returns [`Level::High`] if any of the GPIO pins are set high, otherwise [`Level::Low`]. - #[cfg(not(esp32s3))] + #[cfg(not(dedicated_gpio_version = "esp32s3"))] #[inline(always)] pub fn output_level(&self) -> Level { #[cfg(all(debug_assertions, multi_core))] @@ -696,7 +695,7 @@ impl<'lt> DedicatedGpioOutput<'lt> { "Dedicated GPIO used on a different CPU core than it was created on" ); - Level::from(ll::read_out() & self.mask != 0) + Level::from(low_level::read_out() & self.mask != 0) } } @@ -813,7 +812,7 @@ impl<'lt> DedicatedGpioFlex<'lt> { } /// Enables or disables the output buffer of the GPIO pin. - #[cfg(riscv)] // Xtensas always have the output enabled. + #[cfg(dedicated_gpio_version = "riscv_v1")] // Xtensas always have the output enabled. pub fn set_output_enabled(&mut self, enabled: bool) { #[cfg(all(debug_assertions, multi_core))] debug_assert_eq!( @@ -822,7 +821,7 @@ impl<'lt> DedicatedGpioFlex<'lt> { "Dedicated GPIO used on a different CPU core than it was created on" ); - ll::set_output_enabled(self.mask, enabled); + low_level::set_output_enabled(self.mask, enabled); } /// Change the current state of the GPIO pin. @@ -836,14 +835,14 @@ impl<'lt> DedicatedGpioFlex<'lt> { ); if level == Level::High { - ll::write(self.mask, self.mask); + low_level::write(self.mask, self.mask); } else { - ll::write(self.mask, 0); + low_level::write(self.mask, 0); } } /// Returns the current output state of the GPIO pin. - #[cfg(not(esp32s3))] + #[cfg(not(dedicated_gpio_version = "esp32s3"))] #[inline(always)] pub fn output_level(&self) -> Level { #[cfg(all(debug_assertions, multi_core))] @@ -853,7 +852,7 @@ impl<'lt> DedicatedGpioFlex<'lt> { "Dedicated GPIO used on a different CPU core than it was created on" ); - Level::from(ll::read_out() & self.mask != 0) + Level::from(low_level::read_out() & self.mask != 0) } /// Read the current state of the GPIO pins. @@ -866,7 +865,7 @@ impl<'lt> DedicatedGpioFlex<'lt> { "Dedicated GPIO used on a different CPU core than it was created on" ); - let bits = ll::read_in(); + let bits = low_level::read_in(); Level::from(bits & self.mask != 0) } } @@ -942,7 +941,7 @@ Only channels configured on the current CPU core can be used. )] #[inline(always)] pub fn write_ll(mask: u32, value: u32) { - ll::write(mask, value); + low_level::write(mask, value); } /// Low-level function to read the current state of all dedicated input channels. @@ -951,17 +950,17 @@ pub fn write_ll(mask: u32, value: u32) { /// channel. Bit 0 represents channel 0, bit 1 represents channel 1, etc. #[inline(always)] pub fn read_all_ll() -> u32 { - ll::read_in() + low_level::read_in() } /// Low-level function to read the current output levels of all dedicated GPIO channels. /// /// The returned value is a bitmask where each bit represents the output level of a channel: /// bit 0 -> channel 0, bit 1 -> channel 1, etc. A bit value of 1 means the channel output is high. -#[cfg(not(esp32s3))] +#[cfg(not(dedicated_gpio_version = "esp32s3"))] #[inline(always)] pub fn output_levels_ll() -> u32 { - ll::read_out() + low_level::read_out() } #[doc_replace] @@ -982,7 +981,7 @@ pub fn output_levels_ll() -> u32 { /// individual pins: writing channel bits affects every pin connected to that /// channel. #[cfg_attr( - esp32s3, + dedicated_gpio_version = "esp32s3", doc = r#"
@@ -1214,7 +1213,7 @@ You should only disable dedicated GPIO drivers that were configured on the same (bits & !self.mask) == 0, "Trying to set bits outside of the bundle mask" ); - ll::write(bits, bits); // or ll::write(self.mask, bits); + low_level::write(bits, bits); // or low_level::write(self.mask, bits); } /// Sets selected channels **low**. @@ -1249,8 +1248,8 @@ You should only disable dedicated GPIO drivers that were configured on the same (bits & !self.mask) == 0, "Trying to clear bits outside of the bundle mask" ); - ll::write(bits, 0); - // or ll::write(bits & self.mask, 0); + low_level::write(bits, 0); + // or low_level::write(bits & self.mask, 0); // the latter is safer (preventing writing to channels outside of the bundle) but slower } @@ -1286,7 +1285,7 @@ You should only disable dedicated GPIO drivers that were configured on the same "Dedicated GPIO used on a different CPU core than it was created on" ); - ll::write(self.mask, bits); + low_level::write(self.mask, bits); } /// Returns the current output levels of the channels included by this bundle. @@ -1298,7 +1297,7 @@ You should only disable dedicated GPIO drivers that were configured on the same /// If the bundle mask is `0b0000_1011` (channels 0, 1, and 3), then /// `output_levels()` will only contain bits 0, 1, and 3, regardless of the output /// state of other channels. - #[cfg(not(esp32s3))] + #[cfg(not(dedicated_gpio_version = "esp32s3"))] #[inline(always)] pub fn output_levels(&self) -> u32 { #[cfg(all(debug_assertions, multi_core))] @@ -1307,7 +1306,7 @@ You should only disable dedicated GPIO drivers that were configured on the same Cpu::current(), "Dedicated GPIO used on a different CPU core than it was created on" ); - ll::read_out() & self.mask + low_level::read_out() & self.mask } } @@ -1526,7 +1525,7 @@ You should only disable dedicated GPIO drivers that were configured on the same "Dedicated GPIO used on a different CPU core than it was created on" ); - ll::read_in() & self.mask + low_level::read_in() & self.mask } /// Returns `true` if all channels in this bundle are currently high. @@ -1539,7 +1538,7 @@ You should only disable dedicated GPIO drivers that were configured on the same "Dedicated GPIO used on a different CPU core than it was created on" ); - (ll::read_in() & self.mask) == self.mask + (low_level::read_in() & self.mask) == self.mask } /// Returns `true` if all channels in this bundle are currently low. @@ -1552,7 +1551,7 @@ You should only disable dedicated GPIO drivers that were configured on the same "Dedicated GPIO used on a different CPU core than it was created on" ); - (ll::read_in() & self.mask) == 0 + (low_level::read_in() & self.mask) == 0 } } @@ -1579,7 +1578,7 @@ impl<'lt> Default for DedicatedGpioInputBundle<'lt> { /// input and output. The bundle operates on *channels*, not pins: writing channel bits /// affects the pins currently connected to those channels. #[cfg_attr( - esp32s3, + dedicated_gpio_version = "esp32s3", doc = r#"
@@ -1796,7 +1795,7 @@ You should only disable dedicated GPIO drivers that were configured on the same (bits & !self.mask) == 0, "Trying to set bits outside of the bundle mask" ); - ll::write(bits, bits); // or ll::write(self.mask, bits); + low_level::write(bits, bits); // or low_level::write(self.mask, bits); } /// Sets selected channels **low**. @@ -1832,7 +1831,7 @@ You should only disable dedicated GPIO drivers that were configured on the same (bits & !self.mask) == 0, "Trying to clear bits outside of the bundle mask" ); - ll::write(bits, 0); // or ll::write(bits & self.mask, 0); the latter is safer but slower + low_level::write(bits, 0); // or low_level::write(bits & self.mask, 0); the latter is safer but slower } /// Writes output levels for **all channels included by this bundle**. @@ -1866,7 +1865,7 @@ You should only disable dedicated GPIO drivers that were configured on the same Cpu::current(), "Dedicated GPIO used on a different CPU core than it was created on" ); - ll::write(self.mask, bits); + low_level::write(self.mask, bits); } /// Returns the current output levels of the channels included by this bundle. @@ -1878,7 +1877,7 @@ You should only disable dedicated GPIO drivers that were configured on the same /// If the bundle mask is `0b0000_1011` (channels 0, 1, and 3), then /// `output_levels()` will only contain bits 0, 1, and 3, regardless of the output /// state of other channels. - #[cfg(not(esp32s3))] + #[cfg(not(dedicated_gpio_version = "esp32s3"))] #[inline(always)] pub fn output_levels(&self) -> u32 { #[cfg(all(debug_assertions, multi_core))] @@ -1887,7 +1886,7 @@ You should only disable dedicated GPIO drivers that were configured on the same Cpu::current(), "Dedicated GPIO used on a different CPU core than it was created on" ); - ll::read_out() & self.mask + low_level::read_out() & self.mask } /// Reads the current state of the channels included by this bundle. @@ -1908,7 +1907,7 @@ You should only disable dedicated GPIO drivers that were configured on the same "Dedicated GPIO used on a different CPU core than it was created on" ); - ll::read_in() & self.mask + low_level::read_in() & self.mask } /// Returns `true` if all channels in this bundle are currently high. @@ -1921,7 +1920,7 @@ You should only disable dedicated GPIO drivers that were configured on the same "Dedicated GPIO used on a different CPU core than it was created on" ); - (ll::read_in() & self.mask) == self.mask + (low_level::read_in() & self.mask) == self.mask } /// Returns `true` if all channels in this bundle are currently low. @@ -1934,7 +1933,7 @@ You should only disable dedicated GPIO drivers that were configured on the same "Dedicated GPIO used on a different CPU core than it was created on" ); - (ll::read_in() & self.mask) == 0 + (low_level::read_in() & self.mask) == 0 } } @@ -1943,103 +1942,3 @@ impl<'lt> Default for DedicatedGpioFlexBundle<'lt> { Self::new() } } - -#[cfg(esp32s2)] -mod ll { - #[inline(always)] - pub(super) fn set_output_enabled(_mask: u32, _en: bool) { - // nothing to do - } - - #[inline(always)] - pub(super) fn read_in() -> u32 { - let val; - unsafe { core::arch::asm!("get_gpio_in {0}", out(reg) val) }; - val - } - - #[inline(always)] - pub(super) fn read_out() -> u32 { - let val; - unsafe { core::arch::asm!("rur.gpio_out {0}", out(reg) val) }; - val - } - - #[inline(always)] - pub(super) fn write(mask: u32, value: u32) { - unsafe { core::arch::asm!("wr_mask_gpio_out {0}, {1}", in(reg) mask, in(reg) value) } - } -} - -#[cfg(esp32s3)] -mod ll { - #[inline(always)] - pub(super) fn set_output_enabled(_mask: u32, _en: bool) { - // nothing to do - } - - #[inline(always)] - pub(super) fn read_in() -> u32 { - let val; - unsafe { core::arch::asm!("ee.get_gpio_in {0}", out(reg) val) }; - val - } - - #[cfg(not(esp32s3))] - #[inline(always)] - pub(super) fn read_out() -> u32 { - // currently unavailable due to an LLVM bug, see https://github.com/espressif/llvm-project/issues/120 - let val; - unsafe { core::arch::asm!("rur.gpio_out {0}", out(reg) val) }; - val - } - - #[inline(always)] - pub(super) fn write(mask: u32, value: u32) { - unsafe { core::arch::asm!("ee.wr_mask_gpio_out {0}, {1}", in(reg) mask, in(reg) value) } - } -} - -#[cfg(riscv)] -mod ll { - // CSR_GPIO_OEN_USER 0x803 - // CSR_GPIO_IN_USER 0x804 - // CSR_GPIO_OUT_USER 0x805 - - #[inline(always)] - pub(super) fn set_output_enabled(mask: u32, en: bool) { - riscv::read_csr!(0x803); - riscv::write_csr!(0x803); - - unsafe { - let bits = _read(); - if en { - _write(bits | mask as usize) - } else { - _write(bits & !mask as usize) - } - } - } - - #[inline(always)] - pub(super) fn read_in() -> u32 { - riscv::read_csr!(0x804); - unsafe { _read() as u32 } - } - - #[inline(always)] - pub(super) fn read_out() -> u32 { - riscv::read_csr!(0x805); - unsafe { _read() as u32 } - } - - #[inline(always)] - pub(super) fn write(mask: u32, value: u32) { - riscv::set!(0x805); - riscv::clear!(0x805); - unsafe { - _set((mask & value) as usize); - _clear((mask & !value) as usize); - } - } -} diff --git a/esp-hal/src/gpio/interrupt.rs b/esp-hal/src/gpio/interrupt.rs index a94c14250e7..f4e0a7e3f27 100644 --- a/esp-hal/src/gpio/interrupt.rs +++ b/esp-hal/src/gpio/interrupt.rs @@ -55,9 +55,15 @@ use portable_atomic::{AtomicPtr, Ordering}; use strum::EnumCount; use crate::{ - gpio::{AnyPin, GPIO_LOCK, GpioBank, InputPin, set_int_enable}, + gpio::{ + AnyPin, + GPIO_LOCK, + GpioBank, + InputPin, + low_level::{InterruptStatusRegisterAccess, set_int_enable}, + }, interrupt::Priority, - peripherals::{GPIO, Interrupt}, + peripherals::Interrupt, ram, }; #[cfg(feature = "rt")] @@ -102,11 +108,16 @@ pub(crate) fn bind_default_interrupt_handler() { // The vector table doesn't contain a custom entry. Still, the // peripheral interrupt may already be bound to something else. - for cpu in cores() { + let mut is_mapped = false; + super::low_level::for_each_interrupt_core(|cpu| { if interrupt::mapped_to(cpu, Interrupt::GPIO).is_some() { - info!("Not using default GPIO interrupt handler: peripheral interrupt already in use"); - return; + is_mapped = true; } + }); + + if is_mapped { + info!("Not using default GPIO interrupt handler: peripheral interrupt already in use"); + return; } interrupt::bind_handler(Interrupt::GPIO, default_gpio_interrupt_handler); @@ -114,36 +125,18 @@ pub(crate) fn bind_default_interrupt_handler() { // On ESP32, there are separate interrupt status registers for each core, we need to enable the // interrupt handler on each core otherwise GPIOs listening on the App CPU will not receive // interrupts. - #[cfg(esp32)] - crate::interrupt::enable_on_cpu( - crate::system::Cpu::AppCpu, - Interrupt::GPIO, - Priority::Priority1, - ); -} - -cfg_if::cfg_if! { - if #[cfg(esp32)] { - // On ESP32, the interrupt fires on the core that started listening for a pin event. - fn cores() -> impl Iterator { - crate::system::Cpu::all() - } - } else { - fn cores() -> [crate::system::Cpu; 1] { - [crate::system::Cpu::current()] - } - } + super::low_level::enable_additional_default_interrupts(Interrupt::GPIO, Priority::Priority1); } /// Configures the given peripheral interrupt to trigger the vectored handler of given priority. pub(super) fn set_interrupt_priority(interrupt: Interrupt, priority: Priority) { - for cpu in cores() { + super::low_level::for_each_interrupt_core(|cpu| { // Only change priority if the interrupt is mapped to the core, otherwise we would enable // the interrupt unconditionally, which we don't want to do. if crate::interrupt::mapped_to(cpu, interrupt).is_some() { crate::interrupt::enable_on_cpu(cpu, interrupt, priority); } - } + }); } /// The default GPIO interrupt handler, when the user has not set one. @@ -252,39 +245,6 @@ pub(super) unsafe fn wake_pin_impl(pin: u8) { }); } -#[derive(Clone, Copy)] -pub(crate) enum InterruptStatusRegisterAccess { - Bank0, - #[cfg(gpio_has_bank_1)] - Bank1, -} - -impl InterruptStatusRegisterAccess { - pub(crate) fn interrupt_status_read(self) -> u32 { - cfg_if::cfg_if! { - if #[cfg(esp32)] { - match self { - Self::Bank0 => GPIO::regs().status().read().bits(), - Self::Bank1 => GPIO::regs().status1().read().bits(), - } - } else if #[cfg(esp32p4)] { - // P4 PAC: intr_0() (Core0 GPIO interrupt status) - match self { - Self::Bank0 => GPIO::regs().intr_0().read().bits(), - #[cfg(gpio_has_bank_1)] - Self::Bank1 => GPIO::regs().intr1_0().read().bits(), - } - } else { - match self { - Self::Bank0 => GPIO::regs().pcpu_int().read().bits(), - #[cfg(gpio_has_bank_1)] - Self::Bank1 => GPIO::regs().pcpu_int1().read().bits(), - } - } - } - } -} - fn interrupt_status() -> [(GpioBank, u32); GpioBank::COUNT] { let intrs_bank0 = InterruptStatusRegisterAccess::Bank0.interrupt_status_read(); diff --git a/esp-hal/src/gpio/low_level/mod.rs b/esp-hal/src/gpio/low_level/mod.rs new file mode 100644 index 00000000000..476b95f82bc --- /dev/null +++ b/esp-hal/src/gpio/low_level/mod.rs @@ -0,0 +1,190 @@ +#[cfg_attr(gpio_version = "1", path = "v1.rs")] +#[cfg_attr(gpio_version = "2", path = "v2.rs")] +#[cfg_attr(gpio_version = "3", path = "v3.rs")] +mod version; + +use portable_atomic::AtomicU32; +use strum::EnumCount; + +use super::AnyPin; +use crate::peripherals::GPIO; + +#[doc(hidden)] +#[derive(Debug, Eq, PartialEq, Copy, Clone, Hash, EnumCount)] +#[cfg_attr(feature = "defmt", derive(defmt::Format))] +pub enum GpioBank { + _0, + #[cfg(gpio_has_bank_1)] + _1, +} + +impl GpioBank { + pub(crate) fn async_operations(self) -> &'static AtomicU32 { + static FLAGS: [AtomicU32; GpioBank::COUNT] = [const { AtomicU32::new(0) }; GpioBank::COUNT]; + + &FLAGS[self as usize] + } + + pub(crate) fn offset(self) -> u8 { + match self { + Self::_0 => 0, + #[cfg(gpio_has_bank_1)] + Self::_1 => 32, + } + } + + pub(crate) fn write_out_en(self, word: u32, enable: bool) { + if enable { + self.write_out_en_set(word); + } else { + self.write_out_en_clear(word); + } + } + + pub(crate) fn write_out_en_clear(self, word: u32) { + match self { + Self::_0 => GPIO::regs() + .enable_w1tc() + .write(|w| unsafe { w.bits(word) }), + #[cfg(gpio_has_bank_1)] + Self::_1 => GPIO::regs() + .enable1_w1tc() + .write(|w| unsafe { w.bits(word) }), + }; + } + + pub(crate) fn write_out_en_set(self, word: u32) { + match self { + Self::_0 => GPIO::regs() + .enable_w1ts() + .write(|w| unsafe { w.bits(word) }), + #[cfg(gpio_has_bank_1)] + Self::_1 => GPIO::regs() + .enable1_w1ts() + .write(|w| unsafe { w.bits(word) }), + }; + } + + pub(crate) fn read_input(self) -> u32 { + match self { + Self::_0 => GPIO::regs().in_().read().bits(), + #[cfg(gpio_has_bank_1)] + Self::_1 => GPIO::regs().in1().read().bits(), + } + } + + pub(crate) fn read_output(self) -> u32 { + match self { + Self::_0 => GPIO::regs().out().read().bits(), + #[cfg(gpio_has_bank_1)] + Self::_1 => GPIO::regs().out1().read().bits(), + } + } + + pub(crate) fn read_interrupt_status(self) -> u32 { + version::read_bank_interrupt_status(self) + } + + pub(crate) fn write_interrupt_status_clear(self, word: u32) { + match self { + Self::_0 => GPIO::regs() + .status_w1tc() + .write(|w| unsafe { w.bits(word) }), + #[cfg(gpio_has_bank_1)] + Self::_1 => GPIO::regs() + .status1_w1tc() + .write(|w| unsafe { w.bits(word) }), + }; + } + + pub(crate) fn write_output(self, word: u32, set: bool) { + if set { + self.write_output_set(word); + } else { + self.write_output_clear(word); + } + } + + pub(crate) fn write_output_set(self, word: u32) { + match self { + Self::_0 => GPIO::regs().out_w1ts().write(|w| unsafe { w.bits(word) }), + #[cfg(gpio_has_bank_1)] + Self::_1 => GPIO::regs().out1_w1ts().write(|w| unsafe { w.bits(word) }), + }; + } + + pub(crate) fn write_output_clear(self, word: u32) { + match self { + Self::_0 => GPIO::regs().out_w1tc().write(|w| unsafe { w.bits(word) }), + #[cfg(gpio_has_bank_1)] + Self::_1 => GPIO::regs().out1_w1tc().write(|w| unsafe { w.bits(word) }), + }; + } +} + +#[derive(Clone, Copy)] +pub(crate) enum InterruptStatusRegisterAccess { + Bank0, + #[cfg(gpio_has_bank_1)] + Bank1, +} + +impl InterruptStatusRegisterAccess { + pub(crate) fn interrupt_status_read(self) -> u32 { + version::read_interrupt_status(self) + } +} + +pub(crate) fn bank(_gpio_num: u8) -> GpioBank { + #[cfg(gpio_has_bank_1)] + if _gpio_num >= 32 { + return GpioBank::_1; + } + + GpioBank::_0 +} + +pub(crate) fn prepare_pin_pull(pin: &AnyPin<'_>, pull_up: bool, pull_down: bool) { + version::prepare_pin_pull(pin, pull_up, pull_down); +} + +pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + version::gpio_intr_enable(int_enable, nmi_enable) +} + +pub(crate) fn for_each_interrupt_core(f: impl FnMut(crate::system::Cpu)) { + version::for_each_interrupt_core(f); +} + +#[cfg(feature = "rt")] +pub(crate) fn enable_additional_default_interrupts( + interrupt: crate::peripherals::Interrupt, + priority: crate::interrupt::Priority, +) { + version::enable_additional_default_interrupts(interrupt, priority); +} + +/// Set GPIO event listening. +/// +/// - `gpio_num`: the pin to configure +/// - `int_ena`: maskable and non-maskable CPU interrupt bits. None to leave unchanged. +/// - `int_type`: interrupt type, see [super::Event] (or 0 to disable) +/// - `wake_up_from_light_sleep`: whether to wake up from light sleep +pub(crate) fn set_int_enable( + gpio_num: u8, + int_ena: Option, + int_type: u8, + wake_up_from_light_sleep: bool, +) { + GPIO::regs().pin(gpio_num as usize).modify(|_, w| unsafe { + if let Some(int_ena) = int_ena { + w.int_ena().bits(int_ena); + } + w.int_type().bits(int_type); + w.wakeup_enable().bit(wake_up_from_light_sleep) + }); +} + +pub(crate) fn is_int_enabled(gpio_num: u8) -> bool { + GPIO::regs().pin(gpio_num as usize).read().int_ena().bits() != 0 +} diff --git a/esp-hal/src/gpio/low_level/v1.rs b/esp-hal/src/gpio/low_level/v1.rs new file mode 100644 index 00000000000..32141b10f3b --- /dev/null +++ b/esp-hal/src/gpio/low_level/v1.rs @@ -0,0 +1,43 @@ +use super::{GpioBank, InterruptStatusRegisterAccess}; +use crate::{gpio::AnyPin, peripherals::GPIO}; + +pub(super) fn read_bank_interrupt_status(bank: GpioBank) -> u32 { + match bank { + GpioBank::_0 => GPIO::regs().status().read().bits(), + #[cfg(gpio_has_bank_1)] + GpioBank::_1 => GPIO::regs().status1().read().bits(), + } +} + +pub(super) fn read_interrupt_status(access: InterruptStatusRegisterAccess) -> u32 { + match access { + InterruptStatusRegisterAccess::Bank0 => GPIO::regs().status().read().bits(), + #[cfg(gpio_has_bank_1)] + InterruptStatusRegisterAccess::Bank1 => GPIO::regs().status1().read().bits(), + } +} + +pub(super) fn prepare_pin_pull(pin: &AnyPin<'_>, pull_up: bool, pull_down: bool) { + crate::soc::gpio::errata36(unsafe { pin.clone_unchecked() }, pull_up, pull_down); +} + +pub(super) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + match crate::system::Cpu::current() { + crate::system::Cpu::AppCpu => int_enable as u8 | ((nmi_enable as u8) << 1), + crate::system::Cpu::ProCpu => ((int_enable as u8) << 2) | ((nmi_enable as u8) << 3), + } +} + +pub(super) fn for_each_interrupt_core(mut f: impl FnMut(crate::system::Cpu)) { + for cpu in crate::system::Cpu::all() { + f(cpu); + } +} + +#[cfg(feature = "rt")] +pub(super) fn enable_additional_default_interrupts( + interrupt: crate::peripherals::Interrupt, + priority: crate::interrupt::Priority, +) { + crate::interrupt::enable_on_cpu(crate::system::Cpu::AppCpu, interrupt, priority); +} diff --git a/esp-hal/src/gpio/low_level/v2.rs b/esp-hal/src/gpio/low_level/v2.rs new file mode 100644 index 00000000000..0e15fa651a3 --- /dev/null +++ b/esp-hal/src/gpio/low_level/v2.rs @@ -0,0 +1,35 @@ +use super::{GpioBank, InterruptStatusRegisterAccess}; +use crate::{gpio::AnyPin, peripherals::GPIO}; + +pub(super) fn read_bank_interrupt_status(bank: GpioBank) -> u32 { + match bank { + GpioBank::_0 => GPIO::regs().status().read().bits(), + #[cfg(gpio_has_bank_1)] + GpioBank::_1 => GPIO::regs().status1().read().bits(), + } +} + +pub(super) fn read_interrupt_status(access: InterruptStatusRegisterAccess) -> u32 { + match access { + InterruptStatusRegisterAccess::Bank0 => GPIO::regs().pcpu_int().read().bits(), + #[cfg(gpio_has_bank_1)] + InterruptStatusRegisterAccess::Bank1 => GPIO::regs().pcpu_int1().read().bits(), + } +} + +pub(super) fn prepare_pin_pull(_pin: &AnyPin<'_>, _pull_up: bool, _pull_down: bool) {} + +pub(super) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + int_enable as u8 | ((nmi_enable as u8) << 1) +} + +pub(super) fn for_each_interrupt_core(mut f: impl FnMut(crate::system::Cpu)) { + f(crate::system::Cpu::current()); +} + +#[cfg(feature = "rt")] +pub(super) fn enable_additional_default_interrupts( + _interrupt: crate::peripherals::Interrupt, + _priority: crate::interrupt::Priority, +) { +} diff --git a/esp-hal/src/gpio/low_level/v3.rs b/esp-hal/src/gpio/low_level/v3.rs new file mode 100644 index 00000000000..9998b61e3d2 --- /dev/null +++ b/esp-hal/src/gpio/low_level/v3.rs @@ -0,0 +1,35 @@ +use super::{GpioBank, InterruptStatusRegisterAccess}; +use crate::{gpio::AnyPin, peripherals::GPIO}; + +pub(super) fn read_bank_interrupt_status(bank: GpioBank) -> u32 { + match bank { + GpioBank::_0 => GPIO::regs().status().read().bits(), + #[cfg(gpio_has_bank_1)] + GpioBank::_1 => GPIO::regs().status1().read().bits(), + } +} + +pub(super) fn read_interrupt_status(access: InterruptStatusRegisterAccess) -> u32 { + match access { + InterruptStatusRegisterAccess::Bank0 => GPIO::regs().intr_0().read().bits(), + #[cfg(gpio_has_bank_1)] + InterruptStatusRegisterAccess::Bank1 => GPIO::regs().intr1_0().read().bits(), + } +} + +pub(super) fn prepare_pin_pull(_pin: &AnyPin<'_>, _pull_up: bool, _pull_down: bool) {} + +pub(super) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { + int_enable as u8 | ((nmi_enable as u8) << 1) +} + +pub(super) fn for_each_interrupt_core(mut f: impl FnMut(crate::system::Cpu)) { + f(crate::system::Cpu::current()); +} + +#[cfg(feature = "rt")] +pub(super) fn enable_additional_default_interrupts( + _interrupt: crate::peripherals::Interrupt, + _priority: crate::interrupt::Priority, +) { +} diff --git a/esp-hal/src/gpio/mod.rs b/esp-hal/src/gpio/mod.rs index a5766bfeaeb..6ceb9b1a1a0 100644 --- a/esp-hal/src/gpio/mod.rs +++ b/esp-hal/src/gpio/mod.rs @@ -72,7 +72,10 @@ use interconnect::PeripheralOutput; mod asynch; mod embedded_hal_impls; pub(crate) mod interrupt; +mod low_level; use interrupt::*; +pub use low_level::GpioBank; +use low_level::{gpio_intr_enable, is_int_enabled, set_int_enable}; mod placeholder; @@ -80,8 +83,6 @@ use core::fmt::Display; use esp_sync::RawMutex; pub use placeholder::NoPin; -use portable_atomic::AtomicU32; -use strum::EnumCount; use crate::{ asynch::AtomicWaker, @@ -505,123 +506,6 @@ pub trait TouchPin: Pin { fn set_threshold(&self, threshold: u16, _: private::Internal); } -#[doc(hidden)] -#[derive(Debug, Eq, PartialEq, Copy, Clone, Hash, EnumCount)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -pub enum GpioBank { - _0, - #[cfg(gpio_has_bank_1)] - _1, -} - -impl GpioBank { - fn async_operations(self) -> &'static AtomicU32 { - static FLAGS: [AtomicU32; GpioBank::COUNT] = [const { AtomicU32::new(0) }; GpioBank::COUNT]; - - &FLAGS[self as usize] - } - - fn offset(self) -> u8 { - match self { - Self::_0 => 0, - #[cfg(gpio_has_bank_1)] - Self::_1 => 32, - } - } - - fn write_out_en(self, word: u32, enable: bool) { - if enable { - self.write_out_en_set(word); - } else { - self.write_out_en_clear(word); - } - } - - fn write_out_en_clear(self, word: u32) { - match self { - Self::_0 => GPIO::regs() - .enable_w1tc() - .write(|w| unsafe { w.bits(word) }), - #[cfg(gpio_has_bank_1)] - Self::_1 => GPIO::regs() - .enable1_w1tc() - .write(|w| unsafe { w.bits(word) }), - }; - } - - fn write_out_en_set(self, word: u32) { - match self { - Self::_0 => GPIO::regs() - .enable_w1ts() - .write(|w| unsafe { w.bits(word) }), - #[cfg(gpio_has_bank_1)] - Self::_1 => GPIO::regs() - .enable1_w1ts() - .write(|w| unsafe { w.bits(word) }), - }; - } - - fn read_input(self) -> u32 { - match self { - Self::_0 => GPIO::regs().in_().read().bits(), - #[cfg(gpio_has_bank_1)] - Self::_1 => GPIO::regs().in1().read().bits(), - } - } - - fn read_output(self) -> u32 { - match self { - Self::_0 => GPIO::regs().out().read().bits(), - #[cfg(gpio_has_bank_1)] - Self::_1 => GPIO::regs().out1().read().bits(), - } - } - - fn read_interrupt_status(self) -> u32 { - match self { - Self::_0 => GPIO::regs().status().read().bits(), - #[cfg(gpio_has_bank_1)] - Self::_1 => GPIO::regs().status1().read().bits(), - } - } - - fn write_interrupt_status_clear(self, word: u32) { - match self { - Self::_0 => GPIO::regs() - .status_w1tc() - .write(|w| unsafe { w.bits(word) }), - #[cfg(gpio_has_bank_1)] - Self::_1 => GPIO::regs() - .status1_w1tc() - .write(|w| unsafe { w.bits(word) }), - }; - } - - fn write_output(self, word: u32, set: bool) { - if set { - self.write_output_set(word); - } else { - self.write_output_clear(word); - } - } - - fn write_output_set(self, word: u32) { - match self { - Self::_0 => GPIO::regs().out_w1ts().write(|w| unsafe { w.bits(word) }), - #[cfg(gpio_has_bank_1)] - Self::_1 => GPIO::regs().out1_w1ts().write(|w| unsafe { w.bits(word) }), - }; - } - - fn write_output_clear(self, word: u32) { - match self { - Self::_0 => GPIO::regs().out_w1tc().write(|w| unsafe { w.bits(word) }), - #[cfg(gpio_has_bank_1)] - Self::_1 => GPIO::regs().out1_w1tc().write(|w| unsafe { w.bits(word) }), - }; - } -} - /// Any GPIO pin. #[derive(Debug)] #[cfg_attr(feature = "defmt", derive(defmt::Format))] @@ -1696,12 +1580,7 @@ impl private::Sealed for AnyPin<'_> {} impl<'lt> AnyPin<'lt> { fn bank(&self) -> GpioBank { - #[cfg(gpio_has_bank_1)] - if self.number() >= 32 { - return GpioBank::_1; - } - - GpioBank::_0 + low_level::bank(self.number()) } pub(crate) fn disable_usb_pads(&self) { @@ -1930,8 +1809,7 @@ impl<'lt> AnyPin<'lt> { let pull_up = config.pull == Pull::Up; let pull_down = config.pull == Pull::Down; - #[cfg(esp32)] - crate::soc::gpio::errata36(unsafe { self.clone_unchecked() }, pull_up, pull_down); + low_level::prepare_pin_pull(self, pull_up, pull_down); io_mux_reg(self.number()).modify(|_, w| { w.fun_wpd().bit(pull_down); @@ -1963,21 +1841,6 @@ impl<'lt> AnyPin<'lt> { nmi_enable: bool, wake_up_from_light_sleep: bool, ) -> Result<(), WakeConfigError> { - /// Assembles a valid value for the int_ena pin register field. - fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { - cfg_if::cfg_if! { - if #[cfg(esp32)] { - match crate::system::Cpu::current() { - crate::system::Cpu::AppCpu => int_enable as u8 | ((nmi_enable as u8) << 1), - crate::system::Cpu::ProCpu => ((int_enable as u8) << 2) | ((nmi_enable as u8) << 3), - } - } else { - // ESP32 and ESP32-C3 have separate bits for maskable and NMI interrupts. - int_enable as u8 | ((nmi_enable as u8) << 1) - } - } - } - if wake_up_from_light_sleep { match event { Event::AnyEdge | Event::RisingEdge | Event::FallingEdge => { @@ -2008,8 +1871,7 @@ impl<'lt> AnyPin<'lt> { let pull_up = config.pull == Pull::Up; let pull_down = config.pull == Pull::Down; - #[cfg(esp32)] - crate::soc::gpio::errata36(unsafe { self.clone_unchecked() }, pull_up, pull_down); + low_level::prepare_pin_pull(self, pull_up, pull_down); io_mux_reg(self.number()).modify(|_, w| { unsafe { w.fun_drv().bits(config.drive_strength as u8) }; @@ -2369,26 +2231,6 @@ impl RtcPinWithResistors for AnyPin<'_> { } } -/// Set GPIO event listening. -/// -/// - `gpio_num`: the pin to configure -/// - `int_ena`: maskable and non-maskable CPU interrupt bits. None to leave unchanged. -/// - `int_type`: interrupt type, see [Event] (or 0 to disable) -/// - `wake_up_from_light_sleep`: whether to wake up from light sleep -fn set_int_enable(gpio_num: u8, int_ena: Option, int_type: u8, wake_up_from_light_sleep: bool) { - GPIO::regs().pin(gpio_num as usize).modify(|_, w| unsafe { - if let Some(int_ena) = int_ena { - w.int_ena().bits(int_ena); - } - w.int_type().bits(int_type); - w.wakeup_enable().bit(wake_up_from_light_sleep) - }); -} - -fn is_int_enabled(gpio_num: u8) -> bool { - GPIO::regs().pin(gpio_num as usize).read().int_ena().bits() != 0 -} - for_each_gpio! { ($n:literal, $gpio:ident $af_ins:tt $af_outs:tt ([Input] $output:tt)) => { impl InputPin for crate::peripherals::$gpio<'_> { diff --git a/esp-hal/src/uart/compat.rs b/esp-hal/src/uart/compat.rs index 654efe8a721..1fcda0963d0 100644 --- a/esp-hal/src/uart/compat.rs +++ b/esp-hal/src/uart/compat.rs @@ -1,7 +1,16 @@ -#[cfg(feature = "unstable")] -use super::{Async, Config, ConfigError, IoError, RxError, TxError, UartRx}; -use super::{Blocking, DriverMode, Uart, UartTx}; -#[cfg(feature = "unstable")] +use super::{ + Async, + Blocking, + Config, + ConfigError, + DriverMode, + IoError, + RxError, + TxError, + Uart, + UartRx, + UartTx, +}; use crate::interrupt::InterruptHandler; #[instability::unstable] diff --git a/esp-metadata-generated/src/_build_script_utils.rs b/esp-metadata-generated/src/_build_script_utils.rs index dc947c47b97..08dc7b1c71b 100644 --- a/esp-metadata-generated/src/_build_script_utils.rs +++ b/esp-metadata-generated/src/_build_script_utils.rs @@ -322,6 +322,7 @@ impl Chip { "soc_has_dma_spi3", "soc_has_dma_i2s0", "soc_has_dma_i2s1", + "gpio_version=\"1\"", "gpio_has_bank_1", "gpio_gpio_function=\"2\"", "gpio_constant_0_input=\"48\"", @@ -535,6 +536,7 @@ impl Chip { "cargo:rustc-cfg=soc_has_dma_spi3", "cargo:rustc-cfg=soc_has_dma_i2s0", "cargo:rustc-cfg=soc_has_dma_i2s1", + "cargo:rustc-cfg=gpio_version=\"1\"", "cargo:rustc-cfg=gpio_has_bank_1", "cargo:rustc-cfg=gpio_gpio_function=\"2\"", "cargo:rustc-cfg=gpio_constant_0_input=\"48\"", @@ -864,6 +866,7 @@ impl Chip { "uart_uart1", "assist_debug_has_sp_monitor", "bt_controller=\"npl\"", + "dedicated_gpio_version=\"riscv_v1\"", "dma_kind=\"gdma\"", "dma_supports_mem2mem", "dma_max_priority=\"9\"", @@ -875,6 +878,7 @@ impl Chip { "ecc_has_finite_field_division", "ecc_has_curve_p192", "ecc_has_curve_p256", + "gpio_version=\"2\"", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"31\"", "gpio_constant_1_input=\"30\"", @@ -1030,6 +1034,7 @@ impl Chip { "cargo:rustc-cfg=uart_uart1", "cargo:rustc-cfg=assist_debug_has_sp_monitor", "cargo:rustc-cfg=bt_controller=\"npl\"", + "cargo:rustc-cfg=dedicated_gpio_version=\"riscv_v1\"", "cargo:rustc-cfg=dma_kind=\"gdma\"", "cargo:rustc-cfg=dma_supports_mem2mem", "cargo:rustc-cfg=dma_max_priority=\"9\"", @@ -1041,6 +1046,7 @@ impl Chip { "cargo:rustc-cfg=ecc_has_finite_field_division", "cargo:rustc-cfg=ecc_has_curve_p192", "cargo:rustc-cfg=ecc_has_curve_p256", + "cargo:rustc-cfg=gpio_version=\"2\"", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"31\"", "cargo:rustc-cfg=gpio_constant_1_input=\"30\"", @@ -1334,6 +1340,7 @@ impl Chip { "assist_debug_has_sp_monitor", "assist_debug_has_region_monitor", "bt_controller=\"btdm\"", + "dedicated_gpio_version=\"riscv_v1\"", "dma_kind=\"gdma\"", "dma_supports_mem2mem", "dma_max_priority=\"9\"", @@ -1343,6 +1350,7 @@ impl Chip { "soc_has_dma_ch0", "soc_has_dma_ch1", "soc_has_dma_ch2", + "gpio_version=\"2\"", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"31\"", "gpio_constant_1_input=\"30\"", @@ -1551,6 +1559,7 @@ impl Chip { "cargo:rustc-cfg=assist_debug_has_sp_monitor", "cargo:rustc-cfg=assist_debug_has_region_monitor", "cargo:rustc-cfg=bt_controller=\"btdm\"", + "cargo:rustc-cfg=dedicated_gpio_version=\"riscv_v1\"", "cargo:rustc-cfg=dma_kind=\"gdma\"", "cargo:rustc-cfg=dma_supports_mem2mem", "cargo:rustc-cfg=dma_max_priority=\"9\"", @@ -1560,6 +1569,7 @@ impl Chip { "cargo:rustc-cfg=soc_has_dma_ch0", "cargo:rustc-cfg=soc_has_dma_ch1", "cargo:rustc-cfg=soc_has_dma_ch2", + "cargo:rustc-cfg=gpio_version=\"2\"", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"31\"", "cargo:rustc-cfg=gpio_constant_1_input=\"30\"", @@ -1905,6 +1915,7 @@ impl Chip { "assist_debug_has_sp_monitor", "assist_debug_has_region_monitor", "bt_controller=\"npl\"", + "dedicated_gpio_version=\"riscv_v1\"", "dma_kind=\"gdma\"", "dma_supports_mem2mem", "dma_can_access_psram", @@ -1924,6 +1935,7 @@ impl Chip { "ecc_has_curve_p192", "ecc_has_curve_p256", "ecc_has_curve_p384", + "gpio_version=\"2\"", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"96\"", "gpio_constant_1_input=\"64\"", @@ -2170,6 +2182,7 @@ impl Chip { "cargo:rustc-cfg=assist_debug_has_sp_monitor", "cargo:rustc-cfg=assist_debug_has_region_monitor", "cargo:rustc-cfg=bt_controller=\"npl\"", + "cargo:rustc-cfg=dedicated_gpio_version=\"riscv_v1\"", "cargo:rustc-cfg=dma_kind=\"gdma\"", "cargo:rustc-cfg=dma_supports_mem2mem", "cargo:rustc-cfg=dma_can_access_psram", @@ -2189,6 +2202,7 @@ impl Chip { "cargo:rustc-cfg=ecc_has_curve_p192", "cargo:rustc-cfg=ecc_has_curve_p256", "cargo:rustc-cfg=ecc_has_curve_p384", + "cargo:rustc-cfg=gpio_version=\"2\"", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"96\"", "cargo:rustc-cfg=gpio_constant_1_input=\"64\"", @@ -2595,6 +2609,7 @@ impl Chip { "assist_debug_has_sp_monitor", "assist_debug_has_region_monitor", "bt_controller=\"npl\"", + "dedicated_gpio_version=\"riscv_v1\"", "dma_kind=\"gdma\"", "dma_supports_mem2mem", "dma_separate_in_out_interrupts", @@ -2609,6 +2624,7 @@ impl Chip { "ecc_has_memory_clock_gate", "ecc_has_curve_p192", "ecc_has_curve_p256", + "gpio_version=\"2\"", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"60\"", "gpio_constant_1_input=\"56\"", @@ -2882,6 +2898,7 @@ impl Chip { "cargo:rustc-cfg=assist_debug_has_sp_monitor", "cargo:rustc-cfg=assist_debug_has_region_monitor", "cargo:rustc-cfg=bt_controller=\"npl\"", + "cargo:rustc-cfg=dedicated_gpio_version=\"riscv_v1\"", "cargo:rustc-cfg=dma_kind=\"gdma\"", "cargo:rustc-cfg=dma_supports_mem2mem", "cargo:rustc-cfg=dma_separate_in_out_interrupts", @@ -2896,6 +2913,7 @@ impl Chip { "cargo:rustc-cfg=ecc_has_memory_clock_gate", "cargo:rustc-cfg=ecc_has_curve_p192", "cargo:rustc-cfg=ecc_has_curve_p256", + "cargo:rustc-cfg=gpio_version=\"2\"", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"60\"", "cargo:rustc-cfg=gpio_constant_1_input=\"56\"", @@ -3262,6 +3280,7 @@ impl Chip { "assist_debug_has_sp_monitor", "assist_debug_has_region_monitor", "bt_controller=\"npl\"", + "dedicated_gpio_version=\"riscv_v1\"", "dma_kind=\"gdma\"", "dma_supports_mem2mem", "dma_separate_in_out_interrupts", @@ -3279,6 +3298,7 @@ impl Chip { "ecc_has_point_addition", "ecc_has_curve_p192", "ecc_has_curve_p256", + "gpio_version=\"2\"", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"96\"", "gpio_constant_1_input=\"64\"", @@ -3472,6 +3492,7 @@ impl Chip { "cargo:rustc-cfg=assist_debug_has_sp_monitor", "cargo:rustc-cfg=assist_debug_has_region_monitor", "cargo:rustc-cfg=bt_controller=\"npl\"", + "cargo:rustc-cfg=dedicated_gpio_version=\"riscv_v1\"", "cargo:rustc-cfg=dma_kind=\"gdma\"", "cargo:rustc-cfg=dma_supports_mem2mem", "cargo:rustc-cfg=dma_separate_in_out_interrupts", @@ -3489,6 +3510,7 @@ impl Chip { "cargo:rustc-cfg=ecc_has_point_addition", "cargo:rustc-cfg=ecc_has_curve_p192", "cargo:rustc-cfg=ecc_has_curve_p256", + "cargo:rustc-cfg=gpio_version=\"2\"", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"96\"", "cargo:rustc-cfg=gpio_constant_1_input=\"64\"", @@ -3855,6 +3877,7 @@ impl Chip { "assist_debug_has_sp_monitor", "assist_debug_has_region_monitor", "bt_controller=\"npl\"", + "dedicated_gpio_version=\"riscv_v1\"", "dma_kind=\"gdma\"", "dma_supports_mem2mem", "dma_separate_in_out_interrupts", @@ -3873,6 +3896,7 @@ impl Chip { "ecc_has_point_addition", "ecc_has_curve_p192", "ecc_has_curve_p256", + "gpio_version=\"2\"", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"60\"", "gpio_constant_1_input=\"56\"", @@ -4109,6 +4133,7 @@ impl Chip { "cargo:rustc-cfg=assist_debug_has_sp_monitor", "cargo:rustc-cfg=assist_debug_has_region_monitor", "cargo:rustc-cfg=bt_controller=\"npl\"", + "cargo:rustc-cfg=dedicated_gpio_version=\"riscv_v1\"", "cargo:rustc-cfg=dma_kind=\"gdma\"", "cargo:rustc-cfg=dma_supports_mem2mem", "cargo:rustc-cfg=dma_separate_in_out_interrupts", @@ -4127,6 +4152,7 @@ impl Chip { "cargo:rustc-cfg=ecc_has_point_addition", "cargo:rustc-cfg=ecc_has_curve_p192", "cargo:rustc-cfg=ecc_has_curve_p256", + "cargo:rustc-cfg=gpio_version=\"2\"", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"60\"", "cargo:rustc-cfg=gpio_constant_1_input=\"56\"", @@ -4439,6 +4465,7 @@ impl Chip { "ecc_has_curve_p256", "ecc_has_curve_p384", "ethernet_mii_via_gpio_matrix", + "gpio_version=\"3\"", "gpio_has_bank_1", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"62\"", @@ -4618,6 +4645,7 @@ impl Chip { "cargo:rustc-cfg=ecc_has_curve_p256", "cargo:rustc-cfg=ecc_has_curve_p384", "cargo:rustc-cfg=ethernet_mii_via_gpio_matrix", + "cargo:rustc-cfg=gpio_version=\"3\"", "cargo:rustc-cfg=gpio_has_bank_1", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"62\"", @@ -5056,6 +5084,7 @@ impl Chip { "aes_dma_mode_gcm", "aes_has_split_text_registers", "aes_endianness_configurable", + "dedicated_gpio_version=\"esp32s2\"", "dedicated_gpio_needs_initialization", "dma_kind=\"pdma\"", "dma_supports_mem2mem", @@ -5066,6 +5095,7 @@ impl Chip { "soc_has_dma_i2s0", "soc_has_dma_crypto", "soc_has_dma_copy", + "gpio_version=\"2\"", "gpio_has_bank_1", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"60\"", @@ -5284,6 +5314,7 @@ impl Chip { "cargo:rustc-cfg=aes_dma_mode_gcm", "cargo:rustc-cfg=aes_has_split_text_registers", "cargo:rustc-cfg=aes_endianness_configurable", + "cargo:rustc-cfg=dedicated_gpio_version=\"esp32s2\"", "cargo:rustc-cfg=dedicated_gpio_needs_initialization", "cargo:rustc-cfg=dma_kind=\"pdma\"", "cargo:rustc-cfg=dma_supports_mem2mem", @@ -5294,6 +5325,7 @@ impl Chip { "cargo:rustc-cfg=soc_has_dma_i2s0", "cargo:rustc-cfg=soc_has_dma_crypto", "cargo:rustc-cfg=soc_has_dma_copy", + "cargo:rustc-cfg=gpio_version=\"2\"", "cargo:rustc-cfg=gpio_has_bank_1", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"60\"", @@ -5723,6 +5755,7 @@ impl Chip { "aes_has_split_text_registers", "assist_debug_has_region_monitor", "bt_controller=\"btdm\"", + "dedicated_gpio_version=\"esp32s3\"", "dedicated_gpio_needs_initialization", "dma_kind=\"gdma\"", "dma_supports_mem2mem", @@ -5738,6 +5771,7 @@ impl Chip { "soc_has_dma_ch2", "soc_has_dma_ch3", "soc_has_dma_ch4", + "gpio_version=\"2\"", "gpio_has_bank_1", "gpio_gpio_function=\"1\"", "gpio_constant_0_input=\"60\"", @@ -5984,6 +6018,7 @@ impl Chip { "cargo:rustc-cfg=aes_has_split_text_registers", "cargo:rustc-cfg=assist_debug_has_region_monitor", "cargo:rustc-cfg=bt_controller=\"btdm\"", + "cargo:rustc-cfg=dedicated_gpio_version=\"esp32s3\"", "cargo:rustc-cfg=dedicated_gpio_needs_initialization", "cargo:rustc-cfg=dma_kind=\"gdma\"", "cargo:rustc-cfg=dma_supports_mem2mem", @@ -5999,6 +6034,7 @@ impl Chip { "cargo:rustc-cfg=soc_has_dma_ch2", "cargo:rustc-cfg=soc_has_dma_ch3", "cargo:rustc-cfg=soc_has_dma_ch4", + "cargo:rustc-cfg=gpio_version=\"2\"", "cargo:rustc-cfg=gpio_has_bank_1", "cargo:rustc-cfg=gpio_gpio_function=\"1\"", "cargo:rustc-cfg=gpio_constant_0_input=\"60\"", @@ -6799,6 +6835,7 @@ pub fn emit_check_cfg_directives() { println!("cargo:rustc-check-cfg=cfg(soc_has_clock_node_crypto_pwm_clk)"); println!("cargo:rustc-check-cfg=cfg(bt_controller, values(\"btdm\",\"npl\"))"); println!("cargo:rustc-check-cfg=cfg(dma_kind, values(\"pdma\",\"gdma\"))"); + println!("cargo:rustc-check-cfg=cfg(gpio_version, values(\"1\",\"2\",\"3\"))"); println!("cargo:rustc-check-cfg=cfg(gpio_gpio_function, values(\"2\",\"1\"))"); println!( "cargo:rustc-check-cfg=cfg(gpio_constant_0_input, \ @@ -6860,6 +6897,10 @@ pub fn emit_check_cfg_directives() { println!("cargo:rustc-check-cfg=cfg(uart_ram_size, values(\"128\"))"); println!("cargo:rustc-check-cfg=cfg(uart_version, values(\"1\",\"2\"))"); println!("cargo:rustc-check-cfg=cfg(wifi_mac_version, values(\"1\",\"3\",\"2\"))"); + println!( + "cargo:rustc-check-cfg=cfg(dedicated_gpio_version, \ + values(\"riscv_v1\",\"esp32s2\",\"esp32s3\"))" + ); println!("cargo:rustc-check-cfg=cfg(dma_max_priority, values(\"9\",\"5\"))"); println!("cargo:rustc-check-cfg=cfg(dma_gdma_version, values(\"1\",\"2\"))"); println!("cargo:rustc-check-cfg=cfg(phy_backed_up_digital_register_count, values(\"21\"))"); diff --git a/esp-metadata-generated/src/_generated_esp32.rs b/esp-metadata-generated/src/_generated_esp32.rs index 483de5ad739..4663eb5c9e7 100644 --- a/esp-metadata-generated/src/_generated_esp32.rs +++ b/esp-metadata-generated/src/_generated_esp32.rs @@ -82,6 +82,12 @@ macro_rules! property { ("ethernet.mii_via_gpio_matrix") => { false }; + ("gpio.version") => { + 1 + }; + ("gpio.version", str) => { + stringify!(1) + }; ("gpio.has_bank_1") => { true }; diff --git a/esp-metadata-generated/src/_generated_esp32c2.rs b/esp-metadata-generated/src/_generated_esp32c2.rs index 840b6df8f9d..742d13d2968 100644 --- a/esp-metadata-generated/src/_generated_esp32c2.rs +++ b/esp-metadata-generated/src/_generated_esp32c2.rs @@ -61,6 +61,9 @@ macro_rules! property { ("bt.controller") => { "npl" }; + ("dedicated_gpio.version") => { + "riscv_v1" + }; ("dedicated_gpio.needs_initialization") => { false }; @@ -112,6 +115,12 @@ macro_rules! property { ("ecc.mem_block_size") => { 32 }; + ("gpio.version") => { + 2 + }; + ("gpio.version", str) => { + stringify!(2) + }; ("gpio.has_bank_1") => { false }; diff --git a/esp-metadata-generated/src/_generated_esp32c3.rs b/esp-metadata-generated/src/_generated_esp32c3.rs index 56442b383a9..6aa81a36462 100644 --- a/esp-metadata-generated/src/_generated_esp32c3.rs +++ b/esp-metadata-generated/src/_generated_esp32c3.rs @@ -70,6 +70,9 @@ macro_rules! property { ("bt.controller") => { "btdm" }; + ("dedicated_gpio.version") => { + "riscv_v1" + }; ("dedicated_gpio.needs_initialization") => { false }; @@ -106,6 +109,12 @@ macro_rules! property { ("dma.gdma_version", str) => { stringify!(1) }; + ("gpio.version") => { + 2 + }; + ("gpio.version", str) => { + stringify!(2) + }; ("gpio.has_bank_1") => { false }; diff --git a/esp-metadata-generated/src/_generated_esp32c5.rs b/esp-metadata-generated/src/_generated_esp32c5.rs index 792e48c6b20..51ffedae905 100644 --- a/esp-metadata-generated/src/_generated_esp32c5.rs +++ b/esp-metadata-generated/src/_generated_esp32c5.rs @@ -70,6 +70,9 @@ macro_rules! property { ("bt.controller") => { "npl" }; + ("dedicated_gpio.version") => { + "riscv_v1" + }; ("dedicated_gpio.needs_initialization") => { false }; @@ -121,6 +124,12 @@ macro_rules! property { ("ecc.mem_block_size") => { 48 }; + ("gpio.version") => { + 2 + }; + ("gpio.version", str) => { + stringify!(2) + }; ("gpio.has_bank_1") => { false }; diff --git a/esp-metadata-generated/src/_generated_esp32c6.rs b/esp-metadata-generated/src/_generated_esp32c6.rs index 3a59a0cacd4..7a33641d27a 100644 --- a/esp-metadata-generated/src/_generated_esp32c6.rs +++ b/esp-metadata-generated/src/_generated_esp32c6.rs @@ -70,6 +70,9 @@ macro_rules! property { ("bt.controller") => { "npl" }; + ("dedicated_gpio.version") => { + "riscv_v1" + }; ("dedicated_gpio.needs_initialization") => { false }; @@ -121,6 +124,12 @@ macro_rules! property { ("ecc.mem_block_size") => { 32 }; + ("gpio.version") => { + 2 + }; + ("gpio.version", str) => { + stringify!(2) + }; ("gpio.has_bank_1") => { false }; diff --git a/esp-metadata-generated/src/_generated_esp32c61.rs b/esp-metadata-generated/src/_generated_esp32c61.rs index 0ee1b1fd291..112704308ee 100644 --- a/esp-metadata-generated/src/_generated_esp32c61.rs +++ b/esp-metadata-generated/src/_generated_esp32c61.rs @@ -61,6 +61,9 @@ macro_rules! property { ("bt.controller") => { "npl" }; + ("dedicated_gpio.version") => { + "riscv_v1" + }; ("dedicated_gpio.needs_initialization") => { false }; @@ -112,6 +115,12 @@ macro_rules! property { ("ecc.mem_block_size") => { 32 }; + ("gpio.version") => { + 2 + }; + ("gpio.version", str) => { + stringify!(2) + }; ("gpio.has_bank_1") => { false }; diff --git a/esp-metadata-generated/src/_generated_esp32h2.rs b/esp-metadata-generated/src/_generated_esp32h2.rs index 0dc3afec27d..4936fd9467a 100644 --- a/esp-metadata-generated/src/_generated_esp32h2.rs +++ b/esp-metadata-generated/src/_generated_esp32h2.rs @@ -70,6 +70,9 @@ macro_rules! property { ("bt.controller") => { "npl" }; + ("dedicated_gpio.version") => { + "riscv_v1" + }; ("dedicated_gpio.needs_initialization") => { false }; @@ -121,6 +124,12 @@ macro_rules! property { ("ecc.mem_block_size") => { 32 }; + ("gpio.version") => { + 2 + }; + ("gpio.version", str) => { + stringify!(2) + }; ("gpio.has_bank_1") => { false }; diff --git a/esp-metadata-generated/src/_generated_esp32p4.rs b/esp-metadata-generated/src/_generated_esp32p4.rs index 4660f358b87..ddfc449be62 100644 --- a/esp-metadata-generated/src/_generated_esp32p4.rs +++ b/esp-metadata-generated/src/_generated_esp32p4.rs @@ -112,6 +112,12 @@ macro_rules! property { ("ethernet.mii_via_gpio_matrix") => { true }; + ("gpio.version") => { + 3 + }; + ("gpio.version", str) => { + stringify!(3) + }; ("gpio.has_bank_1") => { true }; diff --git a/esp-metadata-generated/src/_generated_esp32s2.rs b/esp-metadata-generated/src/_generated_esp32s2.rs index d497cfced08..8e258db5c01 100644 --- a/esp-metadata-generated/src/_generated_esp32s2.rs +++ b/esp-metadata-generated/src/_generated_esp32s2.rs @@ -61,6 +61,9 @@ macro_rules! property { ("aes.endianness_configurable") => { true }; + ("dedicated_gpio.version") => { + "esp32s2" + }; ("dedicated_gpio.needs_initialization") => { true }; @@ -85,6 +88,12 @@ macro_rules! property { ("dma.separate_in_out_interrupts") => { false }; + ("gpio.version") => { + 2 + }; + ("gpio.version", str) => { + stringify!(2) + }; ("gpio.has_bank_1") => { true }; diff --git a/esp-metadata-generated/src/_generated_esp32s3.rs b/esp-metadata-generated/src/_generated_esp32s3.rs index d2b1b779d85..875457de944 100644 --- a/esp-metadata-generated/src/_generated_esp32s3.rs +++ b/esp-metadata-generated/src/_generated_esp32s3.rs @@ -70,6 +70,9 @@ macro_rules! property { ("bt.controller") => { "btdm" }; + ("dedicated_gpio.version") => { + "esp32s3" + }; ("dedicated_gpio.needs_initialization") => { true }; @@ -106,6 +109,12 @@ macro_rules! property { ("dma.gdma_version", str) => { stringify!(1) }; + ("gpio.version") => { + 2 + }; + ("gpio.version", str) => { + stringify!(2) + }; ("gpio.has_bank_1") => { true }; diff --git a/esp-metadata/devices/esp32.toml b/esp-metadata/devices/esp32.toml index 332183eb9f6..520fff05039 100644 --- a/esp-metadata/devices/esp32.toml +++ b/esp-metadata/devices/esp32.toml @@ -348,6 +348,7 @@ engines = [ ] [device.gpio] +version = 1 support_status = "supported" has_bank_1 = true gpio_function = 2 diff --git a/esp-metadata/devices/esp32c2.toml b/esp-metadata/devices/esp32c2.toml index 121628e90d4..b8754f56f45 100644 --- a/esp-metadata/devices/esp32c2.toml +++ b/esp-metadata/devices/esp32c2.toml @@ -248,6 +248,7 @@ curves = [ zero_extend_writes = true [device.gpio] +version = 2 support_status = "supported" gpio_function = 1 constant_0_input = 0x1f @@ -382,6 +383,7 @@ output_signals = [ ] [device.dedicated_gpio] +version = "riscv_v1" support_status = "partial" channels = [["CPU_GPIO_0", "CPU_GPIO_1", "CPU_GPIO_2", "CPU_GPIO_3", "CPU_GPIO_4", "CPU_GPIO_5", "CPU_GPIO_6", "CPU_GPIO_7"]] diff --git a/esp-metadata/devices/esp32c3.toml b/esp-metadata/devices/esp32c3.toml index e0c7b31a6c3..5aa01f133ed 100644 --- a/esp-metadata/devices/esp32c3.toml +++ b/esp-metadata/devices/esp32c3.toml @@ -272,6 +272,7 @@ engines = [ ] [device.gpio] +version = 2 support_status = "supported" gpio_function = 1 constant_0_input = 0x1f @@ -433,6 +434,7 @@ output_signals = [ ] [device.dedicated_gpio] +version = "riscv_v1" support_status = "partial" channels = [["CPU_GPIO_0", "CPU_GPIO_1", "CPU_GPIO_2", "CPU_GPIO_3", "CPU_GPIO_4", "CPU_GPIO_5", "CPU_GPIO_6", "CPU_GPIO_7"]] diff --git a/esp-metadata/devices/esp32c5.toml b/esp-metadata/devices/esp32c5.toml index 5fec9d08bc2..a0f46df2208 100644 --- a/esp-metadata/devices/esp32c5.toml +++ b/esp-metadata/devices/esp32c5.toml @@ -336,6 +336,7 @@ has_memory_clock_gate = true supports_enhanced_security = true [device.gpio] +version = 2 support_status = "partial" gpio_function = 1 constant_0_input = 0x60 @@ -541,6 +542,7 @@ output_signals = [ ] [device.dedicated_gpio] +version = "riscv_v1" support_status = "partial" channels = [["CPU_GPIO_0", "CPU_GPIO_1", "CPU_GPIO_2", "CPU_GPIO_3", "CPU_GPIO_4", "CPU_GPIO_5", "CPU_GPIO_6", "CPU_GPIO_7"]] diff --git a/esp-metadata/devices/esp32c6.toml b/esp-metadata/devices/esp32c6.toml index 79e0ce5bcba..c39d5bbf9af 100644 --- a/esp-metadata/devices/esp32c6.toml +++ b/esp-metadata/devices/esp32c6.toml @@ -363,6 +363,7 @@ zero_extend_writes = true has_memory_clock_gate = true [device.gpio] +version = 2 support_status = "supported" gpio_function = 1 constant_0_input = 0x3c @@ -632,6 +633,7 @@ output_signals = [ ] [device.dedicated_gpio] +version = "riscv_v1" support_status = "partial" channels = [["CPU_GPIO_0", "CPU_GPIO_1", "CPU_GPIO_2", "CPU_GPIO_3", "CPU_GPIO_4", "CPU_GPIO_5", "CPU_GPIO_6", "CPU_GPIO_7"]] diff --git a/esp-metadata/devices/esp32c61.toml b/esp-metadata/devices/esp32c61.toml index b725d63cef6..987a2930d96 100644 --- a/esp-metadata/devices/esp32c61.toml +++ b/esp-metadata/devices/esp32c61.toml @@ -229,6 +229,7 @@ instances = [{ name = "timg0" }, { name = "timg1" }] timg_has_divcnt_rst = true [device.gpio] +version = 2 support_status = "partial" gpio_function = 1 constant_0_input = 0x60 @@ -364,6 +365,7 @@ output_signals = [ ] [device.dedicated_gpio] +version = "riscv_v1" support_status = "partial" channels = [["CPU_GPIO_0", "CPU_GPIO_1", "CPU_GPIO_2", "CPU_GPIO_3", "CPU_GPIO_4", "CPU_GPIO_5", "CPU_GPIO_6", "CPU_GPIO_7"]] diff --git a/esp-metadata/devices/esp32h2.toml b/esp-metadata/devices/esp32h2.toml index 4ebc5dc7c93..c4e75430d5d 100644 --- a/esp-metadata/devices/esp32h2.toml +++ b/esp-metadata/devices/esp32h2.toml @@ -323,6 +323,7 @@ has_memory_clock_gate = true supports_enhanced_security = true # only after revision 1.2 [device.gpio] +version = 2 support_status = "supported" gpio_function = 1 constant_0_input = 0x3c @@ -533,6 +534,7 @@ output_signals = [ ] [device.dedicated_gpio] +version = "riscv_v1" support_status = "partial" channels = [["CPU_GPIO_0", "CPU_GPIO_1", "CPU_GPIO_2", "CPU_GPIO_3", "CPU_GPIO_4", "CPU_GPIO_5", "CPU_GPIO_6", "CPU_GPIO_7"]] diff --git a/esp-metadata/devices/esp32p4.toml b/esp-metadata/devices/esp32p4.toml index f5bd89a21ce..4f6bb262659 100644 --- a/esp-metadata/devices/esp32p4.toml +++ b/esp-metadata/devices/esp32p4.toml @@ -529,6 +529,7 @@ has_memory_clock_gate = true supports_enhanced_security = true [device.gpio] +version = 3 support_status = "partial" has_bank_1 = true gpio_function = 1 diff --git a/esp-metadata/devices/esp32s2.toml b/esp-metadata/devices/esp32s2.toml index 3114231d390..6d86f136437 100644 --- a/esp-metadata/devices/esp32s2.toml +++ b/esp-metadata/devices/esp32s2.toml @@ -297,6 +297,7 @@ engines = [ ] [device.gpio] +version = 2 support_status = "supported" has_bank_1 = true gpio_function = 1 @@ -560,6 +561,7 @@ output_signals = [ ] [device.dedicated_gpio] +version = "esp32s2" support_status = "partial" channels = [["PRO_ALONEGPIO0", "PRO_ALONEGPIO1", "PRO_ALONEGPIO2", "PRO_ALONEGPIO3", "PRO_ALONEGPIO4", "PRO_ALONEGPIO5", "PRO_ALONEGPIO6", "PRO_ALONEGPIO7"]] needs_initialization = true diff --git a/esp-metadata/devices/esp32s3.toml b/esp-metadata/devices/esp32s3.toml index b2d1a37abc2..7dd039bf502 100644 --- a/esp-metadata/devices/esp32s3.toml +++ b/esp-metadata/devices/esp32s3.toml @@ -310,6 +310,7 @@ engines = [ ] [device.gpio] +version = 2 support_status = "supported" has_bank_1 = true gpio_function = 1 @@ -746,6 +747,7 @@ output_signals = [ ] [device.dedicated_gpio] +version = "esp32s3" support_status = "partial" channels = [ ["PRO_ALONEGPIO0", "PRO_ALONEGPIO1", "PRO_ALONEGPIO2", "PRO_ALONEGPIO3", "PRO_ALONEGPIO4", "PRO_ALONEGPIO5", "PRO_ALONEGPIO6", "PRO_ALONEGPIO7"], diff --git a/esp-metadata/src/cfg.rs b/esp-metadata/src/cfg.rs index 44f49d80f15..40ce9e85c22 100644 --- a/esp-metadata/src/cfg.rs +++ b/esp-metadata/src/cfg.rs @@ -331,6 +331,8 @@ driver_configs![ driver: dedicated_gpio, name: "Dedicated GPIO", properties: { + /// Low-level access generation derived from CPU instruction/CSR support. + version: String, #[serde(default)] needs_initialization: bool, #[serde(flatten)] @@ -402,6 +404,8 @@ driver_configs![ name: "GPIO", has_computed_properties: true, properties: { + /// Digital GPIO register-layout generation derived from the chip SVD. + version: u32, #[serde(default)] has_bank_1: bool, gpio_function: u32,