diff --git a/litex/soc/cores/gpio.py b/litex/soc/cores/gpio.py
index a2541072f7..0a4a86d2fb 100644
--- a/litex/soc/cores/gpio.py
+++ b/litex/soc/cores/gpio.py
@@ -43,3 +43,21 @@ def __init__(self, pads):
         self.comb += t.oe.eq(self._oe.storage)
         self.comb += t.o.eq(self._out.storage)
         self.specials += MultiReg(t.i, self._in.status)
+
+# GPIO Bidirectional -------------------------------------------------------------------------------
+
+class GPIOBidirectional(Module, AutoCSR):
+    def __init__(self, pads):
+        self._pins_in = CSRStatus(len(pads))
+        self._pins_out = CSRStorage(len(pads))
+        self._pins_oe = CSRStorage(len(pads))
+        gpio_pins_t = [None] * len(pads)
+        bit = 0
+        for pin_group in pads.layout:
+            for pin in getattr(pads, pin_group[0]):
+                gpio_pins_t[bit] = TSTriple()
+                self.specials += gpio_pins_t[bit].get_tristate(pin)
+                self.comb += gpio_pins_t[bit].o.eq(self._pins_out.storage[bit])
+                self.comb += gpio_pins_t[bit].oe.eq(self._pins_oe.storage[bit])
+                self.comb += self._pins_in.status[bit].eq(gpio_pins_t[bit].i)
+                bit=bit+1