Merge commit 'fab9d04' into cyw4373

Author: xoviat

embassy-stm32/src/sdmmc/mod.rs

@@ -784,8 +784,6 @@ impl<'d> Sdmmc<'d> {
 
         // Use buffer.len() not size_of_val: Aligned<A4, [u8]> is #[repr(C)]
         // with alignment 4, so size_of_val rounds up to a multiple of 4.
-        // This causes DLEN to exceed the CMD53 byte count for non-4-aligned
-        // sizes, resulting in data timeouts.
         regs.dlenr().write(|w| w.set_datalength(buffer.len() as u32));
 
         // SAFETY: No other functions use the dma
@@ -846,6 +844,8 @@ impl<'d> Sdmmc<'d> {
         self.wait_idle();
         self.clear_interrupt_flags();
 
+        // Use buffer.len() not size_of_val: Aligned<A4, [u8]> is #[repr(C)]
+        // with alignment 4, so size_of_val rounds up to a multiple of 4.
         regs.dlenr().write(|w| w.set_datalength(buffer.len() as u32));
 
         // SAFETY: No other functions use the dma
@@ -905,6 +905,12 @@ impl<'d> Sdmmc<'d> {
     }
 
     fn init_idle(&mut self) -> Result<CommandResponse<Rz>, Error> {
+        self.start_clocks()?;
+        self.cmd(common_cmd::idle(), true, false)
+    }
+
+    /// Start the SDMMC clock at 400 kHz without performing any card initialization.
+    pub fn start_clocks(&mut self) -> Result<(), Error> {
         let regs = self.info.regs;
 
         self.clkcr_set_clkdiv(SD_INIT_FREQ, BusWidth::One)?;
@@ -916,7 +922,7 @@ impl<'d> Sdmmc<'d> {
         // Wait 74 cycles
         block_for_us((74_000_000 / SD_INIT_FREQ.0) as u64);
 
-        self.cmd(common_cmd::idle(), true, false)
+        Ok(())
     }
 
     /// Start the SDMMC clock at 400 kHz without performing any card initialization.

embassy-stm32/src/sdmmc/sdio.rs

@@ -5,7 +5,7 @@ use core::task::Poll;
 
 use aligned::{A4, Aligned};
 #[cfg(feature = "time")]
-use embassy_time::Timer;
+use embassy_time::{Duration, Ticker};
 use sdio_host::common_cmd::{R1, Resp, cmd};
 use sdio_host::sd::{BusWidth, OCR, RCA, SD};
 use sdio_host::{Cmd, sd_cmd};
@@ -110,30 +110,25 @@ impl<'a, 'b> SerialDataInterface<'a, 'b> {
         // the SDMMC_CK frequency must be no more than 400 kHz.
         self.sdmmc.init_idle()?;
 
-        // Retry CMD5 (IO_SEND_OP_COND) up to 500 times with 1 ms delays, matching the
-        // Infineon/Cypress WHD driver (SDIO_ENUMERATION_TRIES / SDIO_RETRY_DELAY_MS).
-        // The SDMMC peripheral stays POWER_ON throughout so the card clock keeps running,
-        // which is required for SDIO chips (e.g. CYW4373) that need the clock during
-        // their internal power-up sequence before they can ACK CMD5.
-        let _ocr: OCR<SD> = {
-            let mut result = Err(Error::Timeout);
-            for _ in 0..500u16 {
-                match self.sdmmc.cmd(io_send_op_cond(false, 0x0), false, false) {
-                    Ok(r) => {
-                        result = Ok(r);
-                        break;
-                    }
-                    Err(Error::Timeout) => {
-                        #[cfg(feature = "time")]
-                        Timer::after_millis(1).await;
-                        #[cfg(not(feature = "time"))]
-                        crate::block_for_us(1000);
-                    }
-                    Err(e) => return Err(e),
+        // Get IO OCR
+        #[cfg(feature = "time")]
+        let mut ticker = Ticker::every(Duration::from_millis(1));
+        let mut i = 0;
+
+        let _ocr: OCR<SD> = loop {
+            match self.sdmmc.cmd(io_send_op_cond(false, 0x0), false, false) {
+                Ok(r) => break Ok(r),
+                Err(Error::Timeout) if i == 500 => break Err(Error::Timeout),
+                Err(Error::Timeout) => {
+                    i += 1;
+
+                    #[cfg(feature = "time")]
+                    ticker.next().await;
                 }
+                Err(e) => break Err(e),
             }
-            result?.into()
-        };
+        }?
+        .into();
 
         // UDB-based SDIO does not support io volt switch sequence