diff --git a/core/src/main/scala-3/chisel3/SimLogIntf.scala b/core/src/main/scala-3/chisel3/SimLogIntf.scala
index 92d933cd434..2bc7f520362 100644
--- a/core/src/main/scala-3/chisel3/SimLogIntf.scala
+++ b/core/src/main/scala-3/chisel3/SimLogIntf.scala
@@ -2,6 +2,28 @@
 
 package chisel3
 
+import chisel3.experimental.SourceInfo
+
 private[chisel3] trait SimLogIntf { self: SimLog =>
-  // TODO implement macro for Scala 3
+
+  /** Prints a message in simulation
+    *
+    * Prints a message every cycle. If defined within the scope of a
+    * [[when]] block, the message will only be printed on cycles that
+    * the when condition is true.
+    *
+    * Does not fire when in reset (defined as the encapsulating
+    * Module's reset). If your definition of reset is not the
+    * encapsulating Module's reset, you will need to gate this
+    * externally.
+    *
+    * May be called outside of a Module (like defined in a function),
+    * uses the current default clock and reset. These can be overriden
+    * with [[withClockAndReset]].
+    *
+    * @param fmt printf format string
+    * @param data format string varargs containing data to print
+    */
+  def printf(fmt: String, data: Bits*)(using sourceInfo: SourceInfo): chisel3.printf.Printf =
+    self.printf(Printable.pack(fmt, data*))
 }
diff --git a/src/test/scala-2/chiselTests/SimLogSpec.scala b/src/test/scala/chiselTests/SimLogSpec.scala
similarity index 100%
rename from src/test/scala-2/chiselTests/SimLogSpec.scala
rename to src/test/scala/chiselTests/SimLogSpec.scala