From 3c2dab47a4ff1af86f5b6542c407c843cd598893 Mon Sep 17 00:00:00 2001 From: Aditya Naik Date: Wed, 27 May 2026 19:40:54 -0700 Subject: [PATCH 1/3] [Scala3] Move BlackBoxSpec and ChiselStageSpec --- .../experimental/InlineTestSpec.scala | 4 +- .../chiselTests/BlackBox.scala | 2 +- .../circtTests/stage/ChiselStageSpec.scala | 38 +++++++++---------- 3 files changed, 21 insertions(+), 23 deletions(-) rename src/test/{scala-2 => scala}/chiselTests/BlackBox.scala (99%) rename src/test/{scala-2 => scala}/circtTests/stage/ChiselStageSpec.scala (97%) diff --git a/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala b/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala index c3faae1d4e9..6dfce07ab1e 100644 --- a/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala +++ b/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala @@ -33,7 +33,7 @@ object TestHarnessWithMonitorSocket { @instantiable trait HasMonitorSocket { this: RawModule => protected def makeProbe(bundle: ProtocolBundle): ProtocolBundle = { - val monProbe = IO(probe.Probe(chiselTypeOf(bundle))) + val monProbe = chisel3.IO(probe.Probe(chiselTypeOf(bundle))) probe.define(monProbe, probe.ProbeValue(bundle)) monProbe } @@ -67,7 +67,7 @@ object ProtocolChecks { } } -trait HasTestsProperty { this: RawModule with HasTests => +trait HasTestsProperty extends RawModule with HasTests { def enableTestsProperty: Boolean val testNames = Option.when(enableTestsProperty) { diff --git a/src/test/scala-2/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala similarity index 99% rename from src/test/scala-2/chiselTests/BlackBox.scala rename to src/test/scala/chiselTests/BlackBox.scala index 4ee3daf0efa..2269879efb8 100644 --- a/src/test/scala-2/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -374,7 +374,7 @@ class BlackBoxSpec extends AnyFlatSpec with Matchers with ChiselSim with FileChe object A extends layer.Layer(layer.LayerConfig.Extract()) sealed trait NoIo { this: BlackBox @nowarn("cat=deprecation") => - final val io = IO(new Bundle {}) + final val io = chisel3.IO(new Bundle {}) } // No known layers diff --git a/src/test/scala-2/circtTests/stage/ChiselStageSpec.scala b/src/test/scala/circtTests/stage/ChiselStageSpec.scala similarity index 97% rename from src/test/scala-2/circtTests/stage/ChiselStageSpec.scala rename to src/test/scala/circtTests/stage/ChiselStageSpec.scala index 029c30dbd70..fc7830f3f4b 100644 --- a/src/test/scala-2/circtTests/stage/ChiselStageSpec.scala +++ b/src/test/scala/circtTests/stage/ChiselStageSpec.scala @@ -10,7 +10,7 @@ import chisel3.testing.scalatest.FileCheck import circt.stage.{ChiselStage, FirtoolOption, PreserveAggregate} import _root_.logger.LogLevel -import firrtl.EmittedVerilogCircuitAnnotation +import firrtl.{annoSeqToSeq, seqToAnnoSeq, EmittedVerilogCircuitAnnotation} import firrtl.stage.FirrtlCircuitAnnotation import java.io.File @@ -123,12 +123,12 @@ object ChiselStageSpec { } class RecoverableErrorFakeSourceInfo extends RawModule { - implicit val info = SourceLine("Foo", 3, 10) + implicit val info: SourceLine = SourceLine("Foo", 3, 10) 3.U >> -1 } class ErrorCaughtByFirtool extends RawModule { - implicit val info = SourceLine("Foo", 3, 10) + implicit val info: SourceLine = SourceLine("Foo", 3, 10) val w = Wire(UInt(8.W)) } @@ -552,7 +552,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils message should include("Something bad happened") info("The exception should not contain a stack trace") - exception.getStackTrace should be(Array()) + exception.getStackTrace should be(Array.empty[StackTraceElement]) } it("should NOT include a stack trace for recoverable errors") { @@ -569,7 +569,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils message should include("Fatal errors during hardware elaboration. Look above for error list.") info("The exception should not contain a stack trace") - exception.getStackTrace should be(Array()) + exception.getStackTrace should be(Array.empty[StackTraceElement]) } it("should include a stack trace for recoverable errors with '--throw-on-first-error'") { @@ -617,9 +617,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils val lines = stdout.split("\n") // Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match - lines(0) should include( - "src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 122:9: Negative shift amounts are illegal (got -1)" - ) + lines(0) should include("src/test/scala/circtTests/stage/ChiselStageSpec.scala 122:") + lines(0) should include(": Negative shift amounts are illegal (got -1)") lines(1) should include(" 3.U >> -1") lines(2) should include(" ^") } @@ -638,9 +637,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils val lines = stdout.split("\n") // Fuzzy includes aren't ideal but there is ANSI color in these strings that is hard to match lines.size should equal(2) - lines(0) should include( - "src/test/scala-2/circtTests/stage/ChiselStageSpec.scala 122:9: Negative shift amounts are illegal (got -1)" - ) + lines(0) should include("src/test/scala/circtTests/stage/ChiselStageSpec.scala 122:") + lines(0) should include(": Negative shift amounts are illegal (got -1)") (lines(1) should not).include("3.U >> -1") } @@ -743,8 +741,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils import chisel3.util.experimental.InlineInstance trait SimpleIO { this: RawModule => - val a = IO(Input(Bool())) - val b = IO(Output(Bool())) + val a = chisel3.IO(Input(Bool())) + val b = chisel3.IO(Output(Bool())) } class Bar extends RawModule with SimpleIO with InlineInstance { @@ -781,8 +779,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils import chisel3.util.experimental.FlattenInstance trait SimpleIO { this: RawModule => - val a = IO(Input(Bool())) - val b = IO(Output(Bool())) + val a = chisel3.IO(Input(Bool())) + val b = chisel3.IO(Output(Bool())) } class Baz extends RawModule with SimpleIO { @@ -941,8 +939,8 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils import chisel3.util.experimental.{forceName, InlineInstance} trait SimpleIO { this: RawModule => - val a = IO(Input(Bool())) - val b = IO(Output(Bool())) + val a = chisel3.IO(Input(Bool())) + val b = chisel3.IO(Output(Bool())) } class Baz extends RawModule with SimpleIO { @@ -1388,7 +1386,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils message should include("Something bad happened") info("The exception should not contain a stack trace") - exception.getStackTrace should be(Array()) + exception.getStackTrace should be(Array.empty[StackTraceElement]) } it("should NOT include a stack trace for recoverable errors") { @@ -1401,7 +1399,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils message should include("Fatal errors during hardware elaboration. Look above for error list.") info("The exception should not contain a stack trace") - exception.getStackTrace should be(Array()) + exception.getStackTrace should be(Array.empty[StackTraceElement]) } it("should report a specific error if firtool is not found on the PATH") { @@ -1415,7 +1413,7 @@ class ChiselStageSpec extends AnyFunSpec with Matchers with chiselTests.LogUtils message should include("Chisel requires firtool, the MLIR-based FIRRTL Compiler (MFC), to generate Verilog.") info("The exception should not contain a stack trace") - exception.getStackTrace should be(Array()) + exception.getStackTrace should be(Array.empty[StackTraceElement]) } } From 0a247073045c4fd54db916761522d7365a82e2ab Mon Sep 17 00:00:00 2001 From: Aditya Naik Date: Fri, 29 May 2026 14:33:27 -0700 Subject: [PATCH 2/3] undo IO change --- src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala b/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala index 6dfce07ab1e..591878fdd0b 100644 --- a/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala +++ b/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala @@ -33,7 +33,7 @@ object TestHarnessWithMonitorSocket { @instantiable trait HasMonitorSocket { this: RawModule => protected def makeProbe(bundle: ProtocolBundle): ProtocolBundle = { - val monProbe = chisel3.IO(probe.Probe(chiselTypeOf(bundle))) + val monProbe = IO(probe.Probe(chiselTypeOf(bundle))) probe.define(monProbe, probe.ProbeValue(bundle)) monProbe } From 27cad3c462bddd434deb39b74f6cfc461a9564fd Mon Sep 17 00:00:00 2001 From: Aditya Naik Date: Fri, 29 May 2026 14:34:34 -0700 Subject: [PATCH 3/3] undo selftype change --- src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala b/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala index 591878fdd0b..c3faae1d4e9 100644 --- a/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala +++ b/src/test/scala-2/chiselTests/experimental/InlineTestSpec.scala @@ -67,7 +67,7 @@ object ProtocolChecks { } } -trait HasTestsProperty extends RawModule with HasTests { +trait HasTestsProperty { this: RawModule with HasTests => def enableTestsProperty: Boolean val testNames = Option.when(enableTestsProperty) {