diff --git a/config/boards/yy3568.csc b/config/boards/yy3568.csc index 46ed923cc831..df86d0d19012 100644 --- a/config/boards/yy3568.csc +++ b/config/boards/yy3568.csc @@ -4,7 +4,8 @@ BOARD_VENDOR="youyeetoo" BOARDFAMILY="rk35xx" BOARD_MAINTAINER="hqnicolas" INTRODUCED="2023" -BOOTCONFIG="yy3568-rk3568_defconfig" +BOOTCONFIG="youyeetoo-yy3568-rk3568_defconfig" +BOOT_SOC="rk3568" KERNEL_TARGET="current,edge,vendor" KERNEL_TEST_TARGET="current" FULL_DESKTOP="yes" @@ -12,3 +13,30 @@ BOOT_LOGO="desktop" BOOT_FDT_FILE="rockchip/rk3568-yy3568.dtb" BOOT_SCENARIO="spl-blobs" IMAGE_PARTITION_TABLE="gpt" + +function post_family_config__yy3568_use_mainline_uboot() { + display_alert "$BOARD" "Using mainline U-Boot for $BOARD / $BRANCH" "info" + + declare -g BOOTCONFIG="youyeetoo-yy3568-rk3568_defconfig" + declare -g BOOTDELAY=1 + declare -g BOOTSOURCE="https://github.com/u-boot/u-boot.git" + declare -g BOOTBRANCH="tag:v2026.07" + declare -g BOOTPATCHDIR="v2026.07/board_${BOARD}" + + # Let binman combine U-Boot with Armbian's trusted firmware and DDR blobs. + declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin" + + # The mainline binman image is complete and does not need vendor post-processing. + unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd + + function write_uboot_platform() { + dd "if=$1/u-boot-rockchip.bin" "of=$2" bs=32k seek=1 conv=notrunc status=none + } +} + +function pre_config_uboot_target__yy3568_patch_rockchip_common_boot_order() { + declare -a rockchip_uboot_targets=("mmc1" "nvme" "mmc0" "scsi" "usb" "pxe" "dhcp") # mmc1=SD, mmc0=eMMC + display_alert "u-boot for ${BOARD}/${BRANCH}" "u-boot: adjust boot order to '${rockchip_uboot_targets[*]}'" "info" + sed -i -e "s/#define BOOT_TARGETS.*/#define BOOT_TARGETS \"${rockchip_uboot_targets[*]}\"/" include/configs/rockchip-common.h + regular_git diff -u include/configs/rockchip-common.h || true +} diff --git a/patch/kernel/archive/rockchip64-6.12/dt/rk3568-yy3568.dts b/patch/kernel/archive/rockchip64-6.12/dt/rk3568-yy3568.dts index 1de2d89ff2ad..7788c19b04fd 100755 --- a/patch/kernel/archive/rockchip64-6.12/dt/rk3568-yy3568.dts +++ b/patch/kernel/archive/rockchip64-6.12/dt/rk3568-yy3568.dts @@ -263,7 +263,7 @@ }; &pcie3x2 { - num-lanes = <1>; + num-lanes = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2_reset_h>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; @@ -715,4 +715,4 @@ &usb2phy1_otg { phy-supply = <&vcc5v0_host>; status = "okay"; -}; \ No newline at end of file +}; diff --git a/patch/kernel/archive/rockchip64-6.18/dt/rk3568-yy3568.dts b/patch/kernel/archive/rockchip64-6.18/dt/rk3568-yy3568.dts index 5908beaa7724..e3d4357786f1 100644 --- a/patch/kernel/archive/rockchip64-6.18/dt/rk3568-yy3568.dts +++ b/patch/kernel/archive/rockchip64-6.18/dt/rk3568-yy3568.dts @@ -288,7 +288,7 @@ }; &pcie3x2 { - num-lanes = <1>; + num-lanes = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; @@ -754,4 +754,4 @@ &usb2phy1_otg { phy-supply = <&vcc5v0_host>; status = "okay"; -}; \ No newline at end of file +}; diff --git a/patch/kernel/archive/rockchip64-7.1/dt/rk3568-yy3568.dts b/patch/kernel/archive/rockchip64-7.1/dt/rk3568-yy3568.dts index 5908beaa7724..e3d4357786f1 100644 --- a/patch/kernel/archive/rockchip64-7.1/dt/rk3568-yy3568.dts +++ b/patch/kernel/archive/rockchip64-7.1/dt/rk3568-yy3568.dts @@ -288,7 +288,7 @@ }; &pcie3x2 { - num-lanes = <1>; + num-lanes = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; @@ -754,4 +754,4 @@ &usb2phy1_otg { phy-supply = <&vcc5v0_host>; status = "okay"; -}; \ No newline at end of file +}; diff --git a/patch/kernel/archive/rockchip64-7.2/dt/rk3568-yy3568.dts b/patch/kernel/archive/rockchip64-7.2/dt/rk3568-yy3568.dts index 5908beaa7724..e3d4357786f1 100644 --- a/patch/kernel/archive/rockchip64-7.2/dt/rk3568-yy3568.dts +++ b/patch/kernel/archive/rockchip64-7.2/dt/rk3568-yy3568.dts @@ -288,7 +288,7 @@ }; &pcie3x2 { - num-lanes = <1>; + num-lanes = <2>; pinctrl-names = "default"; pinctrl-0 = <&pcie30x2m1_pins>; reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; @@ -754,4 +754,4 @@ &usb2phy1_otg { phy-supply = <&vcc5v0_host>; status = "okay"; -}; \ No newline at end of file +}; diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/yy3568-rk3568_defconfig b/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/yy3568-rk3568_defconfig deleted file mode 100644 index 17ac783cd0bb..000000000000 --- a/patch/u-boot/legacy/u-boot-radxa-rk35xx/defconfig/yy3568-rk3568_defconfig +++ /dev/null @@ -1,227 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_ROCKCHIP=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_SYS_MALLOC_F_LEN=0x80000 -CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh" -CONFIG_ROCKCHIP_RK3568=y -CONFIG_ROCKCHIP_FIT_IMAGE=y -CONFIG_ROCKCHIP_VENDOR_PARTITION=y -CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y -CONFIG_ROCKCHIP_NEW_IDB=y -CONFIG_ROCKCHIP_EMMC_IOMUX=y -CONFIG_SPL_SERIAL_SUPPORT=y -CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -CONFIG_TARGET_EVB_RK3568=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_SPI_FLASH_SUPPORT=y -CONFIG_SPL_SPI_SUPPORT=y -CONFIG_DEFAULT_DEVICE_TREE="rk3568-yy3568" -CONFIG_DEBUG_UART=y -CONFIG_FIT=y -CONFIG_FIT_IMAGE_POST_PROCESS=y -CONFIG_FIT_HW_CRYPTO=y -CONFIG_SPL_LOAD_FIT=y -CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y -CONFIG_SPL_FIT_HW_CRYPTO=y -# CONFIG_SPL_SYS_DCACHE_OFF is not set -CONFIG_BOOTDELAY=0 -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_ANDROID_BOOTLOADER=y -CONFIG_ANDROID_AVB=y -CONFIG_ANDROID_BOOT_IMAGE_HASH=y -CONFIG_SPL_BOARD_INIT=y -# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set -CONFIG_SPL_SEPARATE_BSS=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y -CONFIG_SPL_SHA256_SUPPORT=y -CONFIG_SPL_CRYPTO_SUPPORT=y -CONFIG_SPL_HASH_SUPPORT=y -CONFIG_SPL_MTD_SUPPORT=y -CONFIG_SPL_ATF=y -CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y -CONFIG_SPL_AB=y -CONFIG_FASTBOOT_BUF_ADDR=0xc00800 -CONFIG_FASTBOOT_BUF_SIZE=0x04000000 -CONFIG_FASTBOOT_FLASH=y -CONFIG_FASTBOOT_FLASH_MMC_DEV=0 -CONFIG_CMD_BOOTZ=y -CONFIG_CMD_DTIMG=y -# CONFIG_CMD_ELF is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_IMLS is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_LZMADEC is not set -# CONFIG_CMD_UNZIP is not set -# CONFIG_CMD_FLASH is not set -# CONFIG_CMD_FPGA is not set -CONFIG_CMD_GPT=y -# CONFIG_CMD_LOADB is not set -# CONFIG_CMD_LOADS is not set -CONFIG_CMD_BOOT_ANDROID=y -CONFIG_CMD_BOOT_ROCKCHIP=y -CONFIG_CMD_MMC=y -CONFIG_CMD_MTD=y -CONFIG_CMD_NAND=y -CONFIG_CMD_PCI=y -CONFIG_CMD_USB=y -CONFIG_CMD_USB_MASS_STORAGE=y -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_TFTPPUT=y -CONFIG_CMD_TFTP_BOOTM=y -CONFIG_CMD_TFTP_FLASH=y -# CONFIG_CMD_MISC is not set -# CONFIG_CMD_CHARGE_DISPLAY is not set -CONFIG_CMD_MTD_BLK=y -# CONFIG_SPL_DOS_PARTITION is not set -# CONFIG_ISO_PARTITION is not set -CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64 -CONFIG_SPL_OF_CONTROL=y -CONFIG_SPL_DTB_MINIMUM=y -CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="" -# CONFIG_NET_TFTP_VARS is not set -CONFIG_REGMAP=y -CONFIG_SPL_REGMAP=y -CONFIG_SYSCON=y -CONFIG_SPL_SYSCON=y -CONFIG_CLK=y -CONFIG_SPL_CLK=y -CONFIG_CLK_SCMI=y -CONFIG_DM_CRYPTO=y -CONFIG_SPL_DM_CRYPTO=y -CONFIG_ROCKCHIP_CRYPTO_V2=y -CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y -CONFIG_DM_RNG=y -CONFIG_RNG_ROCKCHIP=y -CONFIG_SCMI_FIRMWARE=y -CONFIG_ROCKCHIP_GPIO=y -CONFIG_ROCKCHIP_GPIO_V2=y -CONFIG_SYS_I2C_ROCKCHIP=y -CONFIG_DM_KEY=y -CONFIG_RK8XX_PWRKEY=y -CONFIG_ADC_KEY=y -CONFIG_MISC=y -CONFIG_SPL_MISC=y -CONFIG_ROCKCHIP_OTP=y -CONFIG_SPL_ROCKCHIP_SECURE_OTP=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_ROCKCHIP=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_SDMA=y -CONFIG_MMC_SDHCI_ROCKCHIP=y -CONFIG_MTD=y -CONFIG_MTD_BLK=y -CONFIG_MTD_DEVICE=y -CONFIG_NAND=y -CONFIG_NAND_ROCKCHIP_V9=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0x8000 -CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x10000 -CONFIG_MTD_SPI_NAND=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_EON=y -CONFIG_SPI_FLASH_GIGADEVICE=y -CONFIG_SPI_FLASH_MACRONIX=y -CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_XMC=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_DM_ETH=y -CONFIG_DM_ETH_PHY=y -CONFIG_DWC_ETH_QOS=y -CONFIG_GMAC_ROCKCHIP=y -CONFIG_NVME=y -CONFIG_PCI=y -CONFIG_DM_PCI=y -CONFIG_DM_PCI_COMPAT=y -CONFIG_PCIE_DW_ROCKCHIP=y -CONFIG_PHY_ROCKCHIP_INNO_USB2=y -CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -CONFIG_PHY_ROCKCHIP_NANENG_EDP=y -CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y -CONFIG_PINCTRL=y -CONFIG_SPL_PINCTRL=y -CONFIG_DM_FUEL_GAUGE=y -CONFIG_POWER_FG_RK817=y -CONFIG_IO_DOMAIN=y -CONFIG_ROCKCHIP_IO_DOMAIN=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_RK8XX=y -CONFIG_REGULATOR_FAN53555=y -CONFIG_REGULATOR_PWM=y -CONFIG_DM_REGULATOR_FIXED=y -CONFIG_DM_REGULATOR_GPIO=y -CONFIG_REGULATOR_RK8XX=y -CONFIG_DM_CHARGE_DISPLAY=y -CONFIG_CHARGE_ANIMATION=y -CONFIG_PWM_ROCKCHIP=y -CONFIG_RAM=y -CONFIG_SPL_RAM=y -CONFIG_TPL_RAM=y -CONFIG_DM_RAMDISK=y -CONFIG_RAMDISK_RO=y -CONFIG_DM_DMC=y -CONFIG_ROCKCHIP_DMC_FSP=y -CONFIG_ROCKCHIP_SDRAM_COMMON=y -CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE=0 -CONFIG_DM_RESET=y -CONFIG_SPL_DM_RESET=y -CONFIG_SPL_RESET_ROCKCHIP=y -CONFIG_BAUDRATE=115200 -CONFIG_DEBUG_UART_BASE=0xFE660000 -CONFIG_DEBUG_UART_CLOCK=24000000 -CONFIG_DEBUG_UART_SHIFT=2 -CONFIG_ROCKCHIP_SFC=y -CONFIG_SYSRESET=y -CONFIG_USB=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_DWC3=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_GENERIC=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_GENERIC=y -CONFIG_USB_DWC3=y -CONFIG_USB_DWC3_GADGET=y -CONFIG_USB_DWC3_GENERIC=y -CONFIG_USB_STORAGE=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_MANUFACTURER="Rockchip" -CONFIG_USB_GADGET_VENDOR_NUM=0x2207 -CONFIG_USB_GADGET_PRODUCT_NUM=0x350a -CONFIG_USB_GADGET_DOWNLOAD=y -CONFIG_DM_VIDEO=y -CONFIG_DISPLAY=y -CONFIG_DRM_ROCKCHIP=y -CONFIG_DRM_ROCKCHIP_DW_HDMI=y -CONFIG_DRM_ROCKCHIP_INNO_MIPI_PHY=y -CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y -CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y -CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y -CONFIG_DRM_ROCKCHIP_LVDS=y -CONFIG_DRM_ROCKCHIP_RGB=y -CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=9 -CONFIG_LCD=y -CONFIG_USE_TINY_PRINTF=y -CONFIG_SPL_TINY_MEMSET=y -CONFIG_RSA=y -CONFIG_SPL_RSA=y -CONFIG_RSA_N_SIZE=0x200 -CONFIG_RSA_E_SIZE=0x10 -CONFIG_RSA_C_SIZE=0x20 -CONFIG_XBC=y -CONFIG_SHA512=y -CONFIG_LZ4=y -CONFIG_LZMA=y -CONFIG_SPL_GZIP=y -CONFIG_ERRNO_STR=y -# CONFIG_EFI_LOADER is not set -CONFIG_AVB_LIBAVB=y -CONFIG_AVB_LIBAVB_AB=y -CONFIG_AVB_LIBAVB_ATX=y -CONFIG_AVB_LIBAVB_USER=y -CONFIG_RK_AVB_LIBAVB_USER=y diff --git a/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3568-yy3568.dts b/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3568-yy3568.dts deleted file mode 100644 index e218ef9eee4b..000000000000 --- a/patch/u-boot/legacy/u-boot-radxa-rk35xx/dt/rk3568-yy3568.dts +++ /dev/null @@ -1,619 +0,0 @@ -/* - * SPDX-License-Identifier: GPL-2.0+ - * Copyright (c) 2020 Rockchip Electronics Co., Ltd. - * Copyright (c) 2024 Radxa Limited - */ -/dts-v1/; -#include -#include -#include -#include "rk3568.dtsi" -#include "rk3568-u-boot.dtsi" -/ { - model = "Youyeetoo YY3568"; - compatible = "youyeetoo,yy3568", "rockchip,rk3568"; - aliases { - ethernet0 = &gmac0; - ethernet1 = &gmac1; - mmc0 = &sdhci; - mmc1 = &sdmmc0; - mmc2 = &sdmmc2; - }; - vcc12v_input: vcc12v-input { - u-boot,dm-pre-reloc; - compatible = "regulator-fixed"; - regulator-name = "vcc12v_input"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <12000000>; - regulator-max-microvolt = <12000000>; - }; - vcc5v0_sys: vcc5v0-sys { - u-boot,dm-pre-reloc; - compatible = "regulator-fixed"; - regulator-name = "vcc5v0_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc12v_input>; - }; - vcc3v3_sys: vcc3v3-sys { - u-boot,dm-pre-reloc; - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_sys"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc12v_input>; - }; - vcc3v3_pi6c_05: vcc3v3-pi6c-05 { - u-boot,dm-pre-reloc; - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie_enable_h>; - regulator-name = "vcc3v3_pi6c_05"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - vin-supply = <&vcc5v0_sys>; - }; - vcc3v3_pcie: vcc3v3-pcie { - u-boot,dm-pre-reloc; - compatible = "regulator-fixed"; - regulator-name = "vcc3v3_pcie"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - enable-active-high; - gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30_pwr>; - startup-delay-us = <5000>; - vin-supply = <&vcc5v0_sys>; - }; - pcie30_avdd0v9: pcie30-avdd0v9 { - u-boot,dm-pre-reloc; - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd0v9"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - vin-supply = <&vcc3v3_sys>; - }; - pcie30_avdd1v8: pcie30-avdd1v8 { - u-boot,dm-pre-reloc; - compatible = "regulator-fixed"; - regulator-name = "pcie30_avdd1v8"; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - vin-supply = <&vcc3v3_sys>; - }; - adc-keys { - compatible = "adc-keys"; - io-channels = <&saradc 0>; - io-channel-names = "buttons"; - keyup-threshold-microvolt = <1800000>; - u-boot,dm-spl; - status = "okay"; - volumeup-key { - u-boot,dm-spl; - linux,code = ; - label = "volume up"; - press-threshold-microvolt = <9>; - }; - }; - leds { - u-boot,dm-pre-reloc; - compatible = "gpio-leds"; - status = "okay"; - blue-led { - u-boot,dm-pre-reloc; - label = "blue"; - gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; - }; - }; -}; -&crypto { - status = "okay"; -}; -&gmac0 { - u-boot,dm-pre-reloc; - phy-mode = "rgmii"; - clock_in_out = "output"; - snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - snps,reset-delays-us = <0 20000 100000>; - assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; - assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac0_miim - &gmac0_tx_bus2 - &gmac0_rx_bus2 - &gmac0_rgmii_clk - &gmac0_rgmii_bus>; - phy-handle = <&rgmii_phy0>; - status = "okay"; -}; -&gmac1 { - u-boot,dm-pre-reloc; - phy-mode = "rgmii"; - clock_in_out = "output"; - snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; - snps,reset-active-low; - /* Reset time is 20ms, 100ms for rtl8211f */ - snps,reset-delays-us = <0 20000 100000>; - assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; - assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; - assigned-clock-rates = <0>, <125000000>; - pinctrl-names = "default"; - pinctrl-0 = <&gmac1m1_miim - &gmac1m1_tx_bus2 - &gmac1m1_rx_bus2 - &gmac1m1_rgmii_clk - &gmac1m1_rgmii_bus>; - tx_delay = <0x44>; - rx_delay = <0x26>; - phy-handle = <&rgmii_phy1>; - status = "okay"; -}; -&grf { - u-boot,dm-pre-reloc; - status = "okay"; -}; -&gpio0 { - u-boot,dm-pre-reloc; -}; -&gpio1 { - u-boot,dm-pre-reloc; -}; -&gpio2 { - u-boot,dm-pre-reloc; -}; -&gpio3 { - u-boot,dm-pre-reloc; -}; -&gpio4 { - u-boot,dm-pre-reloc; -}; -&i2c0 { - status = "okay"; - u-boot,dm-pre-reloc; - clock-frequency = <100000>; - vdd_cpu: tcs4525@1c { - u-boot,dm-pre-reloc; - compatible = "tcs,tcs452x"; - reg = <0x1c>; - vin-supply = <&vcc5v0_sys>; - regulator-compatible = "fan53555-reg"; - regulator-name = "vdd_cpu"; - regulator-min-microvolt = <712500>; - regulator-max-microvolt = <1390000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <2300>; - fcs,suspend-voltage-selector = <1>; - regulator-boot-on; - regulator-always-on; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - rk809: pmic@20 { - u-boot,dm-pre-reloc; - status = "okay"; - compatible = "rockchip,rk809"; - reg = <0x20>; - interrupt-parent = <&gpio0>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default", "pmic-sleep", - "pmic-power-off", "pmic-reset"; - pinctrl-0 = <&pmic_int>; - pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; - pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; - pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>; - rockchip,system-power-controller; - wakeup-source; - #clock-cells = <1>; - clock-output-names = "rk808-clkout1", "rk808-clkout2"; - /* 1: rst regs (default in codes), 0: rst the pmic */ - pmic-reset-func = <0>; - /* not save the PMIC_POWER_EN register in uboot */ - not-save-power-en = <1>; - vcc1-supply = <&vcc3v3_sys>; - vcc2-supply = <&vcc3v3_sys>; - vcc3-supply = <&vcc3v3_sys>; - vcc4-supply = <&vcc3v3_sys>; - vcc5-supply = <&vcc3v3_sys>; - vcc6-supply = <&vcc3v3_sys>; - vcc7-supply = <&vcc3v3_sys>; - vcc8-supply = <&vcc3v3_sys>; - vcc9-supply = <&vcc3v3_sys>; - pwrkey { - status = "okay"; - u-boot,dm-pre-reloc; - }; - pinctrl_rk8xx: pinctrl_rk8xx { - u-boot,dm-pre-reloc; - gpio-controller; - #gpio-cells = <2>; - rk817_slppin_null: rk817_slppin_null { - pins = "gpio_slp"; - function = "pin_fun0"; - u-boot,dm-pre-reloc; - }; - rk817_slppin_slp: rk817_slppin_slp { - pins = "gpio_slp"; - function = "pin_fun1"; - u-boot,dm-pre-reloc; - }; - rk817_slppin_pwrdn: rk817_slppin_pwrdn { - pins = "gpio_slp"; - function = "pin_fun2"; - u-boot,dm-pre-reloc; - }; - rk817_slppin_rst: rk817_slppin_rst { - pins = "gpio_slp"; - function = "pin_fun3"; - u-boot,dm-pre-reloc; - }; - }; - regulators { - u-boot,dm-pre-reloc; - vdd_logic: DCDC_REG1 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_logic"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-on-in-suspend; - }; - }; - vdd_gpu: DCDC_REG2 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_gpu"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-on-in-suspend; - }; - }; - vcc_ddr: DCDC_REG3 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-initial-mode = <0x2>; - regulator-name = "vcc_ddr"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-on-in-suspend; - }; - }; - vdd_npu: DCDC_REG4 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <500000>; - regulator-max-microvolt = <1350000>; - regulator-init-microvolt = <900000>; - regulator-ramp-delay = <6001>; - regulator-initial-mode = <0x2>; - regulator-name = "vdd_npu"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-on-in-suspend; - }; - }; - vdda0v9_image: LDO_REG1 { - u-boot,dm-pre-reloc; - regulator-boot-on; - regulator-always-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_image"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - vdda_0v9: LDO_REG2 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda_0v9"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - vdda0v9_pmu: LDO_REG3 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <900000>; - regulator-name = "vdda0v9_pmu"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-on-in-suspend; - regulator-suspend-microvolt = <900000>; - }; - }; - vccio_acodec: LDO_REG4 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_acodec"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - vccio_sd: LDO_REG5 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vccio_sd"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - vcc3v3_pmu: LDO_REG6 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-name = "vcc3v3_pmu"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-on-in-suspend; - regulator-suspend-microvolt = <3300000>; - }; - }; - vcca_1v8: LDO_REG7 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca_1v8"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - vcca1v8_pmu: LDO_REG8 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_pmu"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-on-in-suspend; - regulator-suspend-microvolt = <1800000>; - }; - }; - vcca1v8_image: LDO_REG9 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcca1v8_image"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - vcc_1v8: DCDC_REG5 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-name = "vcc_1v8"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - vcc_3v3: SWITCH_REG1 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc_3v3"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - vcc3v3_sd: SWITCH_REG2 { - u-boot,dm-pre-reloc; - regulator-always-on; - regulator-boot-on; - regulator-name = "vcc3v3_sd"; - regulator-state-mem { - u-boot,dm-pre-reloc; - regulator-off-in-suspend; - }; - }; - }; - }; -}; -&i2c0_xfer { - u-boot,dm-pre-reloc; - status = "okay"; -}; -&rgmii_phy0 { - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; -}; - -&rgmii_phy1 { - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; - reset-assert-us = <20000>; - reset-deassert-us = <100000>; - reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; -}; -&pcfg_pull_none_smt { - u-boot,dm-pre-reloc; - status = "okay"; -}; -&pcie2x1 { - u-boot,dm-pre-reloc; - reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pi6c_05>; - status = "okay"; -}; -&pcie30_phy_grf { - u-boot,dm-pre-reloc; -}; -&pcie30phy { - u-boot,dm-pre-reloc; - data-lanes = <1 2>; - status = "okay"; -}; -&pcie3x2 { - u-boot,dm-pre-reloc; - num-lanes = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pcie30x2_reset_h>; - reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie>; - phys = <&pcie30phy>; - status = "okay"; -}; -&pinctrl { - u-boot,dm-spl; - pcie { - u-boot,dm-pre-reloc; - pcie30x2_reset_h: pcie30x2-reset-h { - u-boot,dm-pre-reloc; - rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; - }; - pcie_enable_h: pcie-enable-h { - u-boot,dm-pre-reloc; - rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; - }; - pcie30_pwr: pcie30-pwr { - u-boot,dm-pre-reloc; - rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; - }; - }; - pmic { - u-boot,dm-pre-reloc; - pmic_int: pmic_int { - u-boot,dm-pre-reloc; - rockchip,pins = - <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; - }; - soc_slppin_gpio: soc_slppin_gpio { - u-boot,dm-pre-reloc; - rockchip,pins = - <0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low_pull_down>; - }; - soc_slppin_slp: soc_slppin_slp { - u-boot,dm-pre-reloc; - rockchip,pins = - <0 RK_PA2 RK_FUNC_1 &pcfg_pull_up>; - }; - soc_slppin_rst: soc_slppin_rst { - u-boot,dm-pre-reloc; - rockchip,pins = - <0 RK_PA2 RK_FUNC_2 &pcfg_pull_none>; - }; - }; -}; -&pmu_io_domains { - u-boot,dm-pre-reloc; - status = "okay"; - pmuio1-supply = <&vcc3v3_pmu>; - pmuio2-supply = <&vcc3v3_pmu>; - vccio1-supply = <&vccio_acodec>; - vccio2-supply = <&vcc_1v8>; - vccio3-supply = <&vccio_sd>; - vccio4-supply = <&vcc_1v8>; - vccio5-supply = <&vcc_3v3>; - vccio6-supply = <&vcc_1v8>; - vccio7-supply = <&vcc_3v3>; -}; -&pmucru { - u-boot,dm-pre-reloc; - status = "okay"; -}; -&pmugrf { - u-boot,dm-pre-reloc; - status = "okay"; -}; -&saradc { - vref-supply = <&vcca_1v8>; - status = "okay"; -}; -&sdhci { - bus-width = <8>; - max-frequency = <200000000>; - non-removable; - pinctrl-names = "default"; - pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; - vmmc-supply = <&vcc_3v3>; - vqmmc-supply = <&vcc_1v8>; - status = "okay"; -}; -&sdmmc0 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; - sd-uhs-sdr104; - vmmc-supply = <&vcc3v3_sd>; - vqmmc-supply = <&vccio_sd>; - status = "okay"; -}; -&sdmmc2 { - bus-width = <4>; - cap-sd-highspeed; - cd-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default"; - pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; - sd-uhs-sdr104; - status = "okay"; -}; -&uart2 { - status = "okay"; -}; \ No newline at end of file diff --git a/patch/u-boot/v2026.07/board_yy3568/0001-board-rockchip-add-Youyeetoo-YY3568-support.patch b/patch/u-boot/v2026.07/board_yy3568/0001-board-rockchip-add-Youyeetoo-YY3568-support.patch new file mode 100644 index 000000000000..a41ac7fb2ac1 --- /dev/null +++ b/patch/u-boot/v2026.07/board_yy3568/0001-board-rockchip-add-Youyeetoo-YY3568-support.patch @@ -0,0 +1,906 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Nicolas Pereira +Date: Fri, 7 Aug 2026 18:09:49 -0300 +Subject: [PATCH] board: rockchip: add Youyeetoo YY3568 support + +--- + .../dts/rk3568-youyeetoo-yy3568-u-boot.dtsi | 32 + + configs/youyeetoo-yy3568-rk3568_defconfig | 93 +++ + .../rockchip/rk3568-youyeetoo-yy3568.dts | 749 ++++++++++++++++++ + 3 files changed, 874 insertions(+) + create mode 100644 arch/arm/dts/rk3568-youyeetoo-yy3568-u-boot.dtsi + create mode 100644 configs/youyeetoo-yy3568-rk3568_defconfig + create mode 100644 dts/upstream/src/arm64/rockchip/rk3568-youyeetoo-yy3568.dts + +diff --git a/arch/arm/dts/rk3568-youyeetoo-yy3568-u-boot.dtsi b/arch/arm/dts/rk3568-youyeetoo-yy3568-u-boot.dtsi +new file mode 100644 +index 00000000..70df0e7e +--- /dev/null ++++ b/arch/arm/dts/rk3568-youyeetoo-yy3568-u-boot.dtsi +@@ -0,0 +1,32 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++#include "rk356x-u-boot.dtsi" ++ ++/ { ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++}; ++ ++&pcie3x2 { ++ pinctrl-0 = <&pcie30x2m1_pins &pcie30x2_reset_h>; ++}; ++ ++&sdhci { ++ cap-mmc-highspeed; ++ mmc-hs200-1_8v; ++ mmc-hs400-1_8v; ++ mmc-hs400-enhanced-strobe; ++}; ++ ++&vcc3v3_pi6c_05 { ++ regulator-always-on; ++ regulator-boot-on; ++}; ++ ++/* Required by the Rockchip 6.1 BSP NPU power-domain handoff. */ ++&vdd_npu { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++}; +diff --git a/configs/youyeetoo-yy3568-rk3568_defconfig b/configs/youyeetoo-yy3568-rk3568_defconfig +new file mode 100644 +index 00000000..840bc86d +--- /dev/null ++++ b/configs/youyeetoo-yy3568-rk3568_defconfig +@@ -0,0 +1,93 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_SF_DEFAULT_SPEED=24000000 ++CONFIG_SF_DEFAULT_MODE=0x2000 ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3568-youyeetoo-yy3568" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_ROCKCHIP_SPI_IMAGE=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_SF_DEFAULT_BUS=4 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_SPL_SPI_FLASH_SUPPORT=y ++CONFIG_SPL_SPI=y ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-youyeetoo-yy3568.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_SPI_LOAD=y ++CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_POWEROFF=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SCSI_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_SCSI=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_ROCKCHIP_SFC=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_EHCI_HCD=y ++CONFIG_USB_EHCI_GENERIC=y ++CONFIG_USB_OHCI_HCD=y ++CONFIG_USB_OHCI_GENERIC=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_ERRNO_STR=y +diff --git a/dts/upstream/src/arm64/rockchip/rk3568-youyeetoo-yy3568.dts b/dts/upstream/src/arm64/rockchip/rk3568-youyeetoo-yy3568.dts +new file mode 100644 +index 00000000..b0a94d52 +--- /dev/null ++++ b/dts/upstream/src/arm64/rockchip/rk3568-youyeetoo-yy3568.dts +@@ -0,0 +1,749 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2020 Rockchip Electronics Co., Ltd. ++ * ++ */ ++/dts-v1/; ++ ++#include ++#include ++#include ++#include ++#include ++#include "rk3568.dtsi" ++ ++/ { ++ model = "Youyeetoo YY3568"; ++ compatible = "youyeetoo,yy3568", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ ethernet1 = &gmac1; ++ mmc2 = &sdmmc2; ++ mmc1 = &sdmmc0; ++ mmc0 = &sdhci; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ ++ led_user: led-0 { ++ gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_user_en>; ++ }; ++ led_power: led-1 { ++ gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_power_en>; ++ }; ++ }; ++ ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ ++ rk809-sound { ++ compatible = "simple-audio-card"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_det>; ++ hp-det-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,name = "Analog RK809"; ++ simple-audio-card,mclk-fs = <256>; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ ++ vcc5v0_otg: regulator-vbus-typec { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_otg_en>; ++ regulator-name = "vcc5v0_otg"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ /* actually fed by vcc5v0_sys, dependent ++ * on pi6c clock generator ++ */ ++ ++ vcc5v0_host: vcc5v0-host-regulator { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_host_en>; ++ regulator-name = "vcc5v0_host"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 { ++ compatible = "regulator-fixed"; ++ enable-active-high; ++ gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_enable_h>; ++ regulator-name = "vcc3v3_pi6c_05"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ enable-active-high; ++ gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie30_pwr>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++ ++ pcie_oe_regulator: pcie-oe-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie_oe"; ++ gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_oe>; ++ enable-active-high; ++ regulator-always-on; ++ regulator-boot-on; ++ }; ++ ++ pcie30_avdd0v9: regulator-pcie30-avdd0v9 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ pcie30_avdd1v8: regulator-pcie30-avdd1v8 { ++ compatible = "regulator-fixed"; ++ regulator-name = "pcie30_avdd1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc3v3_sys: regulator-vcc3v3-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc12v_input>; ++ }; ++ ++ vcc5v0_sys: regulator-vcc5v0-sys { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_input>; ++ }; ++ ++ /* labeled +12v_input in schematic */ ++ vcc12v_input: regulator-vcc5v-input { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_input"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++}; ++ ++&combphy1 { ++ phy-supply = <&pcie_oe_regulator>; ++ status = "okay"; ++}; ++ ++&combphy0 { ++ status = "okay"; ++}; ++ ++&combphy2 { ++ status = "okay"; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = ; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; ++ ++&hdmi { ++ assigned-clocks = <&cru CLK_HDMI_CEC>; ++ assigned-clock-rates = <32768>; ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&hdmi_sound { ++ status = "okay"; ++}; ++ ++&pcie2x1 { ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pi6c_05>; ++ status = "okay"; ++}; ++ ++&pcie30phy { ++ data-lanes = <1 2>; ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ num-lanes = <2>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie30x2m1_pins>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++ phys = <&pcie30phy>; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc12v_input>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = ; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int>; ++ #sound-dai-cells = <0>; ++ system-power-controller; ++ wakeup-source; ++ ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ leds { ++ led_user_en: led_user_en { ++ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ led_power_en: led_power_en { ++ rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ headphone { ++ hp_det: hp-det { ++ rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int: pmic_int { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++ ++ pcie { ++ pcie30x2_reset_h: pcie30x2-reset-h { ++ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_enable_h: pcie-enable-h { ++ rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie30_pwr: pcie30-pwr { ++ rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ pcie_oe: pcie-oe { ++ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ usb { ++ vcc5v0_host_en: vcc5v0-host-en { ++ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ ++ vcc5v0_otg_en: vcc5v0_otg_en { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++}; ++ ++&i2s0_8ch { ++ status = "okay"; ++}; ++ ++&i2s1_8ch { ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_1v8>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ /* Also used in pcie30x1_clkreqnm0 */ ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>; ++ sd-uhs-sdr104; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&sdmmc2 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_clk &sdmmc2m0_cmd>; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-id001c.c916"; ++ reg = <0x0>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&mdio1 { ++ rgmii_phy1: ethernet-phy@0 { ++ compatible = "ethernet-phy-id001c.c916"; ++ reg = <0x0>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus>; ++ tx_delay = <0x3c>; ++ rx_delay = <0x2f>; ++ status = "okay"; ++}; ++ ++&gmac1 { ++ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; ++ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy1>; ++ phy-mode = "rgmii"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac1m1_miim ++ &gmac1m1_tx_bus2 ++ &gmac1m1_rx_bus2 ++ &gmac1m1_rgmii_clk ++ &gmac1m1_rgmii_bus>; ++ tx_delay = <0x4f>; ++ rx_delay = <0x26>; ++ status = "okay"; ++}; ++ ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ dr_mode = "host"; ++ extcon = <&usb2phy0>; ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vcc5v0_otg>; ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_host>; ++ status = "okay"; ++};