diff --git a/.rat-excludes b/.rat-excludes index 4b9a16e421..4b36748da4 100644 --- a/.rat-excludes +++ b/.rat-excludes @@ -183,6 +183,7 @@ hw/mcu/stm/stm32g0xx/src/clock_stm32g0xx.c hw/mcu/stm/stm32g0xx/src/system_stm32g0xx.c hw/mcu/stm/stm32g4xx/src/clock_stm32g4xx.c hw/mcu/stm/stm32g4xx/src/system_stm32g4xx.c +hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c hw/mcu/stm/stm32h7xx/src/clock_stm32h7xx.c hw/mcu/stm/stm32h7xx/src/system_stm32h7xx.c hw/mcu/stm/stm32l0xx/src/clock_stm32l0xx.c @@ -215,6 +216,7 @@ hw/bsp/nucleo-f746zg/include/bsp/stm32f7xx_hal_conf.h hw/bsp/nucleo-f767zi/include/bsp/stm32f7xx_hal_conf.h hw/bsp/nucleo-g0b1re/include/bsp/stm32g0xx_hal_conf.h hw/bsp/nucleo-g491re/include/bsp/stm32g4xx_hal_conf.h +hw/bsp/nucleo-h563zi/include/bsp/stm32h5xx_hal_conf.h hw/bsp/nucleo-h723zg/include/bsp/stm32h7xx_hal_conf.h hw/bsp/nucleo-h753zi/include/bsp/stm32h7xx_hal_conf.h hw/bsp/nucleo-l073rz/include/bsp/stm32l0xx_hal_conf.h diff --git a/.style_ignored_dirs b/.style_ignored_dirs index cf068c7cc0..6abd29b578 100644 --- a/.style_ignored_dirs +++ b/.style_ignored_dirs @@ -33,6 +33,7 @@ hw/bsp/nucleo-f746zg/include/bsp/stm32f7xx_hal_conf.h hw/bsp/nucleo-f767zi/include/bsp/stm32f7xx_hal_conf.h hw/bsp/nucleo-g0b1re/include/bsp/stm32g0xx_hal_conf.h hw/bsp/nucleo-g491re/include/bsp/stm32g4xx_hal_conf.h +hw/bsp/nucleo-h563zi/include/bsp/stm32h5xx_hal_conf.h hw/bsp/nucleo-l073rz/include/bsp/stm32l0xx_hal_conf.h hw/bsp/nucleo-l476rg/include/bsp/stm32l4xx_hal_conf.h hw/bsp/olimex-p103/include/bsp/stm32f1xx_hal_conf.h @@ -52,6 +53,7 @@ hw/mcu/stm/stm32f3xx/src/system_stm32f3xx.c hw/mcu/stm/stm32f7xx/src/system_stm32f7xx.c hw/mcu/stm/stm32g0xx/src/system_stm32g0xx.c hw/mcu/stm/stm32g4xx/src/system_stm32g4xx.c +hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c hw/mcu/stm/stm32u5xx/src/system_stm32u5xx.c hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c diff --git a/hw/bsp/nucleo-h563zi/bsp.yml b/hw/bsp/nucleo-h563zi/bsp.yml new file mode 100644 index 0000000000..6b23ac4982 --- /dev/null +++ b/hw/bsp/nucleo-h563zi/bsp.yml @@ -0,0 +1,65 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +bsp.name: "NUCLEO-H563ZI" +bsp.url: https://www.st.com/en/evaluation-tools/nucleo-h563zi.html +bsp.maker: "STMicroelectronics" +bsp.arch: cortex_m33 +bsp.compiler: compiler/arm-none-eabi-m33 +bsp.linkerscript: autogenerated +bsp.downloadscript: "hw/scripts/download.sh" +bsp.debugscript: "hw/bsp/nucleo-h563zi/debug.sh" + +bsp.flash_map: + areas: + # System areas. + FLASH_AREA_BOOTLOADER: + device: 0 + offset: 0x08000000 + size: 48kB + FLASH_AREA_IMAGE_0: + device: 0 + offset: 0x08010000 + size: 512kB + FLASH_AREA_IMAGE_1: + device: 0 + offset: 0x08090000 + size: 512kB + FLASH_AREA_IMAGE_SCRATCH: + device: 0 + offset: 0x08110000 + size: 64kB + + # User areas. + FLASH_AREA_REBOOT_LOG: + user_id: 0 + device: 0 + offset: 0x0800C000 + size: 16kB + FLASH_AREA_NFFS: + user_id: 1 + device: 0 + offset: 0x08120000 + size: 64kB + + FLASH_AREA_SPI: + user_id: 2 + device: 1 + offset: 0x0 + size: 128kB diff --git a/hw/bsp/nucleo-h563zi/debug.sh b/hw/bsp/nucleo-h563zi/debug.sh new file mode 100644 index 0000000000..28886adf6b --- /dev/null +++ b/hw/bsp/nucleo-h563zi/debug.sh @@ -0,0 +1,34 @@ +#!/bin/sh +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +# Called with following variables set: +# - CORE_PATH is absolute path to @apache-mynewt-core +# - BSP_PATH is absolute path to hw/bsp/bsp_name +# - BIN_BASENAME is the path to prefix to target binary, +# .elf appended to name is the ELF file +# - FEATURES holds the target features string +# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software +# - RESET set if target should be reset when attaching +# - NO_GDB set if we should not start gdb to debug +# +. $CORE_PATH/hw/scripts/stm32_programmer.sh + +FILE_NAME=$BIN_BASENAME.elf + +stm32_debug diff --git a/hw/bsp/nucleo-h563zi/include/bsp/bsp.h b/hw/bsp/nucleo-h563zi/include/bsp/bsp.h new file mode 100644 index 0000000000..406a09bc95 --- /dev/null +++ b/hw/bsp/nucleo-h563zi/include/bsp/bsp.h @@ -0,0 +1,96 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#ifndef H_BSP_H +#define H_BSP_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Define special stackos sections */ +#define sec_data_core __attribute__((section(".data.core"))) +#define sec_bss_core __attribute__((section(".bss.core"))) +#define sec_bss_nz_core __attribute__((section(".bss.core.nz"))) + +/* More convenient section placement macros. */ +#define bssnz_t sec_bss_nz_core + +extern uint8_t _ram_start; +extern uint8_t _dtcmram_start; +extern uint8_t _itcmram_start; +extern uint8_t _ram2_start; + +#define RAM1_SIZE (256 * 1024) +#define RAM2_SIZE (64 * 1024) +#define RAM3_SIZE (320 * 1024) +#define RAM_SIZE (RAM1_SIZE + RAM2_SIZE + RAM3_SIZE) + +/* LED pins */ +#define LED_1 MCU_GPIO_PORTB(0) +#define LED_2 MCU_GPIO_PORTE(1) +#define LED_3 MCU_GPIO_PORTB(14) +#define LED_green LED_1 +#define LED_blue LED_2 +#define LED_red LED_3 +#define LED_BLINK_PIN LED_1 + +/* BUTTON pins */ +#define BTN_USER_1 MCU_GPIO_PORTC(13) +#define BUTTON_1 BTN_USER_1 + +/* Arduino pins */ +#define ARDUINO_PIN_D0 MCU_GPIO_PORTB(7) +#define ARDUINO_PIN_D1 MCU_GPIO_PORTB(6) +#define ARDUINO_PIN_D2 MCU_GPIO_PORTG(14) +#define ARDUINO_PIN_D3 MCU_GPIO_PORTE(13) +#define ARDUINO_PIN_D4 MCU_GPIO_PORTE(14) +#define ARDUINO_PIN_D5 MCU_GPIO_PORTE(11) +#define ARDUINO_PIN_D6 MCU_GPIO_PORTE(9) +#define ARDUINO_PIN_D7 MCU_GPIO_PORTG(12) +#define ARDUINO_PIN_D8 MCU_GPIO_PORTF(3) +#define ARDUINO_PIN_D9 MCU_GPIO_PORTD(15) +#define ARDUINO_PIN_D10 MCU_GPIO_PORTD(14) +#define ARDUINO_PIN_D11 MCU_GPIO_PORTB(5) +#define ARDUINO_PIN_D12 MCU_GPIO_PORTG(9) +#define ARDUINO_PIN_D13 MCU_GPIO_PORTA(5) +#define ARDUINO_PIN_A0 MCU_GPIO_PORTA(6) +#define ARDUINO_PIN_A1 MCU_GPIO_PORTC(0) +#define ARDUINO_PIN_A2 MCU_GPIO_PORTC(3) +#define ARDUINO_PIN_A3 MCU_GPIO_PORTB(1) +#define ARDUINO_PIN_A4 MCU_GPIO_PORTC(2) +#define ARDUINO_PIN_A5 MCU_GPIO_PORTF(11) + +#define ARDUINO_PIN_RX ARDUINO_PIN_D0 +#define ARDUINO_PIN_TX ARDUINO_PIN_D1 + +#define ARDUINO_PIN_SCL MCU_GPIO_PORTB(8) +#define ARDUINO_PIN_SDA MCU_GPIO_PORTB(9) + +#define ARDUINO_PIN_SCK ARDUINO_PIN_D13 +#define ARDUINO_PIN_MOSI ARDUINO_PIN_D11 +#define ARDUINO_PIN_MISO ARDUINO_PIN_D12 + +#ifdef __cplusplus +} +#endif + +#endif /* H_BSP_H */ diff --git a/hw/bsp/nucleo-h563zi/include/bsp/stm32h5xx_hal_conf.h b/hw/bsp/nucleo-h563zi/include/bsp/stm32h5xx_hal_conf.h new file mode 100644 index 0000000000..cecd418664 --- /dev/null +++ b/hw/bsp/nucleo-h563zi/include/bsp/stm32h5xx_hal_conf.h @@ -0,0 +1,500 @@ +/** + ********************************************************************************************************************** + * @file stm32h5xx_hal_conf_template.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32h5xx_hal_conf.h. + ********************************************************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ********************************************************************************************************************** + */ + +/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ +#ifndef STM32H5xx_HAL_CONF_H +#define STM32H5xx_HAL_CONF_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ----------------------------------------------------------------------------------------------------*/ +/* Exported constants ------------------------------------------------------------------------------------------------*/ + +/* ########################################### Module Selection ##################################################### */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +#define HAL_ADC_MODULE_ENABLED +#define HAL_CEC_MODULE_ENABLED +#define HAL_COMP_MODULE_ENABLED +#define HAL_CORDIC_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_CRC_MODULE_ENABLED +#define HAL_CRYP_MODULE_ENABLED +#define HAL_DAC_MODULE_ENABLED +#define HAL_DCACHE_MODULE_ENABLED +#define HAL_DCMI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_DTS_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_ETH_MODULE_ENABLED +#define HAL_FDCAN_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_FMAC_MODULE_ENABLED +#define HAL_GPIO_MODULE_ENABLED +#define HAL_GTZC_MODULE_ENABLED +#define HAL_HASH_MODULE_ENABLED +#define HAL_HCD_MODULE_ENABLED +#define HAL_I2C_MODULE_ENABLED +#define HAL_I2S_MODULE_ENABLED +#define HAL_I3C_MODULE_ENABLED +#define HAL_ICACHE_MODULE_ENABLED +#define HAL_IRDA_MODULE_ENABLED +#define HAL_IWDG_MODULE_ENABLED +#define HAL_LPTIM_MODULE_ENABLED +#define HAL_MMC_MODULE_ENABLED +#define HAL_NAND_MODULE_ENABLED +#define HAL_NOR_MODULE_ENABLED +#define HAL_OTFDEC_MODULE_ENABLED +#define HAL_OPAMP_MODULE_ENABLED +#define HAL_PCD_MODULE_ENABLED +#define HAL_PKA_MODULE_ENABLED +#define HAL_PSSI_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_RAMCFG_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_RNG_MODULE_ENABLED +#define HAL_RTC_MODULE_ENABLED +#define HAL_SAI_MODULE_ENABLED +#define HAL_SD_MODULE_ENABLED +#define HAL_SDRAM_MODULE_ENABLED +#define HAL_SMARTCARD_MODULE_ENABLED +#define HAL_SMBUS_MODULE_ENABLED +#define HAL_SPI_MODULE_ENABLED +#define HAL_SRAM_MODULE_ENABLED +#define HAL_TIM_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED +#define HAL_USART_MODULE_ENABLED +#define HAL_WWDG_MODULE_ENABLED +#define HAL_XSPI_MODULE_ENABLED + +/* ####################################### Oscillator Values adaptation ##############################################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if defined (MYNEWT_VAL_STM32_CLOCK_HSE_VALUE) +#define HSE_VALUE MYNEWT_VAL(STM32_CLOCK_HSE_VALUE) +#elif !defined (HSE_VALUE) +#define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal Core Speed oscillator (CSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when CSI is used as system clock source, directly or through the PLL). + */ +#if !defined (CSI_VALUE) +#define CSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE 64000000UL /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. + * This internal oscillator is mainly dedicated to provide a high precision clock to + * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. + * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency + * which is subject to manufacturing process variations. + */ +#if !defined (HSI48_VALUE) +#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. + The real value my vary depending on manufacturing process variations.*/ +#endif /* HSI48_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ + +#if !defined (LSI_STARTUP_TIME) +#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */ +#endif /* LSI_STARTUP_TIME */ + +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + + +/** + * @brief External clock source for SPI/SAI peripheral + * This value is used by the SPI/SAI HAL module to compute the SPI/SAI clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) +#define EXTERNAL_CLOCK_VALUE 12288000UL /*!< Value of the External clock in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ############################################ System Configuration ################################################ */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((1UL<<__NVIC_PRIO_BITS) - 1UL) /*!< tick interrupt priority (lowest by default) */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE) /*!< Enable prefetch */ + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)5) /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)5) /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ +#define PHY_BSR ((uint16_t)0x0001U) +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) + +/* ############################################ Assert Selection #################################################### */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* ############################################ Register callback feature configuration ############################# */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32h5xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ +#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DTS_REGISTER_CALLBACKS 0U /* DTS register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ +#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_I3C_REGISTER_CALLBACKS 0U /* I3C register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ +#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OPAMP register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ +#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ +#define USE_HAL_XSPI_REGISTER_CALLBACKS 0U /* XSPI register callback disabled */ + +/* ############################################ SPI peripheral configuration ######################################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver + * Activated: CRC code is present inside driver + * Deactivated: CRC code cleaned from driver + */ +#define USE_SPI_CRC 1U + + +/* Includes ----------------------------------------------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED +#include "stm32h5xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED +#include "stm32h5xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_ICACHE_MODULE_ENABLED +#include "stm32h5xx_hal_icache.h" +#endif /* HAL_ICACHE_MODULE_ENABLED */ + +#ifdef HAL_DCACHE_MODULE_ENABLED +#include "stm32h5xx_hal_dcache.h" +#endif /* HAL_DCACHE_MODULE_ENABLED */ + +#ifdef HAL_GTZC_MODULE_ENABLED +#include "stm32h5xx_hal_gtzc.h" +#endif /* HAL_GTZC_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED +#include "stm32h5xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_DTS_MODULE_ENABLED +#include "stm32h5xx_hal_dts.h" +#endif /* HAL_DTS_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED +#include "stm32h5xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_PKA_MODULE_ENABLED +#include "stm32h5xx_hal_pka.h" +#endif /* HAL_PKA_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED +#include "stm32h5xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED +#include "stm32h5xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED +#include "stm32h5xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED +#include "stm32h5xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED +#include "stm32h5xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED +#include "stm32h5xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED +#include "stm32h5xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED +#include "stm32h5xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED +#include "stm32h5xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED +#include "stm32h5xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED +#include "stm32h5xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED +#include "stm32h5xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED +#include "stm32h5xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_I3C_MODULE_ENABLED +#include "stm32h5xx_hal_i3c.h" +#endif /* HAL_I3C_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED +#include "stm32h5xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED +#include "stm32h5xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED +#include "stm32h5xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_XSPI_MODULE_ENABLED +#include "stm32h5xx_hal_xspi.h" +#endif /* HAL_XSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED +#include "stm32h5xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED +#include "stm32h5xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED +#include "stm32h5xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED +#include "stm32h5xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED +#include "stm32h5xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED +#include "stm32h5xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED +#include "stm32h5xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED +#include "stm32h5xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED +#include "stm32h5xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED +#include "stm32h5xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED +#include "stm32h5xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED +#include "stm32h5xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED +#include "stm32h5xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED +#include "stm32h5xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_COMP_MODULE_ENABLED +#include "stm32h5xx_hal_comp.h" +#endif /* HAL_COMP_MODULE_ENABLED */ + +#ifdef HAL_CORDIC_MODULE_ENABLED +#include "stm32h5xx_hal_cordic.h" +#endif /* HAL_CORDIC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED +#include "stm32h5xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32h5xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED +#include "stm32h5xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FDCAN_MODULE_ENABLED +#include "stm32h5xx_hal_fdcan.h" +#endif /* HAL_FDCAN_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED +#include "stm32h5xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_FMAC_MODULE_ENABLED +#include "stm32h5xx_hal_fmac.h" +#endif /* HAL_FMAC_MODULE_ENABLED */ + +#ifdef HAL_OPAMP_MODULE_ENABLED +#include "stm32h5xx_hal_opamp.h" +#endif /* HAL_OPAMP_MODULE_ENABLED */ + +#ifdef HAL_OTFDEC_MODULE_ENABLED +#include "stm32h5xx_hal_otfdec.h" +#endif /* HAL_OTFDEC_MODULE_ENABLED */ + +#ifdef HAL_PSSI_MODULE_ENABLED +#include "stm32h5xx_hal_pssi.h" +#endif /* HAL_PSSI_MODULE_ENABLED */ + +#ifdef HAL_RAMCFG_MODULE_ENABLED +#include "stm32h5xx_hal_ramcfg.h" +#endif /* HAL_RAMCFG_MODULE_ENABLED */ + +/* Exported macro ----------------------------------------------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ----------------------------------------------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_CONF_H */ diff --git a/hw/bsp/nucleo-h563zi/pkg.yml b/hw/bsp/nucleo-h563zi/pkg.yml new file mode 100644 index 0000000000..5ee9ec5a62 --- /dev/null +++ b/hw/bsp/nucleo-h563zi/pkg.yml @@ -0,0 +1,45 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/bsp/nucleo-h563zi +pkg.type: bsp +bsp.url: https://www.st.com/en/evaluation-tools/nucleo-h563zi.html +pkg.description: BSP definition for the stm32h563zi-nucleo board. +pkg.author: "Apache Mynewt " +pkg.homepage: "http://mynewt.apache.org/" +pkg.keywords: + - stm32 + - stm32h5 + - nucleo + +pkg.cflags: + - -DSTM32H563xx + - -DUSE_FULL_LL_DRIVER + +pkg.cflags.HARDFLOAT: + - -mfloat-abi=hard -mfpu=fpv4-sp-d16 + +pkg.deps: + - "@apache-mynewt-core/hw/mcu/stm/stm32h5xx" + - "@apache-mynewt-core/libc" + - "@apache-mynewt-core/hw/drivers/flash/spiflash" + - "@apache-mynewt-core/hw/bus/drivers/spi_hal" + - "@apache-mynewt-core/hw/scripts" + - "@apache-mynewt-core/hw/bus/drivers/i2c_hal" + - "@apache-mynewt-core/boot/startup" diff --git a/hw/bsp/nucleo-h563zi/src/hal_bsp.c b/hw/bsp/nucleo-h563zi/src/hal_bsp.c new file mode 100644 index 0000000000..a9ab39881e --- /dev/null +++ b/hw/bsp/nucleo-h563zi/src/hal_bsp.c @@ -0,0 +1,285 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include + +#include +#include +#include + +#include +#include +#include + +#include +#include + +#if MYNEWT_VAL(SPIFLASH) +#include +#endif + +#if MYNEWT_VAL(ETH_0) +#include +#include +#endif + +#if MYNEWT_VAL(PWM_0) || MYNEWT_VAL(PWM_1) || MYNEWT_VAL(PWM_2) +#include +#endif + +#if MYNEWT_VAL(PWM_0) +struct stm32_pwm_conf os_bsp_pwm0_cfg = { + .tim = TIM3, + .irq = TIM3_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_1) +struct stm32_pwm_conf os_bsp_pwm1_cfg = { + .tim = TIM4, + .irq = TIM4_IRQn, +}; +#endif +#if MYNEWT_VAL(PWM_2) +struct stm32_pwm_conf os_bsp_pwm2_cfg = { + .tim = TIM12, + .irq = TIM8_BRK_TIM12_IRQn, +}; +#endif + +#if MYNEWT_VAL(UART_0) +const struct stm32_uart_cfg os_bsp_uart0_cfg = { + .suc_uart = USART3, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART3EN, + .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART3, + .suc_irqn = USART3_IRQn, +}; +#endif + +#if MYNEWT_VAL(UART_1) +const struct stm32_uart_cfg os_bsp_uart1_cfg = { + .suc_uart = USART1, + .suc_rcc_reg = &RCC->APB2ENR, + .suc_rcc_dev = RCC_APB2ENR_USART1EN, + .suc_pin_tx = MYNEWT_VAL(UART_1_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_1_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_1_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_1_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART1, + .suc_irqn = USART1_IRQn, +}; +#endif + +#if MYNEWT_VAL(UART_2) +const struct stm32_uart_cfg os_bsp_uart2_cfg = { + .suc_uart = USART2, + .suc_rcc_reg = &RCC->APB1LENR, + .suc_rcc_dev = RCC_APB1LENR_USART2EN, + .suc_pin_tx = MYNEWT_VAL(UART_2_PIN_TX), + .suc_pin_rx = MYNEWT_VAL(UART_2_PIN_RX), + .suc_pin_rts = MYNEWT_VAL(UART_2_PIN_RTS), + .suc_pin_cts = MYNEWT_VAL(UART_2_PIN_CTS), + .suc_pin_af = GPIO_AF7_USART2, + .suc_irqn = USART2_IRQn, +}; +#endif + +#if MYNEWT_VAL(I2C_0) +/* + * The PB8 and PB9 pins are connected through jumpers in the board to + * both ADC_IN and I2C pins. To enable I2C functionality SB147/SB157 need + * to be removed (they are the default connections) and SB138/SB143 need + * to be shorted. + */ +const struct stm32_hal_i2c_cfg os_bsp_i2c0_cfg = { + .hic_i2c = I2C1, + .hic_rcc_reg = &RCC->APB1LENR, + .hic_rcc_dev = RCC_APB1LENR_I2C1EN, + .get_pclk = STM32_I2C1_GET_CLOCK_FREQ, + .hic_pin_sda = MYNEWT_VAL(I2C_0_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_0_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C1, + .hic_10bit = 0, + .hic_timingr = 0xA0303048, /* 100kHz at 544 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_1) +const struct stm32_hal_i2c_cfg os_bsp_i2c1_cfg = { + .hic_i2c = I2C2, + .hic_rcc_reg = &RCC->APB1LENR, + .hic_rcc_dev = RCC_APB1LENR_I2C2EN, + .get_pclk = STM32_I2C2_GET_CLOCK_FREQ, + .hic_pin_sda = MYNEWT_VAL(I2C_1_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_1_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C2, + .hic_10bit = 0, + .hic_timingr = 0xA0303048, /* 100kHz at 544 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_2) +const struct stm32_hal_i2c_cfg os_bsp_i2c2_cfg = { + .hic_i2c = I2C3, + .hic_rcc_reg = &RCC->APB1LENR, + .hic_rcc_dev = RCC_APB1LENR_I2C3EN, + .get_pclk = STM32_I2C3_GET_CLOCK_FREQ, + .hic_pin_sda = MYNEWT_VAL(I2C_2_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_2_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C3, + .hic_10bit = 0, + .hic_timingr = 0xA0303048, /* 100kHz at 544 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(I2C_3) +const struct stm32_hal_i2c_cfg os_bsp_i2c3_cfg = { + .hic_i2c = I2C4, + .hic_rcc_reg = &RCC->APB4ENR, + .hic_rcc_dev = RCC_APB4ENR_I2C4EN, + .get_pclk = STM32_I2C4_GET_CLOCK_FREQ, + .hic_pin_sda = MYNEWT_VAL(I2C_3_PIN_SDA), + .hic_pin_scl = MYNEWT_VAL(I2C_3_PIN_SCL), + .hic_pin_af = GPIO_AF4_I2C4, + .hic_10bit = 0, + .hic_timingr = 0xA0303048, /* 100kHz at 544 MHz system clock */ +}; +#endif + +#if MYNEWT_VAL(ETH_0) +const struct stm32_eth_cfg os_bsp_eth0_cfg = { + /* + * PORTA + * PA1 - ETH_RMII_REF_CLK + * PA2 - ETH_RMII_MDIO + * PA7 - ETH_RMII_CRS_DV + */ + .sec_port_mask[0] = (1 << 1) | (1 << 2) | (1 << 7), + + /* + * PORTB + * PB15 - ETH_RMII_TXD1 + */ + .sec_port_mask[1] = (1 << 15), + + /* + * PORTC + * PC1 - ETH_RMII_MDC + * PC4 - ETH_RMII_RXD0 + * PC5 - ETH_RMII_RXD1 + */ + .sec_port_mask[2] = (1 << 1) | (1 << 4) | (1 << 5), + + /* + * PORTG + * PG11 - ETH_RMII_TXEN + * PG13 - ETH_RMII_TXD0 + */ + .sec_port_mask[6] = (1 << 11) | (1 << 13), + .sec_phy_type = LAN_8742_RMII, + .sec_phy_irq = -1 +}; +#endif + +static const struct hal_bsp_mem_dump dump_cfg[] = { + [0] = { + .hbmd_start = &_ram_start, + .hbmd_size = RAM_SIZE, + }, +}; + +extern const struct hal_flash stm32_flash_dev; + +static const struct hal_flash *flash_devs[] = { + [0] = &stm32_flash_dev, +#if MYNEWT_VAL(SPIFLASH) + [1] = &spiflash_dev.hal, +#endif +}; + +const struct hal_flash * +hal_bsp_flash_dev(uint8_t id) +{ + if (id >= ARRAY_SIZE(flash_devs)) { + return NULL; + } + + return flash_devs[id]; +} + +const struct hal_bsp_mem_dump * +hal_bsp_core_dump(int *area_cnt) +{ + *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]); + return dump_cfg; +} + +void +hal_bsp_init(void) +{ + stm32_periph_create(); +} + +void +hal_bsp_deinit(void) +{ + Cortex_DisableAll(); + + RCC->AHB1ENR = 0xD0000100; + RCC->AHB2ENR = 0xC0000000; + RCC->AHB4ENR = 0x00000000; + RCC->APB1LENR = 0; + RCC->APB1HENR = 0; + RCC->APB2ENR = 0; + RCC->APB3ENR = 0; + + RCC->AHB1RSTR = 0x000AD003; + RCC->AHB2RSTR = 0x001F1DFF; + RCC->AHB4RSTR = 0x00111880; + RCC->APB1LRSTR = 0xBFFEC1FF; + RCC->APB1HRSTR = 0x0080022B; + RCC->APB2RSTR = 0x017F7800; + RCC->APB3RSTR = 0x0010F9E0; + RCC->AHB1RSTR = 0; + RCC->AHB2RSTR = 0; + RCC->AHB4RSTR = 0; + RCC->APB1LRSTR = 0; + RCC->APB1HRSTR = 0; + RCC->APB2RSTR = 0; + RCC->APB3RSTR = 0; +} + +/** + * Returns the configured priority for the given interrupt. If no priority + * configured, return the priority passed in + * + * @param irq_num + * @param pri + * + * @return uint32_t + */ +uint32_t +hal_bsp_get_nvic_priority(int irq_num, uint32_t pri) +{ + /* Add any interrupt priorities configured by the bsp here */ + return pri; +} diff --git a/hw/bsp/nucleo-h563zi/syscfg.yml b/hw/bsp/nucleo-h563zi/syscfg.yml new file mode 100644 index 0000000000..b29a8b7e7d --- /dev/null +++ b/hw/bsp/nucleo-h563zi/syscfg.yml @@ -0,0 +1,68 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + +syscfg.vals: + STM32_FLASH_SIZE_KB: 2048 + MCU_RAM_START: 0x20000000 + MCU_RAM_SIZE: 640K + MCU_TARGET: STM32H563 + STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE0' + STM32_CLOCK_HSI: 1 + STM32_CLOCK_HSIDIV: LL_RCC_HSI_DIV_1 + STM32_CLOCK_HSE: 1 + # 8MHz From ST-LINK + STM32_CLOCK_HSE_BYPASS: 1 + STM32_CLOCK_PLL1_SOURCE: LL_RCC_PLL1SOURCE_HSE + STM32_CLOCK_PLL1_PLLM: 4 # 8 MHZ / 4 = 2 MHz implies RCC_PLL1_VCIRANGE_1 + STM32_CLOCK_PLL1_PLLN: 250 # VCO = 2 MHz * 250 = 500 MHz + STM32_CLOCK_PLL1_PLLP: 2 # PLLP = 250 MHz + STM32_CLOCK_PLL1_PLLQ: 2 # PLPQ = 250 MHz + STM32_CLOCK_PLL1_PLLR: 2 # PLPQ = 250 MHz + STM32_CLOCK_PLL1_RGE: 'RCC_PLL1_VCIRANGE_1' + STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1' + STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV1' + STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1' + STM32_CLOCK_APB3_DIVIDER: 'RCC_HCLK_DIV1' + STM32_FLASH_LATENCY: 'FLASH_LATENCY_6' + STM32_ENABLE_ICACHE: 1 + WATCHDOG_INTERVAL: 28000 + UART_0_PIN_TX: 'MCU_GPIO_PORTD(8)' + UART_0_PIN_RX: 'MCU_GPIO_PORTD(9)' + SPI_0_PIN_SS: 'MCU_GPIO_PORTD(14)' + SPI_0_PIN_SCK: ARDUINO_PIN_SCK + SPI_0_PIN_MISO: ARDUINO_PIN_MISO + SPI_0_PIN_MOSI: ARDUINO_PIN_MOSI + I2C_0_PIN_SCL: 'MCU_GPIO_PORTB(8)' + I2C_0_PIN_SDA: 'MCU_GPIO_PORTB(9)' + I2C_1_PIN_SCL: 'MCU_GPIO_PORTF(1)' + I2C_1_PIN_SDA: 'MCU_GPIO_PORTF(0)' + I2C_2_PIN_SCL: 'MCU_GPIO_PORTA(8)' + I2C_2_PIN_SDA: 'MCU_GPIO_PORTC(9)' + I2C_3_PIN_SCL: 'MCU_GPIO_PORTD(12)' + I2C_3_PIN_SDA: 'MCU_GPIO_PORTD(13)' + TIMER_0_TIM: 'TIM12' + TIMER_1_TIM: 'TIM13' + TIMER_2_TIM: 'TIM14' + + # Flasher parameters + MYNEWT_DOWNLOADER: stm32_programmer_cli + MYNEWT_DOWNLOADER_MFG_IMAGE_FLASH_OFFSET: 0x08000000 + JLINK_TARGET: STM32H563ZI diff --git a/hw/drivers/hash/hash_stm32/src/hash_stm32.c b/hw/drivers/hash/hash_stm32/src/hash_stm32.c index de4c03a628..0e3cc88e9d 100644 --- a/hw/drivers/hash/hash_stm32/src/hash_stm32.c +++ b/hw/drivers/hash/hash_stm32/src/hash_stm32.c @@ -35,6 +35,14 @@ static uint32_t g_algos = 0; #else static uint32_t g_algos = HASH_ALGO_SHA224 | HASH_ALGO_SHA256; #endif +#if defined(STM32H5) +/* Missing defines */ +#define HASH_DATATYPE_8B HASH_BYTE_SWAP + +#define __HAL_HASH_SET_NBVALIDBITS(__SIZE__) \ + MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U)) +#define __HAL_HASH_START_DIGEST() SET_BIT(HASH->STR, HASH_STR_DCAL) +#endif static int stm32_hash_start(struct hash_dev *hash, void *ctx, uint16_t algo) diff --git a/hw/drivers/lwip/stm32_eth/src/stm32_eth.c b/hw/drivers/lwip/stm32_eth/src/stm32_eth.c index 9208b72754..2e3298fd53 100644 --- a/hw/drivers/lwip/stm32_eth/src/stm32_eth.c +++ b/hw/drivers/lwip/stm32_eth/src/stm32_eth.c @@ -22,14 +22,31 @@ #include #include #include +#include #if MYNEWT_VAL(MCU_STM32F4) #include #include + +#define ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE + #endif #if MYNEWT_VAL(MCU_STM32F7) #include #include + +#define ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE + +#endif +#if MYNEWT_VAL(MCU_STM32H5) + +#define ETH_CLK_ENABLE() \ + do { \ + __HAL_RCC_ETH_CLK_ENABLE(); \ + __HAL_RCC_ETHTX_CLK_ENABLE(); \ + __HAL_RCC_ETHRX_CLK_ENABLE(); \ + } while (0) + #endif #if MYNEWT_VAL(MCU_STM32H7) #include @@ -39,11 +56,13 @@ #define PHY_BSR ((uint16_t)0x0001U) #define PHY_LINKED_STATUS ((uint16_t)0x0004U) -#define __HAL_RCC_ETH_CLK_ENABLE() do { \ - __HAL_RCC_ETH1MAC_CLK_ENABLE(); \ - __HAL_RCC_ETH1TX_CLK_ENABLE(); \ - __HAL_RCC_ETH1RX_CLK_ENABLE(); \ -} while (0) +#define ETH_CLK_ENABLE() \ + do { \ + __HAL_RCC_ETH1MAC_CLK_ENABLE(); \ + __HAL_RCC_ETH1TX_CLK_ENABLE(); \ + __HAL_RCC_ETH1RX_CLK_ENABLE(); \ + } while (0) + #endif #include @@ -346,7 +365,7 @@ stm32_lwip_init(struct netif *nif) } NVIC_SetVector(ETH_IRQn, (uint32_t)stm32_eth_isr); - __HAL_RCC_ETH_CLK_ENABLE(); + ETH_CLK_ENABLE(); ses->st_eth.Instance = ETH; ses->st_eth.Init.RxDesc = ses->st_rx_descs; diff --git a/hw/mcu/stm/stm32_common/src/hal_flash.c b/hw/mcu/stm/stm32_common/src/hal_flash.c index 7acf028f2e..da31917965 100644 --- a/hw/mcu/stm/stm32_common/src/hal_flash.c +++ b/hw/mcu/stm/stm32_common/src/hal_flash.c @@ -91,10 +91,12 @@ stm32_flash_write_linear(const struct hal_flash *dev, uint32_t address, { uint64_t val[VAL_SIZE]; uint32_t i; - int rc; + int rc = 0; uint8_t align; uint32_t num_words; - +#if defined(STM32H5) + bool icache_enabled = LL_ICACHE_IsEnabled(); +#endif align = dev->hf_align; #if MYNEWT_VAL(MCU_FLASH_MIN_WRITE_SIZE) == 1 @@ -134,7 +136,7 @@ stm32_flash_write_linear(const struct hal_flash *dev, uint32_t address, rc = HAL_FLASH_Program(FLASH_PROGRAM_TYPE, address, val[0]); #endif if (rc != HAL_OK) { - return rc; + break; } address += align; @@ -151,7 +153,13 @@ stm32_flash_write_linear(const struct hal_flash *dev, uint32_t address, } } - return 0; +#ifdef STM32H5 + if (icache_enabled) { + LL_ICACHE_Invalidate(); + } +#endif + + return rc; } #endif diff --git a/hw/mcu/stm/stm32_common/src/hal_gpio.c b/hw/mcu/stm/stm32_common/src/hal_gpio.c index 93378ccd33..112c5aa0bf 100644 --- a/hw/mcu/stm/stm32_common/src/hal_gpio.c +++ b/hw/mcu/stm/stm32_common/src/hal_gpio.c @@ -142,7 +142,7 @@ struct ext_irqs volatile uint32_t irq2; volatile uint32_t irq3; volatile uint32_t irq4; -#if defined(STM32U5) || defined(STM32L5) +#if defined(STM32U5) || defined(STM32L5) || defined(STM32H5) volatile uint32_t irq5; volatile uint32_t irq6; volatile uint32_t irq7; @@ -231,7 +231,7 @@ ext_irq4(void) ext_irq_handler(4); } -#if defined(STM32U5) || defined(STM32L5) +#if defined(STM32U5) || defined(STM32L5) || defined(STM32H5) static void ext_irq5(void) @@ -500,7 +500,7 @@ hal_gpio_pin_to_irq(int pin) } else { irqn = EXTI4_15_IRQn; } -#elif defined(STM32U5) || defined(STM32L5) +#elif defined(STM32U5) || defined(STM32L5) || defined(STM32H5) irqn = EXTI0_IRQn + index; #else if (index <= 4) { @@ -553,7 +553,7 @@ hal_gpio_set_nvic(IRQn_Type irqn) case EXTI4_IRQn: isr = (uint32_t)&ext_irq4; break; -#if defined(STM32U5) || defined(STM32L5) +#if defined(STM32U5) || defined(STM32L5) || defined(STM32H5) case EXTI5_IRQn: isr = (uint32_t)&ext_irq5; break; @@ -971,8 +971,9 @@ hal_gpio_irq_enable(int pin) mask = GPIO_MASK(pin); __HAL_DISABLE_INTERRUPTS(ctx); -#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || \ - MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32G0) +#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) || \ + MYNEWT_VAL(MCU_STM32H5) || MYNEWT_VAL(MCU_STM32H7) || \ + MYNEWT_VAL(MCU_STM32G0) || MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32U5) EXTI->IMR1 |= mask; #else EXTI->IMR |= mask; @@ -994,8 +995,10 @@ hal_gpio_irq_disable(int pin) mask = GPIO_MASK(pin); __HAL_DISABLE_INTERRUPTS(ctx); -#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || \ - MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32G0) +#if MYNEWT_VAL(MCU_STM32L4) || MYNEWT_VAL(MCU_STM32WB) || \ + MYNEWT_VAL(MCU_STM32H5) || MYNEWT_VAL(MCU_STM32H7) || \ + MYNEWT_VAL(MCU_STM32G0) || MYNEWT_VAL(MCU_STM32G4) || MYNEWT_VAL(MCU_STM32U5) + EXTI->IMR1 |= mask; #else EXTI->IMR &= ~mask; diff --git a/hw/mcu/stm/stm32_common/src/hal_os_tick.c b/hw/mcu/stm/stm32_common/src/hal_os_tick.c index a61e53b133..608c7f1f61 100644 --- a/hw/mcu/stm/stm32_common/src/hal_os_tick.c +++ b/hw/mcu/stm/stm32_common/src/hal_os_tick.c @@ -59,7 +59,7 @@ stm32_wfi_from_ram(void) #define SYNCH_PREDIV (32768 / (ASYNCH_PREDIV + 1) - 1) #define SUB_SECONDS_BITS 12 -#if defined(STM32L0) || defined(STM32F0) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32F0) || defined(STM32U5) || defined(STM32H5) #define RTC_IRQ RTC_IRQn #elif defined(STM32G0) #define RTC_IRQ RTC_TAMP_IRQn @@ -406,7 +406,7 @@ os_tick_init(uint32_t os_ticks_per_sec, int prio) /* * Keep clocking debug even when CPU is sleeping, stopped or in standby. */ -#if MYNEWT_VAL(MCU_STM32F0) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32F0) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) DBGMCU->CR |= (DBGMCU_CR_DBG_STOP | DBGMCU_CR_DBG_STANDBY); #elif MYNEWT_VAL(MCU_STM32H7) DBGMCU->CR |= (DBGMCU_CR_DBG_SLEEPD1 | DBGMCU_CR_DBG_STOPD1 | DBGMCU_CR_DBG_STANDBYD1); diff --git a/hw/mcu/stm/stm32_common/src/hal_uart.c b/hw/mcu/stm/stm32_common/src/hal_uart.c index cd356763c0..83c52149b1 100644 --- a/hw/mcu/stm/stm32_common/src/hal_uart.c +++ b/hw/mcu/stm/stm32_common/src/hal_uart.c @@ -149,8 +149,8 @@ static struct hal_uart_irq uart_irqs[3]; # define TC USART_ISR_TC # define RXDR(x) ((x)->RDR) # define TXDR(x) ((x)->TDR) -#if MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32G4) || \ - MYNEWT_VAL(MCU_STM32G0) +#if MYNEWT_VAL(MCU_STM32WB) || MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32G4) ||\ + MYNEWT_VAL(MCU_STM32G0) || MYNEWT_VAL(MCU_STM32H5) # define BAUD(x,y) UART_DIV_SAMPLING16((x), (y), UART_PRESCALER_DIV1) #else # define BAUD(x,y) UART_DIV_SAMPLING16((x), (y)) diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c index 4e0e619369..156d44f971 100644 --- a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c +++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c @@ -54,7 +54,7 @@ HAL_StatusTypeDef HAL_SPI_QueueTransmit(SPI_HandleTypeDef *hspi, uint8_t *pData, #error "This MCU currently does not support SPI slave" #endif -#if !MYNEWT_VAL(MCU_STM32H7) && !defined(STM32U5) +#if !MYNEWT_VAL(MCU_STM32H7) && !defined(STM32U5) && !defined(STM32H5) #define RXDR DR #define TXDR DR #endif @@ -128,7 +128,7 @@ HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) } #endif -#if ((!MYNEWT_VAL(MCU_STM32H7) && !defined(STM32U5)) || !SPI_HAS_FIFO) +#if (!(MYNEWT_VAL(MCU_STM32H7) || defined(STM32U5) || defined(STM32H5)) || !SPI_HAS_FIFO) static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) { @@ -179,7 +179,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, while ((hspi->Instance->SR & Fifo) != State) { -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) if ((Fifo == SPI_SR_RXPLVL) && (State == SPI_RX_FIFO_0PACKET)) { tmpreg = *((__IO uint8_t *)&hspi->Instance->RXDR); @@ -222,7 +222,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_TXC, SPI_SR_TXC, Timeout, Tickstart) != HAL_OK) { @@ -256,7 +256,7 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_ static HAL_StatusTypeDef SPI_EndTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) { -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) /* Control if the TX fifo is empty */ if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_TXC, SPI_SR_TXC, Timeout, Tickstart) != HAL_OK) { @@ -644,7 +644,7 @@ HAL_StatusTypeDef HAL_SPI_QueueTransmit(SPI_HandleTypeDef *hspi, uint8_t *pData, #endif /* MYNEWT: in slave mode write 1st byte to DR */ -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) if ((hspi->Instance->CFG2 & SPI_CFG2_MASTER) == 0) { hspi->TxISR(hspi); } @@ -757,7 +757,7 @@ HAL_StatusTypeDef HAL_SPI_Slave_Queue_TransmitReceive(SPI_HandleTypeDef *hspi, u //__HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); /* MYNEWT: in slave mode write 1st byte to DR */ -#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) +#if MYNEWT_VAL(MCU_STM32H7) || MYNEWT_VAL(MCU_STM32U5) || MYNEWT_VAL(MCU_STM32H5) if ((hspi->Instance->CFG2 & SPI_CFG2_MASTER) == 0) { hspi->TxISR(hspi); } diff --git a/hw/mcu/stm/stm32_common/src/stm32_hw_id.c b/hw/mcu/stm/stm32_common/src/stm32_hw_id.c index 8ef7877280..1a80644f8b 100644 --- a/hw/mcu/stm/stm32_common/src/stm32_hw_id.c +++ b/hw/mcu/stm/stm32_common/src/stm32_hw_id.c @@ -23,6 +23,11 @@ #include "mcu/stm32_hal.h" #include +#ifdef STM32H5 +#include +#include +#endif + #ifndef min #define min(a, b) ((a)<(b)?(a):(b)) #endif @@ -35,13 +40,40 @@ hal_bsp_hw_id_len(void) return STM32_HW_ID_LEN; } +#ifndef DCACHE1 +/* H503 devices do not have DCACHE */ +#define LL_DCACHE_IsEnabled(dcache) 0 +#define LL_DCACHE_Enable(dcache) +#define LL_DCACHE_Disable(dcache) +#endif + int hal_bsp_hw_id(uint8_t *id, int max_len) { int cnt; +#ifdef STM32H5 + uint32_t dcache_enabled = LL_DCACHE_IsEnabled(DCACHE1); + uint32_t icache_enabled = LL_ICACHE_IsEnabled(); + + if (dcache_enabled) { + LL_DCACHE_Disable(DCACHE1); + } + if (icache_enabled) { + LL_ICACHE_Disable(); + } +#endif cnt = min(STM32_HW_ID_LEN, max_len); memcpy(id, (void *)UID_BASE, cnt); +#ifdef STM32H5 + if (icache_enabled) { + LL_ICACHE_Enable(); + } + if (dcache_enabled) { + LL_DCACHE_Enable(DCACHE1); + } +#endif + return cnt; } diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/cmsis_nvic.h b/hw/mcu/stm/stm32h5xx/include/mcu/cmsis_nvic.h new file mode 100644 index 0000000000..bb28340a70 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/cmsis_nvic.h @@ -0,0 +1,33 @@ +/* mbed Microcontroller Library - cmsis_nvic + * Copyright (c) 2009-2011 ARM Limited. All rights reserved. + * + * CMSIS-style functionality to support dynamic vectors + */ + +#ifndef MBED_CMSIS_NVIC_H +#define MBED_CMSIS_NVIC_H + +#include + +extern uint32_t __isr_vector_start[]; +extern uint32_t __isr_vector_end[]; + +/* Extract number of vectors from .interrupt section size */ +#define NVIC_NUM_VECTORS (__isr_vector_end - __isr_vector_start) +#define NVIC_USER_IRQ_OFFSET 16 + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void NVIC_Relocate(void); +void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); +uint32_t NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/cortex_m33.h b/hw/mcu/stm/stm32h5xx/include/mcu/cortex_m33.h new file mode 100644 index 0000000000..1a5b046dda --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/cortex_m33.h @@ -0,0 +1,39 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_CORTEX_M33_H__ +#define __MCU_CORTEX_M33_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +static inline void +hal_debug_break(void) +{ + __BKPT(1); +} + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_CORTEX_M33_H__ */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/mcu.h b/hw/mcu/stm/stm32h5xx/include/mcu/mcu.h new file mode 100644 index 0000000000..d992abe9bf --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/mcu.h @@ -0,0 +1,39 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_MCU_H_ +#define __MCU_MCU_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(STM32H503xx) +#define STM32_SYSTEM_MEMORY 0x0BF87000 +#else +#define STM32_SYSTEM_MEMORY 0x0BF97000 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_MCU_H_ */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/mcu_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/mcu_vectors.h new file mode 100644 index 0000000000..95bf6b3162 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/mcu_vectors.h @@ -0,0 +1,34 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#if defined(STM32H573xx) +#include "vectors/stm32h573xx_vectors.h" +#elif defined(STM32H563xx) +#include "vectors/stm32h563xx_vectors.h" +#elif defined(STM32H562xx) +#include "vectors/stm32h562xx_vectors.h" +#elif defined(STM32H523xx) +#include "vectors/stm32h523xx_vectors.h" +#elif defined(STM32H533xx) +#include "vectors/stm32h533xx_vectors.h" +#elif defined(STM32H503xx) +#include "vectors/stm32h503xx_vectors.h" +#else +#error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)" +#endif diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h b/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h new file mode 100644 index 0000000000..906e0ee5d9 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/per_clocks.h @@ -0,0 +1,370 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef PER_CLOCKS_H +#define PER_CLOCKS_H + +#ifndef STM32_PER_CLOCK_DEF +#error "File should not be explicitly included" +#else + +STM32_PER_CLOCK_DEF(GPDMA1); +STM32_PER_CLOCK_DEF(GPDMA2); +#ifdef SAI1 +STM32_PER_CLOCK_DEF(SAI1); +#endif +#ifdef SAI2 +STM32_PER_CLOCK_DEF(SAI2); +#endif +#ifdef SAI3 +STM32_PER_CLOCK_DEF(SAI3); +#endif +STM32_PER_CLOCK_DEF(GPIOA); +STM32_PER_CLOCK_DEF(GPIOB); +STM32_PER_CLOCK_DEF(GPIOC); +STM32_PER_CLOCK_DEF(GPIOD); +STM32_PER_CLOCK_DEF(GPIOE); +STM32_PER_CLOCK_DEF(GPIOF); +STM32_PER_CLOCK_DEF(GPIOG); +STM32_PER_CLOCK_DEF(GPIOH); +#ifdef GPIOI +STM32_PER_CLOCK_DEF(GPIOI); +#endif +STM32_PER_CLOCK_DEF(USART1); +STM32_PER_CLOCK_DEF(USART2); +STM32_PER_CLOCK_DEF(USART3); +STM32_PER_CLOCK_DEF(UART4); +STM32_PER_CLOCK_DEF(UART5); +STM32_PER_CLOCK_DEF(USART6); +#ifdef UART7 +STM32_PER_CLOCK_DEF(UART7); +#endif +#ifdef UART8 +STM32_PER_CLOCK_DEF(UART8); +#endif +#ifdef UART9 +STM32_PER_CLOCK_DEF(UART9); +#endif +#ifdef USART10 +STM32_PER_CLOCK_DEF(USART10); +#endif +#ifdef USART11 +STM32_PER_CLOCK_DEF(USART11); +#endif +STM32_PER_CLOCK_DEF(SPI1); +STM32_PER_CLOCK_DEF(SPI2); +STM32_PER_CLOCK_DEF(SPI3); +STM32_PER_CLOCK_DEF(SPI4); +#ifdef SPI5 +STM32_PER_CLOCK_DEF(SPI5); +#endif +#ifdef SPI6 +STM32_PER_CLOCK_DEF(SPI6); +#endif +STM32_PER_CLOCK_DEF(I2C1); +STM32_PER_CLOCK_DEF(I2C2); +STM32_PER_CLOCK_DEF(I2C3); +#ifdef I2C4 +STM32_PER_CLOCK_DEF(I2C4); +#endif + +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PCLK2); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, HSI); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, CSI); +STM32_CLKSEL_DEF2(USART1, CCIPR1, USART1SEL, LSE); + +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PCLK1); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, HSI); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, CSI); +STM32_CLKSEL_DEF2(USART2, CCIPR1, USART2SEL, LSE); + +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PCLK1); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, HSI); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, CSI); +STM32_CLKSEL_DEF2(USART3, CCIPR1, USART3SEL, LSE); + +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PCLK1); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, HSI); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, CSI); +STM32_CLKSEL_DEF2(UART4, CCIPR1, UART4SEL, LSE); + +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PCLK1); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, HSI); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, CSI); +STM32_CLKSEL_DEF2(UART5, CCIPR1, UART5SEL, LSE); + +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PCLK1); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, HSI); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, CSI); +STM32_CLKSEL_DEF2(USART6, CCIPR1, USART6SEL, LSE); + +#ifdef UART7 +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, PCLK1); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, HSI); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, CSI); +STM32_CLKSEL_DEF2(UART7, CCIPR1, UART7SEL, LSE); +#endif + +#ifdef UART8 +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, PCLK1); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, HSI); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, CSI); +STM32_CLKSEL_DEF2(UART8, CCIPR1, UART8SEL, LSE); +#endif + +#ifdef UART9 +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, PCLK1); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, HSI); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, CSI); +STM32_CLKSEL_DEF2(UART9, CCIPR1, UART9SEL, LSE); +#endif + +#ifdef USART10 +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, PCLK1); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, HSI); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, CSI); +STM32_CLKSEL_DEF2(USART10, CCIPR1, USART10SEL, LSE); +#endif + +#ifdef USART11 +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, PCLK1); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, PLL2Q); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, PLL3Q); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, HSI); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, CSI); +STM32_CLKSEL_DEF2(USART11, CCIPR2, USART11SEL, LSE); +#endif + +#ifdef USART12 +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, PCLK1); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, PLL2Q); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, PLL3Q); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, HSI); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, CSI); +STM32_CLKSEL_DEF2(UART12, CCIPR2, UART12SEL, LSE); +#endif + +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM1, CCIPR2, LPTIM1SEL, CLKP); + +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PCLK1); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM2, CCIPR2, LPTIM2SEL, CLKP); + +#ifdef LPTIM3 +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM3, CCIPR2, LPTIM3SEL, CLKP); +#endif + +#ifdef LPTIM4 +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM4, CCIPR2, LPTIM4SEL, CLKP); +#endif + +#ifdef LPTIM5 +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM5, CCIPR2, LPTIM5SEL, CLKP); +#endif + +#ifdef LPTIM6 +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, PCLK3); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, PLL2P); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, PLL3R); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, LSE); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, LSI); +STM32_CLKSEL_DEF2(LPTIM6, CCIPR2, LPTIM6SEL, CLKP); +#endif + + +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL1Q); +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL2P); +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PLL3P); +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, PIN); +STM32_CLKSEL_DEF2(SPI1, CCIPR3, SPI1SEL, CLKP); + +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL1Q); +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL2P); +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PLL3P); +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, PIN); +STM32_CLKSEL_DEF2(SPI2, CCIPR3, SPI2SEL, CLKP); + +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL1Q); +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL2P); +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PLL3P); +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, PIN); +STM32_CLKSEL_DEF2(SPI3, CCIPR3, SPI3SEL, CLKP); + +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PCLK2); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PLL2Q); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, PLL3Q); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, HSI); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, CSI); +STM32_CLKSEL_DEF2(SPI4, CCIPR3, SPI4SEL, HSE); + +#ifdef SPI5 +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, PCLK3); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, PLL2Q); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, PLL3Q); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, HSI); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, CSI); +STM32_CLKSEL_DEF2(SPI5, CCIPR3, SPI5SEL, HSE); +#endif + +#ifdef SPI6 +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, PCLK2); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, PLL2Q); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, PLL3Q); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, HSI); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, CSI); +STM32_CLKSEL_DEF2(SPI6, CCIPR3, SPI6SEL, HSE); +#endif + +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PCLK3); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PLL2Q); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, PLL3Q); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, HSI); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, CSI); +STM32_CLKSEL_DEF1(LPUART1, CCIPR3, LPUART1SEL, LSE); + +STM32_CLKSEL_DEF1(SYSTICK, CCIPR4, SYSTICKSEL, HCLKDIV8); +STM32_CLKSEL_DEF1(SYSTICK, CCIPR4, SYSTICKSEL, LSI); +STM32_CLKSEL_DEF1(SYSTICK, CCIPR4, SYSTICKSEL, LSE); + +STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, PLL1Q); +STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, PLL3Q); +STM32_CLKSEL_DEF1(USB, CCIPR4, USBSEL, HSI48); + +STM32_CLKSEL_DEF2(SDMMC1, CCIPR4, SDMMC1SEL, PLL1Q); +STM32_CLKSEL_DEF2(SDMMC1, CCIPR4, SDMMC1SEL, PLL2R); + +#ifdef SDMMC2 +STM32_CLKSEL_DEF2(SDMMC2, CCIPR4, SDMMC2SEL, PLL1Q); +STM32_CLKSEL_DEF2(SDMMC2, CCIPR4, SDMMC2SEL, PLL2R); +#endif + +STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, PCLK1); +STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, PLL3R); +STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, HSI); +STM32_CLKSEL_DEF2(I2C1, CCIPR4, I2C1SEL, CSI); + +STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, PCLK1); +STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, PLL3R); +STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, HSI); +STM32_CLKSEL_DEF2(I2C2, CCIPR4, I2C2SEL, CSI); + +STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, PCLK3); +STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, PLL3R); +STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, HSI); +STM32_CLKSEL_DEF2(I2C3, CCIPR4, I2C3SEL, CSI); + +#ifdef I2C4 +STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, PCLK3); +STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, PLL3R); +STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, HSI); +STM32_CLKSEL_DEF2(I2C4, CCIPR4, I2C4SEL, CSI); +#endif + +STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, PCLK1); +STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, PLL3R); +STM32_CLKSEL_DEF2(I3C1, CCIPR4, I3C1SEL, HSI); + +#ifdef I3C2 +STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, PCLK3); +STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, PLL3R); +STM32_CLKSEL_DEF2(I3C2, CCIPR4, I3C2SEL, HSI); +#endif + +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, HCLK); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, SYSCLK); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, PLL2R); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, HSE); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, HSI); +STM32_CLKSEL_DEF1(ADCDAC, CCIPR5, ADCDACSEL, CSI); + +STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, HSI48); +STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, PLL1Q); +STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, LSE); +STM32_CLKSEL_DEF1(RNG, CCIPR5, RNGSEL, LSI); + +STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, LSE); +STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, LSI); +STM32_CLKSEL_DEF1(CEC, CCIPR5, CECSEL, CSI_DIV122); + +STM32_CLKSEL_DEF1(FDCAN, CCIPR5, FDCANSEL, HSE); +STM32_CLKSEL_DEF1(FDCAN, CCIPR5, FDCANSEL, PLL1Q); +STM32_CLKSEL_DEF1(FDCAN, CCIPR5, FDCANSEL, PLL2Q); + +#ifdef SAI1 +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, PLL1Q); +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, PLL2P); +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, PLL3P); +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, PIN); +STM32_CLKSEL_DEF2(SAI1, CCIPR5, SAI1SEL, CLKP); +#endif + +#ifdef SAI2 +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, PLL1Q); +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, PLL2P); +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, PLL3P); +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, PIN); +STM32_CLKSEL_DEF2(SAI2, CCIPR5, SAI2SEL, CLKP); +#endif + +#endif + +#endif diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32_clock.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_clock.h new file mode 100644 index 0000000000..83b1ba0a1a --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_clock.h @@ -0,0 +1,67 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef _STM32_CLOCK_H +#define _STM32_CLOCK_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef const struct stm32_clock *stm32_clock_t; +typedef const struct stm32_clock_ops *stm32_clock_ops_t; +typedef const struct stm32_clock_src *stm32_clock_src_t; + +struct stm32_clock_ops { + void (*enable)(stm32_clock_t clock); + void (*disable)(stm32_clock_t clock); +}; + +struct stm32_clock { + stm32_clock_ops_t ops; +}; + +void stm32_clock_enable(stm32_clock_t clock); +void stm32_clock_disable(stm32_clock_t clock); + +#ifndef STM32_PER_CLOCK_DEF +#define STM32_PER_CLOCK_DEF(per) \ +extern const struct stm32_clock _##per##_clock;\ +static const struct stm32_clock *const per##_clock = &_##per##_clock; + +#define PER_CLOCK(per) per##_clock + +#define STM32_CLKSEL_DEF1(per, rcc_reg, reg_field, reg_val)\ +extern const struct stm32_clock_src _##per##_##reg_val;\ +static stm32_clock_t const per##_##reg_val __unused = (stm32_clock_t)&_##per##_##reg_val; + +#define STM32_CLKSEL_DEF2(per, rcc_reg, reg_field, reg_val)\ +extern const struct stm32_clock_src _##per##_##reg_val;\ +static stm32_clock_t const per##_##reg_val __unused = (stm32_clock_t)&_##per##_##reg_val; + +#include +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_CLOCK_H */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32_hal.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_hal.h new file mode 100644 index 0000000000..4a9b44e148 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_hal.h @@ -0,0 +1,126 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef STM32_HAL_H +#define STM32_HAL_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#include +#include + +#include "stm32h5xx_mynewt_hal.h" + +/* hal_watchdog */ +#include +#define STM32_HAL_WATCHDOG_CUSTOM_INIT(x) \ + do { \ + (x)->Init.Window = IWDG_WINDOW_DISABLE; \ + } while (0) + +/* hal_system_start */ +#define STM32_HAL_FLASH_REMAP() + +/* hal_spi */ +#include +#include +#include +#include +#include +#include + +struct stm32_hal_spi_cfg { + int ss_pin; /* for slave mode */ + int sck_pin; + int miso_pin; + int mosi_pin; + int irq_prio; +}; + +/* hal_i2c */ +#include +#include + +/* hal_uart */ +#include +#include + +/* hal_timer */ +#include +#include +#include + +#define STM32_HAL_TIMER_MAX (3) + +#define STM32_HAL_TIMER_TIM1_IRQ TIM1_CC_IRQn +#define STM32_HAL_TIMER_TIM2_IRQ TIM2_IRQn +#define STM32_HAL_TIMER_TIM6_IRQ TIM6_IRQn +#define STM32_HAL_TIMER_TIM8_IRQ TIM8_CC_IRQn +#define STM32_HAL_TIMER_TIM12_IRQ TIM12_IRQn +#define STM32_HAL_TIMER_TIM13_IRQ TIM13_IRQn +#define STM32_HAL_TIMER_TIM14_IRQ TIM14_IRQn +#define STM32_HAL_TIMER_TIM15_IRQ TIM15_IRQn +#define STM32_HAL_TIMER_TIM16_IRQ TIM16_IRQn +#define STM32_HAL_TIMER_TIM17_IRQ TIM17_IRQn + +/* hw/drivers/trng */ +#include + +/* hw/drivers/crypto */ +#include +#include + +/* hal_flash */ +#include +#include +#include +#include +#define STM32_HAL_FLASH_INIT() \ + do { \ + HAL_FLASH_Unlock(); \ + } while (0) +#define FLASH_PROGRAM_TYPE FLASH_TYPEPROGRAM_QUADWORD +/* Some STM32H5 devices don't have those filed */ +#ifndef FLASH_CCR_CLR_OBKERR +#define FLASH_CCR_CLR_OBKERR 0 +#endif +#ifndef FLASH_CCR_CLR_OBKWERR +#define FLASH_CCR_CLR_OBKWERR 0 +#endif +#define STM32_HAL_FLASH_CLEAR_ERRORS() \ + do { \ + __HAL_FLASH_CLEAR_FLAG(FLASH_CCR_CLR_EOP | \ + FLASH_CCR_CLR_WRPERR | \ + FLASH_CCR_CLR_PGSERR | \ + FLASH_CCR_CLR_STRBERR | \ + FLASH_CCR_CLR_INCERR | \ + FLASH_CCR_CLR_OBKERR | \ + FLASH_CCR_CLR_OBKWERR | \ + FLASH_CCR_CLR_OPTCHANGEERR); \ + } while (0) + +#ifdef __cplusplus +} +#endif + +#endif /* STM32_HAL_H */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32_pin_cfg.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_pin_cfg.h new file mode 100644 index 0000000000..f55237499a --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32_pin_cfg.h @@ -0,0 +1,3280 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef _STM32_PIN_CFG_H +#define _STM32_PIN_CFG_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef uint16_t hal_gpio_pin_t; +typedef const struct stm32_pin_cfg *stm32_pin_cfg_t; + +struct stm32_pin_cfg { + hal_gpio_pin_t pin; + GPIO_InitTypeDef hal_init; +}; + +void stm32_pin_config(stm32_pin_cfg_t cfg); +void stm32_pin_pulse(hal_gpio_pin_t pin); +void stm32_pin_pulse_n(hal_gpio_pin_t pin, int pulse_count); + +#define NULL_PIN NULL + +/* Port definitions */ +#ifdef GPIOA +#define PA0 MCU_GPIO_PORTA(0) +#define PA1 MCU_GPIO_PORTA(1) +#define PA2 MCU_GPIO_PORTA(2) +#define PA3 MCU_GPIO_PORTA(3) +#define PA4 MCU_GPIO_PORTA(4) +#define PA5 MCU_GPIO_PORTA(5) +#define PA6 MCU_GPIO_PORTA(6) +#define PA7 MCU_GPIO_PORTA(7) +#define PA8 MCU_GPIO_PORTA(8) +#define PA9 MCU_GPIO_PORTA(9) +#define PA10 MCU_GPIO_PORTA(10) +#define PA11 MCU_GPIO_PORTA(11) +#define PA12 MCU_GPIO_PORTA(12) +#define PA13 MCU_GPIO_PORTA(13) +#define PA14 MCU_GPIO_PORTA(14) +#define PA15 MCU_GPIO_PORTA(15) +#endif + +#ifdef GPIOB +#define PB0 MCU_GPIO_PORTB(0) +#define PB1 MCU_GPIO_PORTB(1) +#define PB2 MCU_GPIO_PORTB(2) +#define PB3 MCU_GPIO_PORTB(3) +#define PB4 MCU_GPIO_PORTB(4) +#define PB5 MCU_GPIO_PORTB(5) +#define PB6 MCU_GPIO_PORTB(6) +#define PB7 MCU_GPIO_PORTB(7) +#define PB8 MCU_GPIO_PORTB(8) +#define PB9 MCU_GPIO_PORTB(9) +#define PB10 MCU_GPIO_PORTB(10) +#define PB11 MCU_GPIO_PORTB(11) +#define PB12 MCU_GPIO_PORTB(12) +#define PB13 MCU_GPIO_PORTB(13) +#define PB14 MCU_GPIO_PORTB(14) +#define PB15 MCU_GPIO_PORTB(15) +#endif + +#ifdef GPIOC +#define PC0 MCU_GPIO_PORTC(0) +#define PC1 MCU_GPIO_PORTC(1) +#define PC2 MCU_GPIO_PORTC(2) +#define PC3 MCU_GPIO_PORTC(3) +#define PC4 MCU_GPIO_PORTC(4) +#define PC5 MCU_GPIO_PORTC(5) +#define PC6 MCU_GPIO_PORTC(6) +#define PC7 MCU_GPIO_PORTC(7) +#define PC8 MCU_GPIO_PORTC(8) +#define PC9 MCU_GPIO_PORTC(9) +#define PC10 MCU_GPIO_PORTC(10) +#define PC11 MCU_GPIO_PORTC(11) +#define PC12 MCU_GPIO_PORTC(12) +#define PC13 MCU_GPIO_PORTC(13) +#define PC14 MCU_GPIO_PORTC(14) +#define PC15 MCU_GPIO_PORTC(15) +#endif + +#ifdef GPIOD +#define PD0 MCU_GPIO_PORTD(0) +#define PD1 MCU_GPIO_PORTD(1) +#define PD2 MCU_GPIO_PORTD(2) +#define PD3 MCU_GPIO_PORTD(3) +#define PD4 MCU_GPIO_PORTD(4) +#define PD5 MCU_GPIO_PORTD(5) +#define PD6 MCU_GPIO_PORTD(6) +#define PD7 MCU_GPIO_PORTD(7) +#define PD8 MCU_GPIO_PORTD(8) +#define PD9 MCU_GPIO_PORTD(9) +#define PD10 MCU_GPIO_PORTD(10) +#define PD11 MCU_GPIO_PORTD(11) +#define PD12 MCU_GPIO_PORTD(12) +#define PD13 MCU_GPIO_PORTD(13) +#define PD14 MCU_GPIO_PORTD(14) +#define PD15 MCU_GPIO_PORTD(15) +#endif + +#ifdef GPIOE +#define PE0 MCU_GPIO_PORTE(0) +#define PE1 MCU_GPIO_PORTE(1) +#define PE2 MCU_GPIO_PORTE(2) +#define PE3 MCU_GPIO_PORTE(3) +#define PE4 MCU_GPIO_PORTE(4) +#define PE5 MCU_GPIO_PORTE(5) +#define PE6 MCU_GPIO_PORTE(6) +#define PE7 MCU_GPIO_PORTE(7) +#define PE8 MCU_GPIO_PORTE(8) +#define PE9 MCU_GPIO_PORTE(9) +#define PE10 MCU_GPIO_PORTE(10) +#define PE11 MCU_GPIO_PORTE(11) +#define PE12 MCU_GPIO_PORTE(12) +#define PE13 MCU_GPIO_PORTE(13) +#define PE14 MCU_GPIO_PORTE(14) +#define PE15 MCU_GPIO_PORTE(15) +#endif + +#ifdef GPIOF +#define PF0 MCU_GPIO_PORTF(0) +#define PF1 MCU_GPIO_PORTF(1) +#define PF2 MCU_GPIO_PORTF(2) +#define PF3 MCU_GPIO_PORTF(3) +#define PF4 MCU_GPIO_PORTF(4) +#define PF5 MCU_GPIO_PORTF(5) +#define PF6 MCU_GPIO_PORTF(6) +#define PF7 MCU_GPIO_PORTF(7) +#define PF8 MCU_GPIO_PORTF(8) +#define PF9 MCU_GPIO_PORTF(9) +#define PF10 MCU_GPIO_PORTF(10) +#define PF11 MCU_GPIO_PORTF(11) +#define PF12 MCU_GPIO_PORTF(12) +#define PF13 MCU_GPIO_PORTF(13) +#define PF14 MCU_GPIO_PORTF(14) +#define PF15 MCU_GPIO_PORTF(15) +#endif + +#ifdef GPIOG +#define PG0 MCU_GPIO_PORTG(0) +#define PG1 MCU_GPIO_PORTG(1) +#define PG2 MCU_GPIO_PORTG(2) +#define PG3 MCU_GPIO_PORTG(3) +#define PG4 MCU_GPIO_PORTG(4) +#define PG5 MCU_GPIO_PORTG(5) +#define PG6 MCU_GPIO_PORTG(6) +#define PG7 MCU_GPIO_PORTG(7) +#define PG8 MCU_GPIO_PORTG(8) +#define PG9 MCU_GPIO_PORTG(9) +#define PG10 MCU_GPIO_PORTG(10) +#define PG11 MCU_GPIO_PORTG(11) +#define PG12 MCU_GPIO_PORTG(12) +#define PG13 MCU_GPIO_PORTG(13) +#define PG14 MCU_GPIO_PORTG(14) +#define PG15 MCU_GPIO_PORTG(15) +#endif + +#ifdef GPIOH +#define PH0 MCU_GPIO_PORTH(0) +#define PH1 MCU_GPIO_PORTH(1) +#define PH2 MCU_GPIO_PORTH(2) +#define PH3 MCU_GPIO_PORTH(3) +#define PH4 MCU_GPIO_PORTH(4) +#define PH5 MCU_GPIO_PORTH(5) +#define PH6 MCU_GPIO_PORTH(6) +#define PH7 MCU_GPIO_PORTH(7) +#define PH8 MCU_GPIO_PORTH(8) +#define PH9 MCU_GPIO_PORTH(9) +#define PH10 MCU_GPIO_PORTH(10) +#define PH11 MCU_GPIO_PORTH(11) +#define PH12 MCU_GPIO_PORTH(12) +#define PH13 MCU_GPIO_PORTH(13) +#define PH14 MCU_GPIO_PORTH(14) +#define PH15 MCU_GPIO_PORTH(15) +#endif + +#ifdef GPIOI +#define PI0 MCU_GPIO_PORTI(0) +#define PI1 MCU_GPIO_PORTI(1) +#define PI2 MCU_GPIO_PORTI(2) +#define PI3 MCU_GPIO_PORTI(3) +#define PI4 MCU_GPIO_PORTI(4) +#define PI5 MCU_GPIO_PORTI(5) +#define PI6 MCU_GPIO_PORTI(6) +#define PI7 MCU_GPIO_PORTI(7) +#define PI8 MCU_GPIO_PORTI(8) +#define PI9 MCU_GPIO_PORTI(9) +#define PI10 MCU_GPIO_PORTI(10) +#define PI11 MCU_GPIO_PORTI(11) +#define PI12 MCU_GPIO_PORTI(12) +#define PI13 MCU_GPIO_PORTI(13) +#define PI14 MCU_GPIO_PORTI(14) +#define PI15 MCU_GPIO_PORTI(15) +#endif + +#ifndef STM32_PIN_FUN_CFG + +#define STM32_PIN_FUN_CFG(port_n, pin_n, pf, af) \ +extern const struct stm32_pin_cfg _P##port_n##pin_n##_##pf;\ +static stm32_pin_cfg_t const P##port_n##pin_n##_##pf __unused = &_P##port_n##pin_n##_##pf; + +#define STM32_PIN_FUN_CFG_OD(port_n, pin_n, pf, af) \ +extern const struct stm32_pin_cfg _P##port_n##pin_n##_##pf##_OD;\ +static stm32_pin_cfg_t const P##port_n##pin_n##_##pf##_OD __unused = &_P##port_n##pin_n##_##pf##_OD; + +#define STM32_PIN_FUN_CFG_OD_PU(port_n, pin_n, pf, af) \ +extern const struct stm32_pin_cfg _P##port_n##pin_n##_##pf##_OD_PU;\ +static stm32_pin_cfg_t const P##port_n##pin_n##_##pf##_OD_PU __unused = &_P##port_n##pin_n##_##pf##_OD_PU; + +#endif + +#ifdef GPIOA +#ifdef ETH +STM32_PIN_FUN_CFG(A, 0, ETH_CRS, GPIO_AF11_ETH) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(A, 0, SAI2_SD_B, GPIO_AF10_SAI2) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(A, 0, SDMMC2_CMD, GPIO_AF9_SDMMC2) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(A, 0, SPI3_RDY, GPIO_AF6_SPI3) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(A, 0, SPI6_NSS, GPIO_AF5_SPI6) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(A, 0, TIM15_BKIN, GPIO_AF4_TIM15) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 0, TIM2_CH1, GPIO_AF1_TIM2) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 0, TIM2_ETR, GPIO_AF14_TIM2) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(A, 0, TIM5_CH1, GPIO_AF2_TIM5) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(A, 0, TIM8_ETR, GPIO_AF3_TIM8) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(A, 0, UART4_TX, GPIO_AF8_UART4) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(A, 0, USART2_CTS, GPIO_AF7_USART2) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(A, 0, USART2_NSS, GPIO_AF7_USART2) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(A, 1, ETH_REF_CLK, GPIO_AF11_ETH) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(A, 1, ETH_RX_CLK, GPIO_AF11_ETH) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(A, 1, LPTIM1_IN1, GPIO_AF5_LPTIM1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(A, 1, OCTOSPI1_DQS, GPIO_AF6_OCTOSPI1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(A, 1, OCTOSPI1_IO3, GPIO_AF9_OCTOSPI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(A, 1, SAI2_MCLK_B, GPIO_AF10_SAI2) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(A, 1, TIM15_CH1N, GPIO_AF4_TIM15) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 1, TIM2_CH2, GPIO_AF1_TIM2) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(A, 1, TIM5_CH2, GPIO_AF2_TIM5) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(A, 1, UART4_RX, GPIO_AF8_UART4) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(A, 1, USART2_DE, GPIO_AF7_USART2) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(A, 1, USART2_RTS, GPIO_AF7_USART2) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(A, 10, DCMI_D1, GPIO_AF13_DCMI) +#endif +#ifdef FDCAN2 +STM32_PIN_FUN_CFG(A, 10, FDCAN2_TX, GPIO_AF9_FDCAN2) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(A, 10, LPTIM2_IN2, GPIO_AF4_LPTIM2) +#endif +#ifdef LPUART1 +STM32_PIN_FUN_CFG(A, 10, LPUART1_RX, GPIO_AF3_LPUART1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(A, 10, PSSI_D1, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(A, 10, SDMMC1_D0, GPIO_AF12_SDMMC1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(A, 10, TIM1_CH3, GPIO_AF1_TIM1) +#endif +#ifdef UCPD1 +STM32_PIN_FUN_CFG(A, 10, UCPD1_FRSTX, GPIO_AF6_UCPD1) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(A, 10, USART1_RX, GPIO_AF7_USART1) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(A, 11, FDCAN1_RX, GPIO_AF9_FDCAN1) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(A, 11, I2S2_WS, GPIO_AF5_SPI2) +#endif +#ifdef LPUART1 +STM32_PIN_FUN_CFG(A, 11, LPUART1_CTS, GPIO_AF3_LPUART1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(A, 11, SPI2_NSS, GPIO_AF5_SPI2) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(A, 11, TIM1_CH4, GPIO_AF1_TIM1) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(A, 11, UART4_RX, GPIO_AF6_UART4) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(A, 11, USART1_CTS, GPIO_AF7_USART1) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(A, 11, USART1_NSS, GPIO_AF7_USART1) +#endif +#ifdef USB +STM32_PIN_FUN_CFG(A, 11, USB_DM, GPIO_AF10_USB) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(A, 12, FDCAN1_TX, GPIO_AF9_FDCAN1) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(A, 12, I2S2_CK, GPIO_AF5_SPI2) +#endif +#ifdef LPUART1 +STM32_PIN_FUN_CFG(A, 12, LPUART1_DE, GPIO_AF3_LPUART1) +#endif +#ifdef LPUART1 +STM32_PIN_FUN_CFG(A, 12, LPUART1_RTS, GPIO_AF3_LPUART1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(A, 12, SAI2_FS_B, GPIO_AF8_SAI2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(A, 12, SPI2_SCK, GPIO_AF5_SPI2) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(A, 12, TIM1_ETR, GPIO_AF1_TIM1) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(A, 12, UART4_TX, GPIO_AF6_UART4) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(A, 12, USART1_DE, GPIO_AF7_USART1) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(A, 12, USART1_RTS, GPIO_AF7_USART1) +#endif +#ifdef USB +STM32_PIN_FUN_CFG(A, 12, USB_DP, GPIO_AF10_USB) +#endif +#ifdef CEC +STM32_PIN_FUN_CFG(A, 15, CEC, GPIO_AF4_CEC) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(A, 15, DCMI_D11, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(A, 15, FMC_NBL1, GPIO_AF12_FMC) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(A, 15, I2S1_WS, GPIO_AF5_SPI1) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(A, 15, I2S3_WS, GPIO_AF6_SPI3) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(A, 15, LPTIM3_IN2, GPIO_AF2_LPTIM3) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(A, 15, PSSI_D11, GPIO_AF13_PSSI) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(A, 15, SPI1_NSS, GPIO_AF5_SPI1) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(A, 15, SPI3_NSS, GPIO_AF6_SPI3) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(A, 15, SPI6_NSS, GPIO_AF7_SPI6) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 15, TIM2_CH1, GPIO_AF1_TIM2) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 15, TIM2_ETR, GPIO_AF14_TIM2) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(A, 15, UART4_DE, GPIO_AF8_UART4) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(A, 15, UART4_RTS, GPIO_AF8_UART4) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(A, 15, UART7_TX, GPIO_AF11_UART7) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(A, 2, ETH_MDIO, GPIO_AF11_ETH) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(A, 2, LPTIM1_IN2, GPIO_AF5_LPTIM1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(A, 2, SAI2_SCK_B, GPIO_AF8_SAI2) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(A, 2, TIM15_CH1, GPIO_AF4_TIM15) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 2, TIM2_CH3, GPIO_AF1_TIM2) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(A, 2, TIM5_CH3, GPIO_AF2_TIM5) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(A, 2, USART2_TX, GPIO_AF7_USART2) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(A, 3, ETH_COL, GPIO_AF11_ETH) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(A, 3, I2S2_WS, GPIO_AF5_SPI2) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(A, 3, OCTOSPI1_CLK, GPIO_AF3_OCTOSPI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(A, 3, SAI1_SD_B, GPIO_AF6_SAI1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(A, 3, SPI2_NSS, GPIO_AF5_SPI2) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(A, 3, TIM15_CH2, GPIO_AF4_TIM15) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 3, TIM2_CH4, GPIO_AF1_TIM2) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(A, 3, TIM5_CH4, GPIO_AF2_TIM5) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(A, 3, USART2_RX, GPIO_AF7_USART2) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(A, 4, DCMI_HSYNC, GPIO_AF13_DCMI) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(A, 4, I2S1_WS, GPIO_AF5_SPI1) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(A, 4, I2S3_WS, GPIO_AF6_SPI3) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(A, 4, LPTIM2_CH1, GPIO_AF3_LPTIM2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(A, 4, PSSI_DE, GPIO_AF13_PSSI) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(A, 4, SPI1_NSS, GPIO_AF5_SPI1) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(A, 4, SPI3_NSS, GPIO_AF6_SPI3) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(A, 4, SPI6_NSS, GPIO_AF8_SPI6) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(A, 4, TIM5_ETR, GPIO_AF2_TIM5) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(A, 4, USART2_CK, GPIO_AF7_USART2) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(A, 5, ETH_TX_EN, GPIO_AF11_ETH) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(A, 5, I2S1_CK, GPIO_AF5_SPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(A, 5, PSSI_D14, GPIO_AF13_PSSI) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(A, 5, SPI1_SCK, GPIO_AF5_SPI1) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(A, 5, SPI6_SCK, GPIO_AF8_SPI6) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 5, TIM2_CH1, GPIO_AF1_TIM2) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(A, 5, TIM2_ETR, GPIO_AF14_TIM2) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(A, 5, TIM8_CH1N, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(A, 6, DCMI_PIXCLK, GPIO_AF13_DCMI) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(A, 6, I2S1_SDI, GPIO_AF5_SPI1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(A, 6, OCTOSPI1_IO3, GPIO_AF6_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(A, 6, PSSI_PDCK, GPIO_AF13_PSSI) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(A, 6, SPI1_MISO, GPIO_AF5_SPI1) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(A, 6, SPI6_MISO, GPIO_AF8_SPI6) +#endif +#ifdef TIM13 +STM32_PIN_FUN_CFG(A, 6, TIM13_CH1, GPIO_AF9_TIM13) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(A, 6, TIM1_BKIN, GPIO_AF1_TIM1) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(A, 6, TIM3_CH1, GPIO_AF2_TIM3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(A, 6, TIM8_BKIN, GPIO_AF3_TIM8) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(A, 6, USART11_TX, GPIO_AF7_USART11) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(A, 7, ETH_CRS_DV, GPIO_AF11_ETH) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(A, 7, ETH_RX_DV, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(A, 7, FMC_NWE, GPIO_AF13_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(A, 7, FMC_SDNWE, GPIO_AF12_FMC) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(A, 7, I2S1_SDO, GPIO_AF5_SPI1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(A, 7, OCTOSPI1_IO2, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(A, 7, SPI1_MOSI, GPIO_AF5_SPI1) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(A, 7, SPI6_MOSI, GPIO_AF8_SPI6) +#endif +#ifdef TIM14 +STM32_PIN_FUN_CFG(A, 7, TIM14_CH1, GPIO_AF9_TIM14) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(A, 7, TIM1_CH1N, GPIO_AF1_TIM1) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(A, 7, TIM3_CH2, GPIO_AF2_TIM3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(A, 7, TIM8_CH1N, GPIO_AF3_TIM8) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(A, 7, USART11_RX, GPIO_AF7_USART11) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(A, 8, DCMI_D3, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(A, 8, FMC_NOE, GPIO_AF12_FMC) +#endif +#ifdef I2C3 +STM32_PIN_FUN_CFG(A, 8, I2C3_SCL, GPIO_AF4_I2C3) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(A, 8, PSSI_D3, GPIO_AF13_PSSI) +#endif +#ifdef RCC +STM32_PIN_FUN_CFG(A, 8, RCC_MCO_1, GPIO_AF0_MCO) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(A, 8, SPI1_RDY, GPIO_AF5_SPI1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(A, 8, TIM1_CH1, GPIO_AF1_TIM1) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(A, 8, TIM8_BKIN2, GPIO_AF3_TIM8) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(A, 8, UART7_RX, GPIO_AF11_UART7) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(A, 8, USART1_CK, GPIO_AF7_USART1) +#endif +#ifdef USB +STM32_PIN_FUN_CFG(A, 8, USB_SOF, GPIO_AF10_USB) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(A, 9, DCMI_D0, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(A, 9, ETH_TX_ER, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(A, 9, FMC_NWE, GPIO_AF12_FMC) +#endif +#ifdef I2C3 +STM32_PIN_FUN_CFG(A, 9, I2C3_SMBA, GPIO_AF4_I2C3) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(A, 9, I2S2_CK, GPIO_AF5_SPI2) +#endif +#ifdef LPUART1 +STM32_PIN_FUN_CFG(A, 9, LPUART1_TX, GPIO_AF3_LPUART1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(A, 9, PSSI_D0, GPIO_AF13_PSSI) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(A, 9, SPI2_SCK, GPIO_AF5_SPI2) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(A, 9, TIM1_CH2, GPIO_AF1_TIM1) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(A, 9, USART1_TX, GPIO_AF7_USART1) +#endif +#endif /* GPIOA */ + +/* Port B definitions */ +#ifdef GPIOB +#ifdef ETH +STM32_PIN_FUN_CFG(B, 0, ETH_RXD2, GPIO_AF11_ETH) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(B, 0, LPTIM3_CH1, GPIO_AF14_LPTIM3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 0, OCTOSPI1_IO1, GPIO_AF6_OCTOSPI1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(B, 0, TIM1_CH2N, GPIO_AF1_TIM1) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(B, 0, TIM3_CH3, GPIO_AF2_TIM3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(B, 0, TIM8_CH2N, GPIO_AF3_TIM8) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(B, 0, UART4_CTS, GPIO_AF8_UART4) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(B, 0, USART11_CK, GPIO_AF7_USART11) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(B, 1, ETH_RXD3, GPIO_AF11_ETH) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(B, 1, LPTIM3_CH2, GPIO_AF14_LPTIM3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 1, OCTOSPI1_IO0, GPIO_AF6_OCTOSPI1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(B, 1, TIM1_CH3N, GPIO_AF1_TIM1) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(B, 1, TIM3_CH4, GPIO_AF2_TIM3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(B, 1, TIM8_CH3N, GPIO_AF3_TIM8) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(B, 10, ETH_RX_ER, GPIO_AF11_ETH) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(B, 10, I2C2_SCL, GPIO_AF4_I2C2) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(B, 10, I2S2_CK, GPIO_AF5_SPI2) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(B, 10, LPTIM2_IN1, GPIO_AF3_LPTIM2) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(B, 10, LPTIM3_CH1, GPIO_AF2_LPTIM3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 10, OCTOSPI1_NCS, GPIO_AF9_OCTOSPI1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(B, 10, SPI2_SCK, GPIO_AF5_SPI2) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(B, 10, TIM2_CH3, GPIO_AF1_TIM2) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(B, 10, USART3_TX, GPIO_AF7_USART3) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(B, 11, ETH_TX_EN, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(B, 11, FMC_NBL1, GPIO_AF12_FMC) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(B, 11, I2C2_SDA, GPIO_AF4_I2C2) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(B, 11, LPTIM2_ETR, GPIO_AF3_LPTIM2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(B, 11, SPI2_RDY, GPIO_AF5_SPI2) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(B, 11, SPI4_RDY, GPIO_AF6_SPI4) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(B, 11, TIM2_CH4, GPIO_AF1_TIM2) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(B, 11, USART3_RX, GPIO_AF7_USART3) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(B, 12, ETH_TXD0, GPIO_AF11_ETH) +#endif +#ifdef FDCAN2 +STM32_PIN_FUN_CFG(B, 12, FDCAN2_RX, GPIO_AF9_FDCAN2) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(B, 12, I2C2_SDA, GPIO_AF4_I2C2) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(B, 12, I2S2_WS, GPIO_AF5_SPI2) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 12, OCTOSPI1_NCLK, GPIO_AF3_OCTOSPI1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(B, 12, SPI2_NSS, GPIO_AF5_SPI2) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(B, 12, TIM1_BKIN, GPIO_AF1_TIM1) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(B, 12, UART5_RX, GPIO_AF14_UART5) +#endif +#ifdef UCPD1 +STM32_PIN_FUN_CFG(B, 12, UCPD1_FRSTX, GPIO_AF6_UCPD1) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(B, 12, USART3_CK, GPIO_AF7_USART3) +#endif +#ifdef FDCAN2 +STM32_PIN_FUN_CFG(B, 13, FDCAN2_TX, GPIO_AF9_FDCAN2) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(B, 13, I2C2_SMBA, GPIO_AF4_I2C2) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(B, 13, I2S2_CK, GPIO_AF5_SPI2) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(B, 13, LPTIM2_CH1, GPIO_AF3_LPTIM2) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(B, 13, LPTIM3_IN1, GPIO_AF2_LPTIM3) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(B, 13, SDMMC1_D0, GPIO_AF12_SDMMC1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(B, 13, SPI2_SCK, GPIO_AF5_SPI2) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(B, 13, TIM1_CH1N, GPIO_AF1_TIM1) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(B, 13, UART5_TX, GPIO_AF14_UART5) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(B, 13, USART3_CTS, GPIO_AF7_USART3) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(B, 13, USART3_NSS, GPIO_AF7_USART3) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(B, 14, I2S2_SDI, GPIO_AF5_SPI2) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(B, 14, LPTIM3_ETR, GPIO_AF14_LPTIM3) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 14, SDMMC2_D0, GPIO_AF9_SDMMC2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(B, 14, SPI2_MISO, GPIO_AF5_SPI2) +#endif +#ifdef TIM12 +STM32_PIN_FUN_CFG(B, 14, TIM12_CH1, GPIO_AF2_TIM12) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(B, 14, TIM1_CH2N, GPIO_AF1_TIM1) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(B, 14, TIM8_CH2N, GPIO_AF3_TIM8) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(B, 14, UART4_DE, GPIO_AF8_UART4) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(B, 14, UART4_RTS, GPIO_AF8_UART4) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(B, 14, USART1_TX, GPIO_AF4_USART1) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(B, 14, USART3_DE, GPIO_AF7_USART3) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(B, 14, USART3_RTS, GPIO_AF7_USART3) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(B, 15, DCMI_D2, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(B, 15, ETH_TXD1, GPIO_AF11_ETH) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(B, 15, I2S2_SDO, GPIO_AF5_SPI2) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 15, OCTOSPI1_CLK, GPIO_AF10_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(B, 15, PSSI_D2, GPIO_AF13_PSSI) +#endif +#ifdef RTC +STM32_PIN_FUN_CFG(B, 15, RTC_REFIN, GPIO_AF0_RTC_50Hz) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 15, SDMMC2_D1, GPIO_AF9_SDMMC2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(B, 15, SPI2_MOSI, GPIO_AF5_SPI2) +#endif +#ifdef TIM12 +STM32_PIN_FUN_CFG(B, 15, TIM12_CH2, GPIO_AF2_TIM12) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(B, 15, TIM1_CH3N, GPIO_AF1_TIM1) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(B, 15, TIM8_CH3N, GPIO_AF3_TIM8) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(B, 15, UART4_CTS, GPIO_AF8_UART4) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(B, 15, UART5_RX, GPIO_AF14_UART5) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(B, 15, USART11_CTS, GPIO_AF7_USART11) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(B, 15, USART11_NSS, GPIO_AF7_USART11) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(B, 15, USART1_RX, GPIO_AF4_USART1) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(B, 2, I2S3_SDO, GPIO_AF7_SPI3) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(B, 2, LPTIM1_CH1, GPIO_AF5_LPTIM1) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(B, 2, LPTIM5_ETR, GPIO_AF13_LPTIM5) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 2, OCTOSPI1_CLK, GPIO_AF9_OCTOSPI1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 2, OCTOSPI1_DQS, GPIO_AF10_OCTOSPI1) +#endif +#ifdef RTC +STM32_PIN_FUN_CFG(B, 2, RTC_OUT2, GPIO_AF0_RTC_50Hz) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(B, 2, SAI1_D1, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(B, 2, SAI1_SD_A, GPIO_AF6_SAI1) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(B, 2, SDMMC1_CMD, GPIO_AF12_SDMMC1) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(B, 2, SPI1_RDY, GPIO_AF4_SPI1) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(B, 2, SPI3_MOSI, GPIO_AF7_SPI3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(B, 2, TIM8_CH4N, GPIO_AF3_TIM8) +#endif +#ifdef CRS +STM32_PIN_FUN_CFG(B, 3, CRS_SYNC, GPIO_AF10_CRS) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(B, 3, I2C2_SDA, GPIO_AF4_I2C2) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(B, 3, I2S1_CK, GPIO_AF5_SPI1) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(B, 3, I2S3_CK, GPIO_AF6_SPI3) +#endif +#ifdef LPTIM6 +STM32_PIN_FUN_CFG(B, 3, LPTIM6_ETR, GPIO_AF14_LPTIM6) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 3, SDMMC2_D2, GPIO_AF9_SDMMC2) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(B, 3, SPI1_SCK, GPIO_AF5_SPI1) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(B, 3, SPI3_SCK, GPIO_AF6_SPI3) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(B, 3, SPI6_SCK, GPIO_AF8_SPI6) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(B, 3, TIM2_CH2, GPIO_AF1_TIM2) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(B, 3, UART12_CTS, GPIO_AF7_UART12) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(B, 3, UART7_RX, GPIO_AF11_UART7) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(B, 4, DCMI_D7, GPIO_AF13_DCMI) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(B, 4, I2S1_SDI, GPIO_AF5_SPI1) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(B, 4, I2S2_WS, GPIO_AF7_SPI2) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(B, 4, I2S3_SDI, GPIO_AF6_SPI3) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(B, 4, LPTIM1_CH2, GPIO_AF4_LPTIM1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 4, OCTOSPI1_CLK, GPIO_AF3_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(B, 4, PSSI_D7, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 4, SDMMC2_D3, GPIO_AF9_SDMMC2) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(B, 4, SPI1_MISO, GPIO_AF5_SPI1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(B, 4, SPI2_NSS, GPIO_AF7_SPI2) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(B, 4, SPI3_MISO, GPIO_AF6_SPI3) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(B, 4, SPI6_MISO, GPIO_AF8_SPI6) +#endif +#ifdef TIM16 +STM32_PIN_FUN_CFG(B, 4, TIM16_BKIN, GPIO_AF1_TIM16) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(B, 4, TIM3_CH1, GPIO_AF2_TIM3) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(B, 4, UART7_TX, GPIO_AF11_UART7) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(B, 5, DCMI_D10, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(B, 5, ETH_PPS_OUT, GPIO_AF11_ETH) +#endif +#ifdef FDCAN2 +STM32_PIN_FUN_CFG(B, 5, FDCAN2_RX, GPIO_AF9_FDCAN2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(B, 5, FMC_SDCKE1, GPIO_AF12_FMC) +#endif +#ifdef I2C1 +STM32_PIN_FUN_CFG(B, 5, I2C1_SMBA, GPIO_AF4_I2C1) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(B, 5, I2C4_SMBA, GPIO_AF6_I2C4) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(B, 5, I2S1_SDO, GPIO_AF5_SPI1) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(B, 5, I2S3_SDO, GPIO_AF7_SPI3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 5, OCTOSPI1_NCLK, GPIO_AF3_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(B, 5, PSSI_D10, GPIO_AF13_PSSI) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(B, 5, SPI1_MOSI, GPIO_AF5_SPI1) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(B, 5, SPI3_MOSI, GPIO_AF7_SPI3) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(B, 5, SPI6_MOSI, GPIO_AF8_SPI6) +#endif +#ifdef TIM17 +STM32_PIN_FUN_CFG(B, 5, TIM17_BKIN, GPIO_AF1_TIM17) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(B, 5, TIM3_CH2, GPIO_AF2_TIM3) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(B, 5, UART5_RX, GPIO_AF14_UART5) +#endif +#ifdef CEC +STM32_PIN_FUN_CFG(B, 6, CEC, GPIO_AF5_CEC) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(B, 6, DCMI_D5, GPIO_AF13_DCMI) +#endif +#ifdef FDCAN2 +STM32_PIN_FUN_CFG(B, 6, FDCAN2_TX, GPIO_AF9_FDCAN2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(B, 6, FMC_SDNE1, GPIO_AF12_FMC) +#endif +#ifdef I2C1 +STM32_PIN_FUN_CFG(B, 6, I2C1_SCL, GPIO_AF4_I2C1) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(B, 6, I2C4_SCL, GPIO_AF6_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(B, 6, I3C1_SCL, GPIO_AF3_I3C1) +#endif +#ifdef LPUART1 +STM32_PIN_FUN_CFG(B, 6, LPUART1_TX, GPIO_AF8_LPUART1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(B, 6, OCTOSPI1_NCS, GPIO_AF10_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(B, 6, PSSI_D5, GPIO_AF13_PSSI) +#endif +#ifdef TIM16 +STM32_PIN_FUN_CFG(B, 6, TIM16_CH1N, GPIO_AF1_TIM16) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(B, 6, TIM4_CH1, GPIO_AF2_TIM4) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(B, 6, UART5_TX, GPIO_AF14_UART5) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(B, 6, USART1_TX, GPIO_AF7_USART1) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(B, 7, DCMI_VSYNC, GPIO_AF13_DCMI) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(B, 7, FDCAN1_TX, GPIO_AF9_FDCAN1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(B, 7, FMC_NL, GPIO_AF12_FMC) +#endif +#ifdef I2C1 +STM32_PIN_FUN_CFG(B, 7, I2C1_SDA, GPIO_AF4_I2C1) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(B, 7, I2C4_SDA, GPIO_AF6_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(B, 7, I3C1_SDA, GPIO_AF3_I3C1) +#endif +#ifdef LPUART1 +STM32_PIN_FUN_CFG(B, 7, LPUART1_RX, GPIO_AF8_LPUART1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(B, 7, PSSI_RDY, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 7, SDMMC2_CKIN, GPIO_AF11_SDMMC2) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 7, SDMMC2_D5, GPIO_AF10_SDMMC2) +#endif +#ifdef TIM17 +STM32_PIN_FUN_CFG(B, 7, TIM17_CH1N, GPIO_AF1_TIM17) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(B, 7, TIM4_CH2, GPIO_AF2_TIM4) +#endif +#ifdef USART1 +STM32_PIN_FUN_CFG(B, 7, USART1_RX, GPIO_AF7_USART1) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(B, 8, DCMI_D6, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(B, 8, ETH_TXD3, GPIO_AF11_ETH) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(B, 8, FDCAN1_RX, GPIO_AF9_FDCAN1) +#endif +#ifdef I2C1 +STM32_PIN_FUN_CFG(B, 8, I2C1_SCL, GPIO_AF4_I2C1) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(B, 8, I2C4_SCL, GPIO_AF6_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(B, 8, I3C1_SCL, GPIO_AF3_I3C1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(B, 8, PSSI_D6, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(B, 8, SDMMC1_CKIN, GPIO_AF7_SDMMC1) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(B, 8, SDMMC1_D4, GPIO_AF12_SDMMC1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 8, SDMMC2_D4, GPIO_AF10_SDMMC2) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(B, 8, SPI4_RDY, GPIO_AF5_SPI4) +#endif +#ifdef TIM16 +STM32_PIN_FUN_CFG(B, 8, TIM16_CH1, GPIO_AF1_TIM16) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(B, 8, TIM4_CH3, GPIO_AF2_TIM4) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(B, 8, UART4_RX, GPIO_AF8_UART4) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(B, 9, DCMI_D7, GPIO_AF13_DCMI) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(B, 9, FDCAN1_TX, GPIO_AF9_FDCAN1) +#endif +#ifdef I2C1 +STM32_PIN_FUN_CFG(B, 9, I2C1_SDA, GPIO_AF4_I2C1) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(B, 9, I2C4_SDA, GPIO_AF6_I2C4) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(B, 9, I2S2_WS, GPIO_AF5_SPI2) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(B, 9, I3C1_SDA, GPIO_AF3_I3C1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(B, 9, PSSI_D7, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(B, 9, SDMMC1_CDIR, GPIO_AF7_SDMMC1) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(B, 9, SDMMC1_D5, GPIO_AF12_SDMMC1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 9, SDMMC2_CKIN, GPIO_AF11_SDMMC2) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(B, 9, SDMMC2_D5, GPIO_AF10_SDMMC2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(B, 9, SPI2_NSS, GPIO_AF5_SPI2) +#endif +#ifdef TIM17 +STM32_PIN_FUN_CFG(B, 9, TIM17_CH1, GPIO_AF1_TIM17) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(B, 9, TIM4_CH4, GPIO_AF2_TIM4) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(B, 9, UART4_TX, GPIO_AF8_UART4) +#endif +#endif /* GPIOB */ + +/* Port C definitions */ +#ifdef GPIOC +#ifdef FMC +STM32_PIN_FUN_CFG(C, 0, FMC_A25, GPIO_AF9_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 0, FMC_SDNWE, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 0, OCTOSPI1_IO7, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(C, 0, SAI1_MCLK_A, GPIO_AF6_SAI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(C, 0, SAI2_FS_B, GPIO_AF8_SAI2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(C, 0, SPI2_RDY, GPIO_AF7_SPI2) +#endif +#ifdef TIM16 +STM32_PIN_FUN_CFG(C, 0, TIM16_BKIN, GPIO_AF1_TIM16) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(C, 1, ETH_MDC, GPIO_AF11_ETH) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(C, 1, I2S2_SDO, GPIO_AF5_SPI2) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 1, OCTOSPI1_IO4, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(C, 1, SAI1_D1, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(C, 1, SAI1_SD_A, GPIO_AF6_SAI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(C, 1, SAI2_SD_A, GPIO_AF8_SAI2) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(C, 1, SDMMC2_CK, GPIO_AF9_SDMMC2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(C, 1, SPI2_MOSI, GPIO_AF5_SPI2) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(C, 1, USART11_DE, GPIO_AF7_USART11) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(C, 1, USART11_RTS, GPIO_AF7_USART11) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(C, 10, DCMI_D8, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(C, 10, ETH_TXD0, GPIO_AF11_ETH) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(C, 10, I2S3_CK, GPIO_AF6_SPI3) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(C, 10, LPTIM3_ETR, GPIO_AF2_LPTIM3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 10, OCTOSPI1_IO1, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(C, 10, PSSI_D8, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 10, SDMMC1_D2, GPIO_AF12_SDMMC1) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(C, 10, SPI3_SCK, GPIO_AF6_SPI3) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(C, 10, UART4_TX, GPIO_AF8_UART4) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(C, 10, USART3_TX, GPIO_AF7_USART3) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(C, 11, DCMI_D4, GPIO_AF13_DCMI) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(C, 11, I2S3_SDI, GPIO_AF6_SPI3) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(C, 11, LPTIM3_IN1, GPIO_AF2_LPTIM3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 11, OCTOSPI1_NCS, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(C, 11, PSSI_D4, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 11, SDMMC1_D3, GPIO_AF12_SDMMC1) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(C, 11, SPI3_MISO, GPIO_AF6_SPI3) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(C, 11, UART4_RX, GPIO_AF8_UART4) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(C, 11, USART3_RX, GPIO_AF7_USART3) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(C, 12, DCMI_D9, GPIO_AF13_DCMI) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(C, 12, I2S3_SDO, GPIO_AF6_SPI3) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(C, 12, PSSI_D9, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 12, SDMMC1_CK, GPIO_AF12_SDMMC1) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(C, 12, SPI3_MOSI, GPIO_AF6_SPI3) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(C, 12, SPI6_SCK, GPIO_AF5_SPI6) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(C, 12, TIM15_CH1, GPIO_AF2_TIM15) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(C, 12, UART5_TX, GPIO_AF8_UART5) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(C, 12, USART3_CK, GPIO_AF7_USART3) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(C, 2, ETH_TXD2, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 2, FMC_SDNE0, GPIO_AF12_FMC) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(C, 2, I2S2_SDI, GPIO_AF5_SPI2) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 2, OCTOSPI1_IO2, GPIO_AF9_OCTOSPI1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 2, OCTOSPI1_IO5, GPIO_AF6_OCTOSPI1) +#endif +#ifdef PWR +STM32_PIN_FUN_CFG(C, 2, PWR_CSLEEP, GPIO_AF0_CSLEEP) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(C, 2, SPI2_MISO, GPIO_AF5_SPI2) +#endif +#ifdef TIM17 +STM32_PIN_FUN_CFG(C, 2, TIM17_CH1, GPIO_AF1_TIM17) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(C, 2, TIM4_CH4, GPIO_AF2_TIM4) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(C, 3, ETH_TX_CLK, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 3, FMC_SDCKE0, GPIO_AF12_FMC) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(C, 3, I2S2_SDO, GPIO_AF5_SPI2) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(C, 3, LPTIM3_CH1, GPIO_AF3_LPTIM3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 3, OCTOSPI1_IO0, GPIO_AF9_OCTOSPI1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 3, OCTOSPI1_IO6, GPIO_AF6_OCTOSPI1) +#endif +#ifdef PWR +STM32_PIN_FUN_CFG(C, 3, PWR_CSTOP, GPIO_AF0_CSTOP) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(C, 3, SAI1_D3, GPIO_AF2_SAI1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(C, 3, SPI2_MOSI, GPIO_AF5_SPI2) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(C, 4, ETH_RXD0, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 4, FMC_SDNE0, GPIO_AF12_FMC) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(C, 4, I2S1_MCK, GPIO_AF5_SPI1) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(C, 4, LPTIM2_ETR, GPIO_AF3_LPTIM2) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(C, 4, SAI1_CK1, GPIO_AF2_SAI1) +#endif +#ifdef TIM2 +STM32_PIN_FUN_CFG(C, 4, TIM2_CH4, GPIO_AF1_TIM2) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(C, 4, USART3_RX, GPIO_AF7_USART3) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(C, 5, ETH_RXD1, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 5, FMC_SDCKE0, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 5, OCTOSPI1_DQS, GPIO_AF10_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(C, 5, PSSI_D15, GPIO_AF4_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(C, 5, SAI1_D3, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(C, 5, SAI1_FS_A, GPIO_AF6_SAI1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(C, 5, TIM1_CH4N, GPIO_AF1_TIM1) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(C, 5, UART12_DE, GPIO_AF7_UART12) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(C, 5, UART12_RTS, GPIO_AF7_UART12) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(C, 6, DCMI_D0, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 6, FMC_NWAIT, GPIO_AF9_FMC) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(C, 6, I2S2_MCK, GPIO_AF5_SPI2) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 6, OCTOSPI1_IO5, GPIO_AF11_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(C, 6, PSSI_D0, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(C, 6, SAI1_SCK_A, GPIO_AF6_SAI1) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 6, SDMMC1_D0DIR, GPIO_AF8_SDMMC1) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 6, SDMMC1_D6, GPIO_AF12_SDMMC1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(C, 6, SDMMC2_D6, GPIO_AF10_SDMMC2) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(C, 6, TIM3_CH1, GPIO_AF2_TIM3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(C, 6, TIM8_CH1, GPIO_AF3_TIM8) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(C, 6, USART6_TX, GPIO_AF7_USART6) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(C, 7, DCMI_D1, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 7, FMC_NE1, GPIO_AF9_FMC) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(C, 7, I2S3_MCK, GPIO_AF6_SPI3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 7, OCTOSPI1_IO6, GPIO_AF11_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(C, 7, PSSI_D1, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 7, SDMMC1_D123DIR, GPIO_AF8_SDMMC1) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 7, SDMMC1_D7, GPIO_AF12_SDMMC1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(C, 7, SDMMC2_D7, GPIO_AF10_SDMMC2) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(C, 7, TIM3_CH2, GPIO_AF2_TIM3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(C, 7, TIM8_CH2, GPIO_AF3_TIM8) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(C, 7, USART6_RX, GPIO_AF7_USART6) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(C, 8, DCMI_D2, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 8, FMC_ALE, GPIO_AF11_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 8, FMC_INT, GPIO_AF10_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 8, FMC_NCE, GPIO_AF9_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 8, FMC_NE2, GPIO_AF9_FMC) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(C, 8, PSSI_D2, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 8, SDMMC1_D0, GPIO_AF12_SDMMC1) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(C, 8, TIM3_CH3, GPIO_AF2_TIM3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(C, 8, TIM8_CH3, GPIO_AF3_TIM8) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(C, 8, UART5_DE, GPIO_AF8_UART5) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(C, 8, UART5_RTS, GPIO_AF8_UART5) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(C, 8, USART6_CK, GPIO_AF7_USART6) +#endif +#ifdef AUDIOCLK +STM32_PIN_FUN_CFG(C, 9, AUDIOCLK, GPIO_AF5_SPI1) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(C, 9, DCMI_D3, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(C, 9, FMC_CLE, GPIO_AF11_FMC) +#endif +#ifdef I2C3 +STM32_PIN_FUN_CFG(C, 9, I2C3_SDA, GPIO_AF4_I2C3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(C, 9, OCTOSPI1_IO0, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(C, 9, PSSI_D3, GPIO_AF13_PSSI) +#endif +#ifdef RCC +STM32_PIN_FUN_CFG(C, 9, RCC_MCO_2, GPIO_AF0_MCO) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(C, 9, SDMMC1_D1, GPIO_AF12_SDMMC1) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(C, 9, TIM3_CH4, GPIO_AF2_TIM3) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(C, 9, TIM8_CH4, GPIO_AF3_TIM8) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(C, 9, UART5_CTS, GPIO_AF8_UART5) +#endif +#endif /* GPIOC */ + +/* Port D definitions */ +#ifdef GPIOD +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(D, 0, FDCAN1_RX, GPIO_AF9_FDCAN1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 0, FMC_D2, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 0, FMC_DA2, GPIO_AF12_FMC) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(D, 0, TIM8_CH4N, GPIO_AF3_TIM8) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(D, 0, UART4_RX, GPIO_AF8_UART4) +#endif +#ifdef UART9 +STM32_PIN_FUN_CFG(D, 0, UART9_CTS, GPIO_AF11_UART9) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(D, 1, FDCAN1_TX, GPIO_AF9_FDCAN1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 1, FMC_D3, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 1, FMC_DA3, GPIO_AF12_FMC) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(D, 1, UART4_TX, GPIO_AF8_UART4) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 10, FMC_D15, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 10, FMC_DA15, GPIO_AF12_FMC) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(D, 10, LPTIM2_CH2, GPIO_AF3_LPTIM2) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 10, USART3_CK, GPIO_AF7_USART3) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 11, FMC_A16, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 11, FMC_CLE, GPIO_AF12_FMC) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(D, 11, I2C4_SMBA, GPIO_AF4_I2C4) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(D, 11, LPTIM2_IN2, GPIO_AF3_LPTIM2) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 11, OCTOSPI1_IO0, GPIO_AF9_OCTOSPI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(D, 11, SAI1_CK1, GPIO_AF2_SAI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(D, 11, SAI2_SD_A, GPIO_AF10_SAI2) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(D, 11, UART4_RX, GPIO_AF8_UART4) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 11, USART3_CTS, GPIO_AF7_USART3) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 11, USART3_NSS, GPIO_AF7_USART3) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(D, 12, DCMI_D12, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 12, FMC_A17, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 12, FMC_ALE, GPIO_AF12_FMC) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(D, 12, I2C4_SCL, GPIO_AF4_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(D, 12, I3C1_SCL, GPIO_AF5_I3C1) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(D, 12, LPTIM1_IN1, GPIO_AF1_LPTIM1) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(D, 12, LPTIM2_IN1, GPIO_AF3_LPTIM2) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 12, OCTOSPI1_IO1, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(D, 12, PSSI_D12, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(D, 12, SAI1_D1, GPIO_AF6_SAI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(D, 12, SAI2_FS_A, GPIO_AF10_SAI2) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(D, 12, TIM4_CH1, GPIO_AF2_TIM4) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(D, 12, UART4_TX, GPIO_AF8_UART4) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 12, USART3_DE, GPIO_AF7_USART3) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 12, USART3_RTS, GPIO_AF7_USART3) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(D, 13, DCMI_D13, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 13, FMC_A18, GPIO_AF12_FMC) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(D, 13, I2C4_SDA, GPIO_AF4_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(D, 13, I3C1_SDA, GPIO_AF5_I3C1) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(D, 13, LPTIM1_CH1, GPIO_AF1_LPTIM1) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(D, 13, LPTIM2_CH1, GPIO_AF3_LPTIM2) +#endif +#ifdef LPTIM4 +STM32_PIN_FUN_CFG(D, 13, LPTIM4_IN1, GPIO_AF14_LPTIM4) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 13, OCTOSPI1_IO3, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(D, 13, PSSI_D13, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(D, 13, SAI2_SCK_A, GPIO_AF10_SAI2) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(D, 13, TIM4_CH2, GPIO_AF2_TIM4) +#endif +#ifdef UART9 +STM32_PIN_FUN_CFG(D, 13, UART9_DE, GPIO_AF11_UART9) +#endif +#ifdef UART9 +STM32_PIN_FUN_CFG(D, 13, UART9_RTS, GPIO_AF11_UART9) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 14, FMC_D0, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 14, FMC_DA0, GPIO_AF12_FMC) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(D, 14, TIM4_CH3, GPIO_AF2_TIM4) +#endif +#ifdef UART8 +STM32_PIN_FUN_CFG(D, 14, UART8_CTS, GPIO_AF8_UART8) +#endif +#ifdef UART9 +STM32_PIN_FUN_CFG(D, 14, UART9_RX, GPIO_AF11_UART9) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 15, FMC_D1, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 15, FMC_DA1, GPIO_AF12_FMC) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(D, 15, TIM4_CH4, GPIO_AF2_TIM4) +#endif +#ifdef UART8 +STM32_PIN_FUN_CFG(D, 15, UART8_DE, GPIO_AF8_UART8) +#endif +#ifdef UART8 +STM32_PIN_FUN_CFG(D, 15, UART8_RTS, GPIO_AF8_UART8) +#endif +#ifdef UART9 +STM32_PIN_FUN_CFG(D, 15, UART9_TX, GPIO_AF11_UART9) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(D, 2, DCMI_D11, GPIO_AF13_DCMI) +#endif +#ifdef LPTIM4 +STM32_PIN_FUN_CFG(D, 2, LPTIM4_ETR, GPIO_AF14_LPTIM4) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(D, 2, PSSI_D11, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC1 +STM32_PIN_FUN_CFG(D, 2, SDMMC1_CMD, GPIO_AF12_SDMMC1) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(D, 2, TIM15_BKIN, GPIO_AF4_TIM15) +#endif +#ifdef TIM3 +STM32_PIN_FUN_CFG(D, 2, TIM3_ETR, GPIO_AF2_TIM3) +#endif +#ifdef UART5 +STM32_PIN_FUN_CFG(D, 2, UART5_RX, GPIO_AF8_UART5) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(D, 3, DCMI_D5, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 3, FMC_CLK, GPIO_AF12_FMC) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(D, 3, I2S2_CK, GPIO_AF5_SPI2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(D, 3, PSSI_D5, GPIO_AF13_PSSI) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(D, 3, SPI2_SCK, GPIO_AF5_SPI2) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 3, USART2_CTS, GPIO_AF7_USART2) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 3, USART2_NSS, GPIO_AF7_USART2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 4, FMC_NOE, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 4, OCTOSPI1_IO4, GPIO_AF10_OCTOSPI1) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 4, USART2_DE, GPIO_AF7_USART2) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 4, USART2_RTS, GPIO_AF7_USART2) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(D, 5, FDCAN1_TX, GPIO_AF9_FDCAN1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 5, FMC_NWE, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 5, OCTOSPI1_IO5, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(D, 5, SPI2_RDY, GPIO_AF5_SPI2) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(D, 5, TIM1_CH4N, GPIO_AF1_TIM1) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 5, USART2_TX, GPIO_AF7_USART2) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(D, 6, DCMI_D10, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 6, FMC_NWAIT, GPIO_AF12_FMC) +#endif +#ifdef I2S3 +STM32_PIN_FUN_CFG(D, 6, I2S3_SDO, GPIO_AF5_SPI3) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 6, OCTOSPI1_IO6, GPIO_AF10_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(D, 6, PSSI_D10, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(D, 6, SAI1_D1, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(D, 6, SAI1_SD_A, GPIO_AF6_SAI1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(D, 6, SDMMC2_CK, GPIO_AF11_SDMMC2) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(D, 6, SPI3_MOSI, GPIO_AF5_SPI3) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 6, USART2_RX, GPIO_AF7_USART2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 7, FMC_NCE, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 7, FMC_NE1, GPIO_AF12_FMC) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(D, 7, I2S1_SDO, GPIO_AF5_SPI1) +#endif +#ifdef LPTIM4 +STM32_PIN_FUN_CFG(D, 7, LPTIM4_OUT, GPIO_AF14_LPTIM4) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(D, 7, OCTOSPI1_IO7, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(D, 7, SDMMC2_CMD, GPIO_AF11_SDMMC2) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(D, 7, SPI1_MOSI, GPIO_AF5_SPI1) +#endif +#ifdef USART2 +STM32_PIN_FUN_CFG(D, 7, USART2_CK, GPIO_AF7_USART2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 8, FMC_D13, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 8, FMC_DA13, GPIO_AF12_FMC) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 8, USART3_TX, GPIO_AF7_USART3) +#endif +#ifdef FDCAN2 +STM32_PIN_FUN_CFG(D, 9, FDCAN2_RX, GPIO_AF9_FDCAN2) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 9, FMC_D14, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(D, 9, FMC_DA14, GPIO_AF12_FMC) +#endif +#ifdef USART3 +STM32_PIN_FUN_CFG(D, 9, USART3_RX, GPIO_AF7_USART3) +#endif +#endif /* GPIOD */ + +/* Port E definitions */ +#ifdef GPIOE +#ifdef DCMI +STM32_PIN_FUN_CFG(E, 0, DCMI_D2, GPIO_AF13_DCMI) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(E, 0, FDCAN1_RX, GPIO_AF9_FDCAN1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 0, FMC_NBL0, GPIO_AF12_FMC) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(E, 0, LPTIM1_ETR, GPIO_AF1_LPTIM1) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(E, 0, LPTIM2_CH2, GPIO_AF3_LPTIM2) +#endif +#ifdef LPTIM2 +STM32_PIN_FUN_CFG(E, 0, LPTIM2_ETR, GPIO_AF4_LPTIM2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(E, 0, PSSI_D2, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(E, 0, SAI2_MCLK_A, GPIO_AF10_SAI2) +#endif +#ifdef SPI3 +STM32_PIN_FUN_CFG(E, 0, SPI3_RDY, GPIO_AF6_SPI3) +#endif +#ifdef TIM4 +STM32_PIN_FUN_CFG(E, 0, TIM4_ETR, GPIO_AF2_TIM4) +#endif +#ifdef UART8 +STM32_PIN_FUN_CFG(E, 0, UART8_RX, GPIO_AF8_UART8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(E, 1, DCMI_D3, GPIO_AF13_DCMI) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(E, 1, FDCAN1_TX, GPIO_AF9_FDCAN1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 1, FMC_NBL1, GPIO_AF12_FMC) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(E, 1, LPTIM1_IN2, GPIO_AF1_LPTIM1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(E, 1, PSSI_D3, GPIO_AF13_PSSI) +#endif +#ifdef UART8 +STM32_PIN_FUN_CFG(E, 1, UART8_TX, GPIO_AF8_UART8) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 10, FMC_D7, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 10, FMC_DA7, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(E, 10, OCTOSPI1_IO7, GPIO_AF10_OCTOSPI1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 10, TIM1_CH2N, GPIO_AF1_TIM1) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(E, 10, UART12_TX, GPIO_AF6_UART12) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(E, 10, UART7_CTS, GPIO_AF7_UART7) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 11, FMC_D8, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 11, FMC_DA8, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(E, 11, OCTOSPI1_NCS, GPIO_AF6_OCTOSPI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(E, 11, SAI2_SD_B, GPIO_AF10_SAI2) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(E, 11, SPI1_RDY, GPIO_AF4_SPI1) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(E, 11, SPI4_NSS, GPIO_AF5_SPI4) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 11, TIM1_CH2, GPIO_AF1_TIM1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 12, FMC_D9, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 12, FMC_DA9, GPIO_AF12_FMC) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(E, 12, SAI2_SCK_B, GPIO_AF10_SAI2) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(E, 12, SPI4_SCK, GPIO_AF5_SPI4) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 12, TIM1_CH3N, GPIO_AF1_TIM1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 13, FMC_D10, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 13, FMC_DA10, GPIO_AF12_FMC) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(E, 13, SAI2_FS_B, GPIO_AF10_SAI2) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(E, 13, SPI4_MISO, GPIO_AF5_SPI4) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 13, TIM1_CH3, GPIO_AF1_TIM1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 14, FMC_D11, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 14, FMC_DA11, GPIO_AF12_FMC) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(E, 14, SAI2_MCLK_B, GPIO_AF10_SAI2) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(E, 14, SPI4_MOSI, GPIO_AF5_SPI4) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 14, TIM1_CH4, GPIO_AF1_TIM1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 15, FMC_D12, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 15, FMC_DA12, GPIO_AF12_FMC) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 15, TIM1_BKIN, GPIO_AF1_TIM1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 15, TIM1_CH4N, GPIO_AF3_TIM1) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(E, 15, USART10_CK, GPIO_AF7_USART10) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(E, 2, DCMI_D3, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(E, 2, ETH_TXD3, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 2, FMC_A23, GPIO_AF12_FMC) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(E, 2, LPTIM1_IN2, GPIO_AF1_LPTIM1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(E, 2, OCTOSPI1_IO2, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(E, 2, PSSI_D3, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 2, SAI1_CK1, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 2, SAI1_MCLK_A, GPIO_AF6_SAI1) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(E, 2, SPI4_SCK, GPIO_AF5_SPI4) +#endif +#ifdef UART8 +STM32_PIN_FUN_CFG(E, 2, UART8_TX, GPIO_AF8_UART8) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(E, 2, USART10_RX, GPIO_AF7_USART10) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 3, FMC_A19, GPIO_AF12_FMC) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 3, SAI1_SD_B, GPIO_AF6_SAI1) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(E, 3, TIM15_BKIN, GPIO_AF4_TIM15) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(E, 3, USART10_TX, GPIO_AF7_USART10) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(E, 4, DCMI_D4, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 4, FMC_A20, GPIO_AF12_FMC) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(E, 4, PSSI_D4, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 4, SAI1_D2, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 4, SAI1_FS_A, GPIO_AF6_SAI1) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(E, 4, SPI4_NSS, GPIO_AF5_SPI4) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(E, 4, TIM15_CH1N, GPIO_AF4_TIM15) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(E, 5, DCMI_D6, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 5, FMC_A21, GPIO_AF12_FMC) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(E, 5, PSSI_D6, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 5, SAI1_CK2, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 5, SAI1_SCK_A, GPIO_AF6_SAI1) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(E, 5, SPI4_MISO, GPIO_AF5_SPI4) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(E, 5, TIM15_CH1, GPIO_AF4_TIM15) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(E, 6, DCMI_D7, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 6, FMC_A22, GPIO_AF12_FMC) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(E, 6, PSSI_D7, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 6, SAI1_D1, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(E, 6, SAI1_SD_A, GPIO_AF6_SAI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(E, 6, SAI2_MCLK_B, GPIO_AF10_SAI2) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(E, 6, SPI4_MOSI, GPIO_AF5_SPI4) +#endif +#ifdef TIM15 +STM32_PIN_FUN_CFG(E, 6, TIM15_CH2, GPIO_AF4_TIM15) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 6, TIM1_BKIN2, GPIO_AF1_TIM1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 7, FMC_D4, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 7, FMC_DA4, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(E, 7, OCTOSPI1_IO4, GPIO_AF10_OCTOSPI1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 7, TIM1_ETR, GPIO_AF1_TIM1) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(E, 7, UART12_DE, GPIO_AF6_UART12) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(E, 7, UART12_RTS, GPIO_AF6_UART12) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(E, 7, UART7_RX, GPIO_AF7_UART7) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 8, FMC_D5, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 8, FMC_DA5, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(E, 8, OCTOSPI1_IO5, GPIO_AF10_OCTOSPI1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 8, TIM1_CH1N, GPIO_AF1_TIM1) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(E, 8, UART12_CTS, GPIO_AF6_UART12) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(E, 8, UART7_TX, GPIO_AF7_UART7) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 9, FMC_D6, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(E, 9, FMC_DA6, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(E, 9, OCTOSPI1_IO6, GPIO_AF10_OCTOSPI1) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(E, 9, TIM1_CH1, GPIO_AF1_TIM1) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(E, 9, UART12_RX, GPIO_AF6_UART12) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(E, 9, UART7_DE, GPIO_AF7_UART7) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(E, 9, UART7_RTS, GPIO_AF7_UART7) +#endif +#endif /* GPIOE */ + +/* Port F definitions */ +#ifdef GPIOF +#ifdef FMC +STM32_PIN_FUN_CFG(F, 0, FMC_A0, GPIO_AF12_FMC) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(F, 0, I2C2_SDA, GPIO_AF4_I2C2) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(F, 0, LPTIM5_CH1, GPIO_AF13_LPTIM5) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 1, FMC_A1, GPIO_AF12_FMC) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(F, 1, I2C2_SCL, GPIO_AF4_I2C2) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(F, 1, LPTIM5_CH2, GPIO_AF13_LPTIM5) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(F, 10, DCMI_D11, GPIO_AF13_DCMI) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(F, 10, OCTOSPI1_CLK, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(F, 10, PSSI_D11, GPIO_AF13_PSSI) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(F, 10, PSSI_D15, GPIO_AF4_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(F, 10, SAI1_D3, GPIO_AF2_SAI1) +#endif +#ifdef TIM16 +STM32_PIN_FUN_CFG(F, 10, TIM16_BKIN, GPIO_AF1_TIM16) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(F, 11, DCMI_D12, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 11, FMC_SDNRAS, GPIO_AF12_FMC) +#endif +#ifdef LPTIM6 +STM32_PIN_FUN_CFG(F, 11, LPTIM6_CH1, GPIO_AF14_LPTIM6) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(F, 11, OCTOSPI1_NCLK, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(F, 11, PSSI_D12, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(F, 11, SAI2_SD_B, GPIO_AF10_SAI2) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(F, 11, SPI5_MOSI, GPIO_AF5_SPI5) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 12, FMC_A6, GPIO_AF12_FMC) +#endif +#ifdef LPTIM6 +STM32_PIN_FUN_CFG(F, 12, LPTIM6_CH2, GPIO_AF14_LPTIM6) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 13, FMC_A7, GPIO_AF12_FMC) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(F, 13, I2C4_SMBA, GPIO_AF4_I2C4) +#endif +#ifdef LPTIM6 +STM32_PIN_FUN_CFG(F, 13, LPTIM6_IN1, GPIO_AF14_LPTIM6) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 14, FMC_A8, GPIO_AF12_FMC) +#endif +#ifdef LPTIM6 +STM32_PIN_FUN_CFG(F, 14, LPTIM6_IN2, GPIO_AF14_LPTIM6) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 15, FMC_A9, GPIO_AF12_FMC) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(F, 15, I2C4_SDA, GPIO_AF4_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(F, 15, I3C1_SDA, GPIO_AF5_I3C1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 2, FMC_A2, GPIO_AF12_FMC) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(F, 2, I2C2_SMBA, GPIO_AF4_I2C2) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(F, 2, LPTIM3_CH2, GPIO_AF2_LPTIM3) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(F, 2, LPTIM3_IN2, GPIO_AF3_LPTIM3) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(F, 2, LPTIM5_IN1, GPIO_AF13_LPTIM5) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(F, 2, UART12_TX, GPIO_AF6_UART12) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(F, 2, USART11_CK, GPIO_AF7_USART11) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 3, FMC_A3, GPIO_AF12_FMC) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(F, 3, LPTIM3_IN1, GPIO_AF2_LPTIM3) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(F, 3, LPTIM5_IN2, GPIO_AF13_LPTIM5) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(F, 3, USART11_TX, GPIO_AF7_USART11) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 4, FMC_A4, GPIO_AF12_FMC) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(F, 4, LPTIM3_ETR, GPIO_AF2_LPTIM3) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(F, 4, USART11_RX, GPIO_AF7_USART11) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(F, 5, FMC_A5, GPIO_AF12_FMC) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(F, 5, I2C4_SCL, GPIO_AF4_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(F, 5, I3C1_SCL, GPIO_AF5_I3C1) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(F, 5, LPTIM3_CH1, GPIO_AF2_LPTIM3) +#endif +#ifdef LPTIM3 +STM32_PIN_FUN_CFG(F, 5, LPTIM3_IN1, GPIO_AF14_LPTIM3) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(F, 5, UART12_RX, GPIO_AF6_UART12) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(F, 5, USART11_CTS, GPIO_AF7_USART11) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(F, 5, USART11_NSS, GPIO_AF7_USART11) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(F, 6, LPTIM5_CH1, GPIO_AF13_LPTIM5) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(F, 6, OCTOSPI1_IO3, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(F, 6, SAI1_SD_B, GPIO_AF6_SAI1) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(F, 6, SPI5_NSS, GPIO_AF5_SPI5) +#endif +#ifdef TIM16 +STM32_PIN_FUN_CFG(F, 6, TIM16_CH1, GPIO_AF1_TIM16) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(F, 6, UART7_RX, GPIO_AF7_UART7) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(F, 7, LPTIM5_CH2, GPIO_AF13_LPTIM5) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(F, 7, OCTOSPI1_IO2, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(F, 7, SAI1_MCLK_B, GPIO_AF6_SAI1) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(F, 7, SPI5_SCK, GPIO_AF5_SPI5) +#endif +#ifdef TIM17 +STM32_PIN_FUN_CFG(F, 7, TIM17_CH1, GPIO_AF1_TIM17) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(F, 7, UART7_TX, GPIO_AF7_UART7) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(F, 8, LPTIM5_IN1, GPIO_AF13_LPTIM5) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(F, 8, OCTOSPI1_IO0, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(F, 8, SAI1_SCK_B, GPIO_AF6_SAI1) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(F, 8, SPI5_MISO, GPIO_AF5_SPI5) +#endif +#ifdef TIM13 +STM32_PIN_FUN_CFG(F, 8, TIM13_CH1, GPIO_AF9_TIM13) +#endif +#ifdef TIM16 +STM32_PIN_FUN_CFG(F, 8, TIM16_CH1N, GPIO_AF1_TIM16) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(F, 8, UART7_DE, GPIO_AF7_UART7) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(F, 8, UART7_RTS, GPIO_AF7_UART7) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(F, 9, LPTIM5_IN2, GPIO_AF13_LPTIM5) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(F, 9, OCTOSPI1_IO1, GPIO_AF10_OCTOSPI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(F, 9, SAI1_FS_B, GPIO_AF6_SAI1) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(F, 9, SPI5_MOSI, GPIO_AF5_SPI5) +#endif +#ifdef TIM14 +STM32_PIN_FUN_CFG(F, 9, TIM14_CH1, GPIO_AF9_TIM14) +#endif +#ifdef TIM17 +STM32_PIN_FUN_CFG(F, 9, TIM17_CH1N, GPIO_AF1_TIM17) +#endif +#ifdef UART7 +STM32_PIN_FUN_CFG(F, 9, UART7_CTS, GPIO_AF7_UART7) +#endif +#endif /* GPIOF */ + +/* Port G definitions */ +#ifdef GPIOG +#ifdef FMC +STM32_PIN_FUN_CFG(G, 0, FMC_A10, GPIO_AF12_FMC) +#endif +#ifdef LPTIM4 +STM32_PIN_FUN_CFG(G, 0, LPTIM4_IN1, GPIO_AF14_LPTIM4) +#endif +#ifdef UART9 +STM32_PIN_FUN_CFG(G, 0, UART9_RX, GPIO_AF11_UART9) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 1, FMC_A11, GPIO_AF12_FMC) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(G, 1, I2S2_SDO, GPIO_AF7_SPI2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(G, 1, SPI2_MOSI, GPIO_AF7_SPI2) +#endif +#ifdef UART9 +STM32_PIN_FUN_CFG(G, 1, UART9_TX, GPIO_AF11_UART9) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(G, 10, DCMI_D2, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 10, FMC_NE3, GPIO_AF12_FMC) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(G, 10, I2S1_WS, GPIO_AF5_SPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(G, 10, PSSI_D2, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(G, 10, SAI2_SD_B, GPIO_AF10_SAI2) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(G, 10, SDMMC2_D1, GPIO_AF11_SDMMC2) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(G, 10, SPI1_NSS, GPIO_AF5_SPI1) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(G, 11, DCMI_D3, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(G, 11, ETH_TX_EN, GPIO_AF11_ETH) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(G, 11, I2S1_CK, GPIO_AF5_SPI1) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(G, 11, LPTIM1_IN2, GPIO_AF1_LPTIM1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(G, 11, PSSI_D3, GPIO_AF13_PSSI) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(G, 11, SDMMC2_D2, GPIO_AF10_SDMMC2) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(G, 11, SPI1_SCK, GPIO_AF5_SPI1) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(G, 11, USART10_RX, GPIO_AF6_USART10) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(G, 11, USART11_DE, GPIO_AF7_USART11) +#endif +#ifdef USART11 +STM32_PIN_FUN_CFG(G, 11, USART11_RTS, GPIO_AF7_USART11) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(G, 12, DCMI_D11, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(G, 12, ETH_TXD1, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 12, FMC_NE4, GPIO_AF12_FMC) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(G, 12, LPTIM1_IN1, GPIO_AF1_LPTIM1) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(G, 12, LPTIM5_CH1, GPIO_AF14_LPTIM5) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(G, 12, PSSI_D11, GPIO_AF13_PSSI) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(G, 12, PSSI_D15, GPIO_AF4_PSSI) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(G, 12, SDMMC2_D3, GPIO_AF10_SDMMC2) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(G, 12, SPI6_MISO, GPIO_AF5_SPI6) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(G, 12, USART10_TX, GPIO_AF6_USART10) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 12, USART6_DE, GPIO_AF7_USART6) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 12, USART6_RTS, GPIO_AF7_USART6) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(G, 13, ETH_TXD0, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 13, FMC_A24, GPIO_AF12_FMC) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(G, 13, LPTIM1_CH1, GPIO_AF1_LPTIM1) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(G, 13, LPTIM5_CH2, GPIO_AF13_LPTIM5) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(G, 13, SDMMC2_D6, GPIO_AF10_SDMMC2) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(G, 13, SPI6_SCK, GPIO_AF5_SPI6) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(G, 13, USART10_CTS, GPIO_AF6_USART10) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(G, 13, USART10_NSS, GPIO_AF6_USART10) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 13, USART6_CTS, GPIO_AF7_USART6) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 13, USART6_NSS, GPIO_AF7_USART6) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(G, 14, ETH_TXD1, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 14, FMC_A25, GPIO_AF12_FMC) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(G, 14, LPTIM1_CH2, GPIO_AF4_LPTIM1) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(G, 14, LPTIM1_ETR, GPIO_AF1_LPTIM1) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(G, 14, LPTIM5_IN1, GPIO_AF13_LPTIM5) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(G, 14, OCTOSPI1_IO7, GPIO_AF9_OCTOSPI1) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(G, 14, SDMMC2_D7, GPIO_AF10_SDMMC2) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(G, 14, SPI6_MOSI, GPIO_AF5_SPI6) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(G, 14, USART10_DE, GPIO_AF6_USART10) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(G, 14, USART10_RTS, GPIO_AF6_USART10) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 14, USART6_TX, GPIO_AF7_USART6) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(G, 15, DCMI_D13, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 15, FMC_SDNCAS, GPIO_AF12_FMC) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(G, 15, PSSI_D13, GPIO_AF13_PSSI) +#endif +#ifdef SPI4 +STM32_PIN_FUN_CFG(G, 15, SPI4_RDY, GPIO_AF5_SPI4) +#endif +#ifdef USART10 +STM32_PIN_FUN_CFG(G, 15, USART10_CK, GPIO_AF6_USART10) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 15, USART6_CTS, GPIO_AF7_USART6) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 15, USART6_NSS, GPIO_AF7_USART6) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 2, FMC_A12, GPIO_AF12_FMC) +#endif +#ifdef LPTIM6 +STM32_PIN_FUN_CFG(G, 2, LPTIM6_ETR, GPIO_AF14_LPTIM6) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(G, 2, TIM8_BKIN, GPIO_AF3_TIM8) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(G, 2, UART12_RX, GPIO_AF7_UART12) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 3, FMC_A13, GPIO_AF12_FMC) +#endif +#ifdef LPTIM5 +STM32_PIN_FUN_CFG(G, 3, LPTIM5_ETR, GPIO_AF13_LPTIM5) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(G, 3, TIM8_BKIN2, GPIO_AF3_TIM8) +#endif +#ifdef UART12 +STM32_PIN_FUN_CFG(G, 3, UART12_TX, GPIO_AF7_UART12) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 4, FMC_A14, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 4, FMC_BA0, GPIO_AF12_FMC) +#endif +#ifdef LPTIM4 +STM32_PIN_FUN_CFG(G, 4, LPTIM4_ETR, GPIO_AF14_LPTIM4) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(G, 4, TIM1_BKIN2, GPIO_AF1_TIM1) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 5, FMC_A15, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 5, FMC_BA1, GPIO_AF12_FMC) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(G, 5, TIM1_ETR, GPIO_AF1_TIM1) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(G, 6, DCMI_D12, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 6, FMC_NE3, GPIO_AF12_FMC) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(G, 6, I2C4_SDA, GPIO_AF4_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(G, 6, I3C1_SDA, GPIO_AF3_I3C1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(G, 6, OCTOSPI1_NCS, GPIO_AF10_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(G, 6, PSSI_D12, GPIO_AF13_PSSI) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(G, 6, SPI1_RDY, GPIO_AF5_SPI1) +#endif +#ifdef TIM17 +STM32_PIN_FUN_CFG(G, 6, TIM17_BKIN, GPIO_AF1_TIM17) +#endif +#ifdef UCPD1 +STM32_PIN_FUN_CFG(G, 6, UCPD1_FRSTX, GPIO_AF11_UCPD1) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(G, 7, DCMI_D13, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 7, FMC_INT, GPIO_AF12_FMC) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(G, 7, I2C4_SCL, GPIO_AF4_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(G, 7, I3C1_SCL, GPIO_AF3_I3C1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(G, 7, PSSI_D13, GPIO_AF13_PSSI) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(G, 7, SAI1_CK2, GPIO_AF2_SAI1) +#endif +#ifdef SAI1 +STM32_PIN_FUN_CFG(G, 7, SAI1_MCLK_A, GPIO_AF6_SAI1) +#endif +#ifdef UCPD1 +STM32_PIN_FUN_CFG(G, 7, UCPD1_FRSTX, GPIO_AF11_UCPD1) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 7, USART6_CK, GPIO_AF7_USART6) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(G, 8, ETH_PPS_OUT, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 8, FMC_SDCLK, GPIO_AF12_FMC) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(G, 8, SPI6_NSS, GPIO_AF5_SPI6) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(G, 8, TIM8_ETR, GPIO_AF3_TIM8) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 8, USART6_DE, GPIO_AF7_USART6) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 8, USART6_RTS, GPIO_AF7_USART6) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(G, 9, DCMI_VSYNC, GPIO_AF13_DCMI) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 9, FMC_NCE, GPIO_AF12_FMC) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(G, 9, FMC_NE2, GPIO_AF12_FMC) +#endif +#ifdef I2S1 +STM32_PIN_FUN_CFG(G, 9, I2S1_SDI, GPIO_AF5_SPI1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(G, 9, OCTOSPI1_IO6, GPIO_AF9_OCTOSPI1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(G, 9, PSSI_RDY, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(G, 9, SAI2_FS_B, GPIO_AF10_SAI2) +#endif +#ifdef SDMMC2 +STM32_PIN_FUN_CFG(G, 9, SDMMC2_D0, GPIO_AF11_SDMMC2) +#endif +#ifdef SPI1 +STM32_PIN_FUN_CFG(G, 9, SPI1_MISO, GPIO_AF5_SPI1) +#endif +#ifdef USART6 +STM32_PIN_FUN_CFG(G, 9, USART6_RX, GPIO_AF7_USART6) +#endif +#endif /* GPIOG */ + +/* Port H definitions */ +#ifdef GPIOH +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 10, DCMI_D1, GPIO_AF13_DCMI) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(H, 10, I2C4_SMBA, GPIO_AF4_I2C4) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 10, PSSI_D1, GPIO_AF13_PSSI) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(H, 10, SPI5_RDY, GPIO_AF5_SPI5) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(H, 10, TIM1_CH1N, GPIO_AF1_TIM1) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(H, 10, TIM5_CH1, GPIO_AF2_TIM5) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 10, TIM8_CH3, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 11, DCMI_D2, GPIO_AF13_DCMI) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(H, 11, I2C4_SCL, GPIO_AF4_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(H, 11, I3C1_SCL, GPIO_AF5_I3C1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 11, PSSI_D2, GPIO_AF13_PSSI) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(H, 11, TIM1_CH1, GPIO_AF1_TIM1) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(H, 11, TIM5_CH2, GPIO_AF2_TIM5) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 11, TIM8_CH3N, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 12, DCMI_D3, GPIO_AF13_DCMI) +#endif +#ifdef I2C4 +STM32_PIN_FUN_CFG(H, 12, I2C4_SDA, GPIO_AF4_I2C4) +#endif +#ifdef I3C1 +STM32_PIN_FUN_CFG(H, 12, I3C1_SDA, GPIO_AF5_I3C1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 12, PSSI_D3, GPIO_AF13_PSSI) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(H, 12, TIM1_BKIN, GPIO_AF1_TIM1) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(H, 12, TIM5_CH3, GPIO_AF2_TIM5) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 12, TIM8_BKIN, GPIO_AF3_TIM8) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 12, TIM8_CH4N, GPIO_AF10_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 13, DCMI_D3, GPIO_AF13_DCMI) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(H, 13, FDCAN1_TX, GPIO_AF9_FDCAN1) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(H, 13, LPTIM1_IN2, GPIO_AF1_LPTIM1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 13, PSSI_D3, GPIO_AF13_PSSI) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 13, TIM8_CH1N, GPIO_AF3_TIM8) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(H, 13, UART4_TX, GPIO_AF8_UART4) +#endif +#ifdef UART8 +STM32_PIN_FUN_CFG(H, 13, UART8_TX, GPIO_AF7_UART8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 14, DCMI_D4, GPIO_AF13_DCMI) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(H, 14, FDCAN1_RX, GPIO_AF9_FDCAN1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 14, PSSI_D4, GPIO_AF13_PSSI) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 14, TIM8_CH2N, GPIO_AF3_TIM8) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(H, 14, UART4_RX, GPIO_AF8_UART4) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 15, DCMI_D11, GPIO_AF13_DCMI) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 15, PSSI_D11, GPIO_AF13_PSSI) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 15, TIM8_CH3N, GPIO_AF3_TIM8) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(H, 2, ETH_CRS, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(H, 2, FMC_SDCKE0, GPIO_AF12_FMC) +#endif +#ifdef LPTIM1 +STM32_PIN_FUN_CFG(H, 2, LPTIM1_IN2, GPIO_AF1_LPTIM1) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(H, 2, OCTOSPI1_IO4, GPIO_AF9_OCTOSPI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(H, 2, SAI2_SCK_B, GPIO_AF10_SAI2) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(H, 3, ETH_COL, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(H, 3, FMC_SDNE0, GPIO_AF12_FMC) +#endif +#ifdef OCTOSPI1 +STM32_PIN_FUN_CFG(H, 3, OCTOSPI1_IO5, GPIO_AF9_OCTOSPI1) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(H, 3, SAI2_MCLK_B, GPIO_AF10_SAI2) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(H, 4, I2C2_SCL, GPIO_AF4_I2C2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 4, PSSI_D14, GPIO_AF13_PSSI) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(H, 4, SPI5_RDY, GPIO_AF5_SPI5) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(H, 4, SPI6_RDY, GPIO_AF7_SPI6) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(H, 5, FMC_SDNWE, GPIO_AF12_FMC) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(H, 5, I2C2_SDA, GPIO_AF4_I2C2) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(H, 5, SPI5_NSS, GPIO_AF5_SPI5) +#endif +#ifdef SPI6 +STM32_PIN_FUN_CFG(H, 5, SPI6_RDY, GPIO_AF7_SPI6) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 6, DCMI_D8, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(H, 6, ETH_RXD2, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(H, 6, FMC_SDNE1, GPIO_AF12_FMC) +#endif +#ifdef I2C2 +STM32_PIN_FUN_CFG(H, 6, I2C2_SMBA, GPIO_AF4_I2C2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 6, PSSI_D8, GPIO_AF13_PSSI) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(H, 6, SPI5_SCK, GPIO_AF5_SPI5) +#endif +#ifdef TIM12 +STM32_PIN_FUN_CFG(H, 6, TIM12_CH1, GPIO_AF2_TIM12) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(H, 6, TIM1_CH3N, GPIO_AF1_TIM1) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 6, TIM8_CH1, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 7, DCMI_D9, GPIO_AF13_DCMI) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(H, 7, ETH_RXD3, GPIO_AF11_ETH) +#endif +#ifdef FMC +STM32_PIN_FUN_CFG(H, 7, FMC_SDCKE1, GPIO_AF12_FMC) +#endif +#ifdef I2C3 +STM32_PIN_FUN_CFG(H, 7, I2C3_SCL, GPIO_AF4_I2C3) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 7, PSSI_D9, GPIO_AF13_PSSI) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(H, 7, SPI5_MISO, GPIO_AF5_SPI5) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(H, 7, TIM1_CH3, GPIO_AF1_TIM1) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 7, TIM8_CH1N, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 8, DCMI_HSYNC, GPIO_AF13_DCMI) +#endif +#ifdef I2C3 +STM32_PIN_FUN_CFG(H, 8, I2C3_SDA, GPIO_AF4_I2C3) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 8, PSSI_DE, GPIO_AF13_PSSI) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(H, 8, SPI5_MOSI, GPIO_AF5_SPI5) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(H, 8, TIM1_CH2N, GPIO_AF1_TIM1) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(H, 8, TIM5_ETR, GPIO_AF2_TIM5) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 8, TIM8_CH2, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(H, 9, DCMI_D0, GPIO_AF13_DCMI) +#endif +#ifdef I2C3 +STM32_PIN_FUN_CFG(H, 9, I2C3_SMBA, GPIO_AF4_I2C3) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(H, 9, PSSI_D0, GPIO_AF13_PSSI) +#endif +#ifdef SPI5 +STM32_PIN_FUN_CFG(H, 9, SPI5_NSS, GPIO_AF5_SPI5) +#endif +#ifdef TIM12 +STM32_PIN_FUN_CFG(H, 9, TIM12_CH2, GPIO_AF2_TIM12) +#endif +#ifdef TIM1 +STM32_PIN_FUN_CFG(H, 9, TIM1_CH2, GPIO_AF1_TIM1) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(H, 9, TIM8_CH2N, GPIO_AF3_TIM8) +#endif +#endif /* GPIOH */ + +/* Port I definitions */ +#ifdef GPIOI +#ifdef DCMI +STM32_PIN_FUN_CFG(I, 0, DCMI_D13, GPIO_AF13_DCMI) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(I, 0, I2S2_WS, GPIO_AF5_SPI2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 0, PSSI_D13, GPIO_AF13_PSSI) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(I, 0, SPI2_NSS, GPIO_AF5_SPI2) +#endif +#ifdef TIM5 +STM32_PIN_FUN_CFG(I, 0, TIM5_CH4, GPIO_AF2_TIM5) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(I, 1, DCMI_D8, GPIO_AF13_DCMI) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(I, 1, I2S2_CK, GPIO_AF5_SPI2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 1, PSSI_D8, GPIO_AF13_PSSI) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(I, 1, SPI2_SCK, GPIO_AF5_SPI2) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(I, 1, TIM8_BKIN2, GPIO_AF3_TIM8) +#endif +#ifdef ETH +STM32_PIN_FUN_CFG(I, 10, ETH_RX_ER, GPIO_AF11_ETH) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(I, 10, FDCAN1_RX, GPIO_AF9_FDCAN1) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 10, PSSI_D14, GPIO_AF13_PSSI) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 11, PSSI_D15, GPIO_AF13_PSSI) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(I, 2, DCMI_D9, GPIO_AF13_DCMI) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(I, 2, I2S2_SDI, GPIO_AF5_SPI2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 2, PSSI_D9, GPIO_AF13_PSSI) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(I, 2, SPI2_MISO, GPIO_AF5_SPI2) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(I, 2, TIM8_CH4, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(I, 3, DCMI_D10, GPIO_AF13_DCMI) +#endif +#ifdef I2S2 +STM32_PIN_FUN_CFG(I, 3, I2S2_SDO, GPIO_AF5_SPI2) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 3, PSSI_D10, GPIO_AF13_PSSI) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(I, 3, SPI2_MOSI, GPIO_AF5_SPI2) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(I, 3, TIM8_ETR, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(I, 4, DCMI_D5, GPIO_AF13_DCMI) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 4, PSSI_D5, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(I, 4, SAI2_MCLK_A, GPIO_AF10_SAI2) +#endif +#ifdef SPI2 +STM32_PIN_FUN_CFG(I, 4, SPI2_RDY, GPIO_AF7_SPI2) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(I, 4, TIM8_BKIN, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(I, 5, DCMI_VSYNC, GPIO_AF13_DCMI) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 5, PSSI_RDY, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(I, 5, SAI2_SCK_A, GPIO_AF10_SAI2) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(I, 5, TIM8_CH1, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(I, 6, DCMI_D6, GPIO_AF13_DCMI) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 6, PSSI_D6, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(I, 6, SAI2_SD_A, GPIO_AF10_SAI2) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(I, 6, TIM8_CH2, GPIO_AF3_TIM8) +#endif +#ifdef DCMI +STM32_PIN_FUN_CFG(I, 7, DCMI_D7, GPIO_AF13_DCMI) +#endif +#ifdef PSSI +STM32_PIN_FUN_CFG(I, 7, PSSI_D7, GPIO_AF13_PSSI) +#endif +#ifdef SAI2 +STM32_PIN_FUN_CFG(I, 7, SAI2_FS_A, GPIO_AF10_SAI2) +#endif +#ifdef TIM8 +STM32_PIN_FUN_CFG(I, 7, TIM8_CH3, GPIO_AF3_TIM8) +#endif +#ifdef FDCAN1 +STM32_PIN_FUN_CFG(I, 9, FDCAN1_RX, GPIO_AF9_FDCAN1) +#endif +#ifdef UART4 +STM32_PIN_FUN_CFG(I, 9, UART4_RX, GPIO_AF8_UART4) +#endif +#endif /* GPIOI */ + +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_PIN_CFG_H */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5_bsp.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5_bsp.h new file mode 100644 index 0000000000..b8de98a20c --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5_bsp.h @@ -0,0 +1,57 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_STM32H5_BSP_H_ +#define __MCU_STM32H5_BSP_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * BSP specific UART settings. + */ +struct stm32_uart_cfg { + USART_TypeDef *suc_uart; /* UART dev registers */ + volatile uint32_t *suc_rcc_reg; /* RCC register to modify */ + uint32_t suc_rcc_dev; /* RCC device ID */ + int8_t suc_pin_tx; /* pins for IO */ + int8_t suc_pin_rx; + int8_t suc_pin_rts; + int8_t suc_pin_cts; + uint8_t suc_pin_af; /* AF selection for this */ + IRQn_Type suc_irqn; /* NVIC IRQn */ +}; + +/* + * Internal API for stm32h5xx mcu specific code. + */ +int hal_gpio_init_af(int pin, uint8_t af_type, enum hal_gpio_pull pull, uint8_t od); + +struct hal_flash; +extern struct hal_flash stm32h5_flash_dev; + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_STM32H5_BSP_H_ */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5xx_mynewt_hal.h b/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5xx_mynewt_hal.h new file mode 100644 index 0000000000..554bb85796 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/stm32h5xx_mynewt_hal.h @@ -0,0 +1,67 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __MCU_STM32H5_MYNEWT_HAL_H +#define __MCU_STM32H5_MYNEWT_HAL_H + +#include +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/* Helper functions to enable/disable interrupts. */ +#define __HAL_DISABLE_INTERRUPTS(x) \ + do { \ + x = __get_PRIMASK(); \ + __disable_irq(); \ + } while (0) + +#define __HAL_ENABLE_INTERRUPTS(x) \ + do { \ + if (!x) { \ + __enable_irq(); \ + } \ + } while (0) + +int hal_gpio_init_stm(int pin, GPIO_InitTypeDef *cfg); +int hal_gpio_deinit_stm(int pin, GPIO_InitTypeDef *cfg); + +struct stm32_hal_i2c_cfg { + I2C_TypeDef *hic_i2c; + volatile uint32_t *hic_rcc_reg; /* RCC register to modify */ + uint32_t hic_rcc_dev; /* RCC device ID */ + uint32_t (*get_pclk)(void); + uint8_t hic_pin_sda; + uint8_t hic_pin_scl; + uint8_t hic_pin_af; + uint8_t hic_10bit; + uint32_t hic_timingr; /* TIMINGR register */ + uint32_t hic_speed; /* Requested speed (used when hic_timingr is 0) */ +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __MCU_STM32H5_MYNEWT_HAL_H */ diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h503xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h503xx_vectors.h new file mode 100644 index 0000000000..93228fef6e --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h503xx_vectors.h @@ -0,0 +1,169 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR(DebugMon_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C2_EV_IRQHandler) +INT_VECTOR(I3C2_ER_IRQHandler) +INT_VECTOR(COMP1_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h523xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h523xx_vectors.h new file mode 100644 index 0000000000..ece06de361 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h523xx_vectors.h @@ -0,0 +1,168 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR(DebugMon_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR(FDCAN2_IT0_IRQHandler) +INT_VECTOR(FDCAN2_IT1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C2_EV_IRQHandler) +INT_VECTOR(I3C2_ER_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h533xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h533xx_vectors.h new file mode 100644 index 0000000000..eb10d80319 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h533xx_vectors.h @@ -0,0 +1,168 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR(DebugMon_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR(SAES_IRQHandler) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR(FDCAN2_IT0_IRQHandler) +INT_VECTOR(FDCAN2_IT1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR(OTFDEC1_IRQHandler) +INT_VECTOR(AES_IRQHandler) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR(PKA_IRQHandler) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(I3C2_EV_IRQHandler) +INT_VECTOR(I3C2_ER_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h562xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h562xx_vectors.h new file mode 100644 index 0000000000..e2b206f6b6 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h562xx_vectors.h @@ -0,0 +1,166 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR(TIM16_IRQHandler) +INT_VECTOR(TIM17_IRQHandler) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR(SPI5_IRQHandler) +INT_VECTOR(SPI6_IRQHandler) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR(USART10_IRQHandler) +INT_VECTOR(USART11_IRQHandler) +INT_VECTOR(SAI1_IRQHandler) +INT_VECTOR(SAI2_IRQHandler) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR(UART7_IRQHandler) +INT_VECTOR(UART8_IRQHandler) +INT_VECTOR(UART9_IRQHandler) +INT_VECTOR(UART12_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(CORDIC_IRQHandler) +INT_VECTOR(FMAC_IRQHandler) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR(TIM13_IRQHandler) +INT_VECTOR(TIM14_IRQHandler) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR(I2C4_EV_IRQHandler) +INT_VECTOR(I2C4_ER_IRQHandler) +INT_VECTOR(LPTIM3_IRQHandler) +INT_VECTOR(LPTIM4_IRQHandler) +INT_VECTOR(LPTIM5_IRQHandler) +INT_VECTOR(LPTIM6_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h563xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h563xx_vectors.h new file mode 100644 index 0000000000..a1095059c0 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h563xx_vectors.h @@ -0,0 +1,166 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR_DEBUGMON_HANDLER(DebugMon_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR(TIM16_IRQHandler) +INT_VECTOR(TIM17_IRQHandler) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR(SPI5_IRQHandler) +INT_VECTOR(SPI6_IRQHandler) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR(USART10_IRQHandler) +INT_VECTOR(USART11_IRQHandler) +INT_VECTOR(SAI1_IRQHandler) +INT_VECTOR(SAI2_IRQHandler) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR(UART7_IRQHandler) +INT_VECTOR(UART8_IRQHandler) +INT_VECTOR(UART9_IRQHandler) +INT_VECTOR(UART12_IRQHandler) +INT_VECTOR(SDMMC2_IRQHandler) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR(ETH_IRQHandler) +INT_VECTOR(ETH_WKUP_IRQHandler) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR(FDCAN2_IT0_IRQHandler) +INT_VECTOR(FDCAN2_IT1_IRQHandler) +INT_VECTOR(CORDIC_IRQHandler) +INT_VECTOR(FMAC_IRQHandler) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR_UNUSED(0) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR(TIM13_IRQHandler) +INT_VECTOR(TIM14_IRQHandler) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR(I2C4_EV_IRQHandler) +INT_VECTOR(I2C4_ER_IRQHandler) +INT_VECTOR(LPTIM3_IRQHandler) +INT_VECTOR(LPTIM4_IRQHandler) +INT_VECTOR(LPTIM5_IRQHandler) +INT_VECTOR(LPTIM6_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h573xx_vectors.h b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h573xx_vectors.h new file mode 100644 index 0000000000..d7acec3ec3 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/include/mcu/vectors/stm32h573xx_vectors.h @@ -0,0 +1,166 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +INT_VECTOR_STACK_TOP(__StackTop) +INT_VECTOR_RESET_HANDLER(Reset_Handler) +INT_VECTOR_NMI_HANDLER(NMI_Handler) +INT_VECTOR_HARDFAULT_HANDLER(HardFault_Handler) +INT_VECTOR_MEMMANAGE_HANDLER(MemManage_Handler) +INT_VECTOR_BUSFAULT_HANDLER(BusFault_Handler) +INT_VECTOR_USAGEFAULT_HANDLER(UsageFault_Handler) +INT_VECTOR_SECUREFAULT_HANDLER(SecureFault_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_SVC_HANDLER(SVC_Handler) +INT_VECTOR_UNUSED(0) +INT_VECTOR_UNUSED(0) +INT_VECTOR_PENDSV_HANDLER(PendSV_Handler) +INT_VECTOR_SYSTICK_HANDLER(SysTick_Handler) +INT_VECTOR(WWDG_IRQHandler) +INT_VECTOR(PVD_AVD_IRQHandler) +INT_VECTOR(RTC_IRQHandler) +INT_VECTOR(RTC_S_IRQHandler) +INT_VECTOR(TAMP_IRQHandler) +INT_VECTOR(RAMCFG_IRQHandler) +INT_VECTOR(FLASH_IRQHandler) +INT_VECTOR(FLASH_S_IRQHandler) +INT_VECTOR(GTZC_IRQHandler) +INT_VECTOR(RCC_IRQHandler) +INT_VECTOR(RCC_S_IRQHandler) +INT_VECTOR(EXTI0_IRQHandler) +INT_VECTOR(EXTI1_IRQHandler) +INT_VECTOR(EXTI2_IRQHandler) +INT_VECTOR(EXTI3_IRQHandler) +INT_VECTOR(EXTI4_IRQHandler) +INT_VECTOR(EXTI5_IRQHandler) +INT_VECTOR(EXTI6_IRQHandler) +INT_VECTOR(EXTI7_IRQHandler) +INT_VECTOR(EXTI8_IRQHandler) +INT_VECTOR(EXTI9_IRQHandler) +INT_VECTOR(EXTI10_IRQHandler) +INT_VECTOR(EXTI11_IRQHandler) +INT_VECTOR(EXTI12_IRQHandler) +INT_VECTOR(EXTI13_IRQHandler) +INT_VECTOR(EXTI14_IRQHandler) +INT_VECTOR(EXTI15_IRQHandler) +INT_VECTOR(GPDMA1_Channel0_IRQHandler) +INT_VECTOR(GPDMA1_Channel1_IRQHandler) +INT_VECTOR(GPDMA1_Channel2_IRQHandler) +INT_VECTOR(GPDMA1_Channel3_IRQHandler) +INT_VECTOR(GPDMA1_Channel4_IRQHandler) +INT_VECTOR(GPDMA1_Channel5_IRQHandler) +INT_VECTOR(GPDMA1_Channel6_IRQHandler) +INT_VECTOR(GPDMA1_Channel7_IRQHandler) +INT_VECTOR(IWDG_IRQHandler) +INT_VECTOR(SAES_IRQHandler) +INT_VECTOR(ADC1_IRQHandler) +INT_VECTOR(DAC1_IRQHandler) +INT_VECTOR(FDCAN1_IT0_IRQHandler) +INT_VECTOR(FDCAN1_IT1_IRQHandler) +INT_VECTOR(TIM1_BRK_IRQHandler) +INT_VECTOR(TIM1_UP_IRQHandler) +INT_VECTOR(TIM1_TRG_COM_IRQHandler) +INT_VECTOR(TIM1_CC_IRQHandler) +INT_VECTOR(TIM2_IRQHandler) +INT_VECTOR(TIM3_IRQHandler) +INT_VECTOR(TIM4_IRQHandler) +INT_VECTOR(TIM5_IRQHandler) +INT_VECTOR(TIM6_IRQHandler) +INT_VECTOR(TIM7_IRQHandler) +INT_VECTOR(I2C1_EV_IRQHandler) +INT_VECTOR(I2C1_ER_IRQHandler) +INT_VECTOR(I2C2_EV_IRQHandler) +INT_VECTOR(I2C2_ER_IRQHandler) +INT_VECTOR(SPI1_IRQHandler) +INT_VECTOR(SPI2_IRQHandler) +INT_VECTOR(SPI3_IRQHandler) +INT_VECTOR(USART1_IRQHandler) +INT_VECTOR(USART2_IRQHandler) +INT_VECTOR(USART3_IRQHandler) +INT_VECTOR(UART4_IRQHandler) +INT_VECTOR(UART5_IRQHandler) +INT_VECTOR(LPUART1_IRQHandler) +INT_VECTOR(LPTIM1_IRQHandler) +INT_VECTOR(TIM8_BRK_IRQHandler) +INT_VECTOR(TIM8_UP_IRQHandler) +INT_VECTOR(TIM8_TRG_COM_IRQHandler) +INT_VECTOR(TIM8_CC_IRQHandler) +INT_VECTOR(ADC2_IRQHandler) +INT_VECTOR(LPTIM2_IRQHandler) +INT_VECTOR(TIM15_IRQHandler) +INT_VECTOR(TIM16_IRQHandler) +INT_VECTOR(TIM17_IRQHandler) +INT_VECTOR(USB_DRD_FS_IRQHandler) +INT_VECTOR(CRS_IRQHandler) +INT_VECTOR(UCPD1_IRQHandler) +INT_VECTOR(FMC_IRQHandler) +INT_VECTOR(OCTOSPI1_IRQHandler) +INT_VECTOR(SDMMC1_IRQHandler) +INT_VECTOR(I2C3_EV_IRQHandler) +INT_VECTOR(I2C3_ER_IRQHandler) +INT_VECTOR(SPI4_IRQHandler) +INT_VECTOR(SPI5_IRQHandler) +INT_VECTOR(SPI6_IRQHandler) +INT_VECTOR(USART6_IRQHandler) +INT_VECTOR(USART10_IRQHandler) +INT_VECTOR(USART11_IRQHandler) +INT_VECTOR(SAI1_IRQHandler) +INT_VECTOR(SAI2_IRQHandler) +INT_VECTOR(GPDMA2_Channel0_IRQHandler) +INT_VECTOR(GPDMA2_Channel1_IRQHandler) +INT_VECTOR(GPDMA2_Channel2_IRQHandler) +INT_VECTOR(GPDMA2_Channel3_IRQHandler) +INT_VECTOR(GPDMA2_Channel4_IRQHandler) +INT_VECTOR(GPDMA2_Channel5_IRQHandler) +INT_VECTOR(GPDMA2_Channel6_IRQHandler) +INT_VECTOR(GPDMA2_Channel7_IRQHandler) +INT_VECTOR(UART7_IRQHandler) +INT_VECTOR(UART8_IRQHandler) +INT_VECTOR(UART9_IRQHandler) +INT_VECTOR(UART12_IRQHandler) +INT_VECTOR(SDMMC2_IRQHandler) +INT_VECTOR(FPU_IRQHandler) +INT_VECTOR(ICACHE_IRQHandler) +INT_VECTOR(DCACHE1_IRQHandler) +INT_VECTOR(ETH_IRQHandler) +INT_VECTOR(ETH_WKUP_IRQHandler) +INT_VECTOR(DCMI_PSSI_IRQHandler) +INT_VECTOR(FDCAN2_IT0_IRQHandler) +INT_VECTOR(FDCAN2_IT1_IRQHandler) +INT_VECTOR(CORDIC_IRQHandler) +INT_VECTOR(FMAC_IRQHandler) +INT_VECTOR(DTS_IRQHandler) +INT_VECTOR(RNG_IRQHandler) +INT_VECTOR(OTFDEC1_IRQHandler) +INT_VECTOR(AES_IRQHandler) +INT_VECTOR(HASH_IRQHandler) +INT_VECTOR(PKA_IRQHandler) +INT_VECTOR(CEC_IRQHandler) +INT_VECTOR(TIM12_IRQHandler) +INT_VECTOR(TIM13_IRQHandler) +INT_VECTOR(TIM14_IRQHandler) +INT_VECTOR(I3C1_EV_IRQHandler) +INT_VECTOR(I3C1_ER_IRQHandler) +INT_VECTOR(I2C4_EV_IRQHandler) +INT_VECTOR(I2C4_ER_IRQHandler) +INT_VECTOR(LPTIM3_IRQHandler) +INT_VECTOR(LPTIM4_IRQHandler) +INT_VECTOR(LPTIM5_IRQHandler) +INT_VECTOR(LPTIM6_IRQHandler) diff --git a/hw/mcu/stm/stm32h5xx/pkg.yml b/hw/mcu/stm/stm32h5xx/pkg.yml new file mode 100644 index 0000000000..ea98076c05 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/pkg.yml @@ -0,0 +1,71 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/mcu/stm/stm32h5xx +pkg.description: MCU definition for STM32H5 ARM Cortex-M33 chips. +pkg.author: "Apache Mynewt " +pkg.homepage: "http://mynewt.apache.org/" +pkg.keywords: + - stm32 + - stm32h5 + +pkg.type: sdk + +pkg.cflags: + - -Wno-maybe-uninitialized + +pkg.ign_files: + - ".*template.*" + +pkg.include_dirs: + - "@stm-cmsis_device_h5/Include" + - "@stm-stm32h5xx_hal_driver/Inc" + +pkg.src_dirs: + - "@stm-cmsis_device_h5/Source/Templates/gcc" + - "@stm-stm32h5xx_hal_driver/Src" + - "src" + +pkg.ign_dirs: + - "Device" + +pkg.deps: + - "@apache-mynewt-core/hw/hal" + - "@apache-mynewt-core/hw/mcu/stm/stm32_common" + - "@apache-mynewt-core/hw/cmsis-core" + +pkg.deps.'(SPI_0_MASTER || SPI_1_MASTER || SPI_2_MASTER || SPI_3_MASTER || SPI_4_MASTER || SPI_5_MASTER) && BUS_DRIVER_PRESENT': + - "@apache-mynewt-core/hw/bus/drivers/spi_stm32" + +#pkg.deps.ETH_0: +# - "@apache-mynewt-core/hw/drivers/lwip/stm32h_eth" + +repository.stm-cmsis_device_h5: + type: github + vers: v1.6.0-commit + branch: main + user: STMicroelectronics + repo: cmsis_device_h5 + +repository.stm-stm32h5xx_hal_driver: + type: github + vers: v1.6.0-commit + branch: main + user: STMicroelectronics + repo: stm32h5xx_hal_driver diff --git a/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c b/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c new file mode 100644 index 0000000000..cf1cb52aab --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/clock_stm32h5xx.c @@ -0,0 +1,194 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include +#include +#include +#include +#include +#include + +/* + * This allows an user to have a custom clock configuration by zeroing + * every possible clock source in the syscfg. + */ +#if MYNEWT_VAL_STM32_CLOCK_HSE || MYNEWT_VAL_STM32_CLOCK_LSE || \ + MYNEWT_VAL_STM32_CLOCK_HSI || MYNEWT_VAL_STM32_CLOCK_LSI + +/* + * HSI is turned on by default, but can be turned off and use HSE instead. + */ +_Static_assert((MYNEWT_VAL_STM32_CLOCK_HSE != 0) + (MYNEWT_VAL_STM32_CLOCK_HSI != 0) >= 1, + "At least one of HSE or HSI clock source must be enabled"); + +#define PLL_ON(n) (MYNEWT_VAL_STM32_CLOCK_##n != 0) +#define PLL_OFF(n) (MYNEWT_VAL_STM32_CLOCK_##n == 0) +#define PLL_VAL(n, val) MYNEWT_VAL_STM32_CLOCK_##n##_##val + +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLM_VALUE(PLL_VAL(PLL1, PLLM)), + "PLLM value is invalid"); +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLN_VALUE(PLL_VAL(PLL1, PLLN)), + "PLLN value is invalid"); +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLP_VALUE(PLL_VAL(PLL1, PLLP)), + "PLLP value is invalid"); +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLQ_VALUE(PLL_VAL(PLL1, PLLQ)), + "PLLQ value is invalid"); +_Static_assert(PLL_OFF(PLL1) || IS_RCC_PLLR_VALUE(PLL_VAL(PLL1, PLLR)), + "PLLR value is invalid"); + +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLM_VALUE(PLL_VAL(PLL2, PLLM)), + "PLLM value is invalid"); +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLN_VALUE(PLL_VAL(PLL2, PLLN)), + "PLLN value is invalid"); +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLP_VALUE(PLL_VAL(PLL2, PLLP)), + "PLLP value is invalid"); +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLQ_VALUE(PLL_VAL(PLL2, PLLQ)), + "PLLQ value is invalid"); +_Static_assert(PLL_OFF(PLL2) || IS_RCC_PLLR_VALUE(PLL_VAL(PLL2, PLLR)), + "PLLR value is invalid"); + +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLM_VALUE(PLL_VAL(PLL3, PLLM)), + "PLLM value is invalid"); +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLN_VALUE(PLL_VAL(PLL3, PLLN)), + "PLLN value is invalid"); +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLP_VALUE(PLL_VAL(PLL3, PLLP)), + "PLLP value is invalid"); +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLQ_VALUE(PLL_VAL(PLL3, PLLQ)), + "PLLQ value is invalid"); +_Static_assert(PLL_OFF(PLL3) || IS_RCC_PLLR_VALUE(PLL_VAL(PLL3, PLLR)), + "PLLR value is invalid"); + +_Static_assert(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE != LL_RCC_SYS_CLKSOURCE_PLL1 || + PLL_ON(PLL1), + "PLL1 selected as system clock but no enabled"); + +#define BUSY_LOOP(cond) \ + while (cond) { \ + } + +void +SystemClock_Config(void) +{ + LL_PWR_SetRegulVoltageScaling(MYNEWT_VAL_STM32_CLOCK_VOLTAGESCALING_CONFIG); + BUSY_LOOP(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)); + + __HAL_FLASH_SET_LATENCY(MYNEWT_VAL_STM32_FLASH_LATENCY); + __HAL_FLASH_SET_PROGRAM_DELAY(MYNEWT_VAL_STM32_FLASH_PROGRAM_DELAY); + + if (MYNEWT_VAL_STM32_CLOCK_LSI) { + LL_RCC_LSI_Enable(); + } + if (MYNEWT_VAL_STM32_CLOCK_LSE_BYPASS && !LL_RCC_LSE_IsReady()) { + LL_PWR_EnableBkUpAccess(); + LL_RCC_LSE_EnableBypass(); + } + if (MYNEWT_VAL_STM32_CLOCK_LSE && !LL_RCC_LSE_IsReady()) { + LL_PWR_EnableBkUpAccess(); + LL_RCC_LSE_Enable(); + } + if (MYNEWT_VAL_STM32_CLOCK_HSE_BYPASS) { + LL_RCC_HSE_EnableBypass(); + } + if (MYNEWT_VAL_STM32_CLOCK_HSE) { + LL_RCC_HSE_Enable(); + } + + if (MYNEWT_VAL_STM32_CLOCK_HSI48) { + LL_RCC_HSI48_Enable(); + } + + LL_RCC_SetAHBPrescaler(MYNEWT_VAL_STM32_CLOCK_AHB_DIVIDER); + LL_RCC_SetAPB1Prescaler(MYNEWT_VAL_STM32_CLOCK_APB1_DIVIDER); + LL_RCC_SetAPB2Prescaler(MYNEWT_VAL_STM32_CLOCK_APB2_DIVIDER); + LL_RCC_SetAPB3Prescaler(MYNEWT_VAL_STM32_CLOCK_APB3_DIVIDER); + + if (MYNEWT_VAL_STM32_CLOCK_USBSEL) { + LL_RCC_SetUSBClockSource(MYNEWT_VAL_STM32_CLOCK_USBSEL); + } + + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL1, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); + if (PLL_ON(PLL1)) { + LL_RCC_PLL1_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL1_SOURCE); + LL_RCC_PLL1_SetM(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLM); + LL_RCC_PLL1_SetN(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLN); + LL_RCC_PLL1_SetP(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLP); + LL_RCC_PLL1_SetQ(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLQ); + LL_RCC_PLL1_SetR(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLR); + if (MYNEWT_VAL_STM32_CLOCK_PLL1_PLLFRACN) { + LL_RCC_PLL1_SetFRACN(MYNEWT_VAL_STM32_CLOCK_PLL1_PLLFRACN); + } + LL_RCC_PLL1_SetVCOInputRange(MYNEWT_VAL_STM32_CLOCK_PLL1_RGE); + LL_RCC_PLL1_Enable(); + LL_RCC_PLL1P_Enable(); + LL_RCC_PLL1Q_Enable(); + } + + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL2, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); + if (PLL_ON(PLL2)) { + LL_RCC_PLL2_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL2_SOURCE); + LL_RCC_PLL2_SetM(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLM); + LL_RCC_PLL2_SetN(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLN); + LL_RCC_PLL2_SetP(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLP); + LL_RCC_PLL2_SetQ(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLQ); + LL_RCC_PLL2_SetR(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLR); + if (MYNEWT_VAL_STM32_CLOCK_PLL2_PLLFRACN) { + LL_RCC_PLL2_SetFRACN(MYNEWT_VAL_STM32_CLOCK_PLL2_PLLFRACN); + } + LL_RCC_PLL2_SetVCOInputRange(MYNEWT_VAL_STM32_CLOCK_PLL2_RGE); + LL_RCC_PLL2_Enable(); + LL_RCC_PLL2P_Enable(); + LL_RCC_PLL2Q_Enable(); + } + +#if RCC_CR_PLL3ON + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_HSE && !LL_RCC_HSE_IsReady()); + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_HSI && !LL_RCC_HSI_IsReady()); + BUSY_LOOP(PLL_VAL(PLL3, SOURCE) == LL_RCC_PLL1SOURCE_CSI && !LL_RCC_CSI_IsReady()); + if (PLL_ON(PLL3)) { + LL_RCC_PLL3_SetSource(MYNEWT_VAL_STM32_CLOCK_PLL3_SOURCE); + LL_RCC_PLL3_SetM(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLM); + LL_RCC_PLL3_SetN(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLN); + LL_RCC_PLL3_SetP(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLP); + LL_RCC_PLL3_SetQ(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLQ); + LL_RCC_PLL3_SetR(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLR); + if (MYNEWT_VAL_STM32_CLOCK_PLL3_PLLFRACN) { + LL_RCC_PLL3_SetFRACN(MYNEWT_VAL_STM32_CLOCK_PLL3_PLLFRACN); + } + LL_RCC_PLL3_SetVCOInputRange(MYNEWT_VAL_STM32_CLOCK_PLL3_RGE); + LL_RCC_PLL3_Enable(); + LL_RCC_PLL3P_Enable(); + LL_RCC_PLL3Q_Enable(); + } +#endif + BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE == LL_RCC_SYS_CLKSOURCE_HSI && + !LL_RCC_HSI_IsReady()); + BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE == LL_RCC_SYS_CLKSOURCE_HSE && + !LL_RCC_HSE_IsReady()); + BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE == LL_RCC_SYS_CLKSOURCE_CSI && + !LL_RCC_CSI_IsReady()); + BUSY_LOOP(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE == LL_RCC_SYS_CLKSOURCE_PLL1 && + !LL_RCC_PLL1_IsReady()); + LL_RCC_SetSysClkSource(MYNEWT_VAL_STM32_CLOCK_SYSCLK_SOURCE); +} + +#endif diff --git a/hw/mcu/stm/stm32h5xx/src/hal_flash.c b/hw/mcu/stm/stm32h5xx/src/hal_flash.c new file mode 100644 index 0000000000..2e023d966b --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/hal_flash.c @@ -0,0 +1,55 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include +#include +#include "hal/hal_flash_int.h" + +#define STM32_FLASH_SIZE (MYNEWT_VAL_STM32_FLASH_SIZE_KB * 1024) + +int +stm32_mcu_flash_erase_sector(const struct hal_flash *dev, uint32_t sector_address) +{ + FLASH_EraseInitTypeDef eraseinit; + uint32_t PageError; + HAL_StatusTypeDef rc; + + (void)PageError; + + if (!(sector_address & (FLASH_SECTOR_SIZE - 1))) { + eraseinit.TypeErase = FLASH_TYPEERASE_SECTORS; +#ifdef FLASH_BANK_2 + if ((sector_address - dev->hf_base_addr) < (STM32_FLASH_SIZE / 2)) { + eraseinit.Banks = FLASH_BANK_1; + } else { + eraseinit.Banks = FLASH_BANK_2; + } +#else + eraseinit.Banks = FLASH_BANK_1; +#endif + eraseinit.Sector = ((sector_address - dev->hf_base_addr) / FLASH_SECTOR_SIZE) % FLASH_SECTOR_NB; + eraseinit.NbSectors = 1; + rc = HAL_FLASHEx_Erase(&eraseinit, &PageError); + if (rc == HAL_OK) { + return 0; + } + } + + return -1; +} diff --git a/hw/mcu/stm/stm32h5xx/src/hal_reset_cause.c b/hw/mcu/stm/stm32h5xx/src/hal_reset_cause.c new file mode 100644 index 0000000000..4b366b39c1 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/hal_reset_cause.c @@ -0,0 +1,47 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ +#include + +#include + +enum hal_reset_reason +hal_reset_cause(void) +{ + static enum hal_reset_reason reason; + uint32_t reg; + + if (reason) { + return reason; + } + + reg = RCC->RSR; + if (reg & RCC_RSR_WWDGRSTF || reg & RCC_RSR_IWDGRSTF) { + reason = HAL_RESET_WATCHDOG; + } else if (reg & RCC_RSR_SFTRSTF) { + reason = HAL_RESET_SOFT; + } else if (reg & RCC_RSR_PINRSTF) { + reason = HAL_RESET_PIN; + } else if (reg & RCC_RSR_BORRSTF) { + reason = HAL_RESET_BROWNOUT; + } else { + reason = HAL_RESET_POR; + } + RCC->RSR |= RCC_RSR_RMVF; + return reason; +} diff --git a/hw/mcu/stm/stm32h5xx/src/hal_system_init.c b/hw/mcu/stm/stm32h5xx/src/hal_system_init.c new file mode 100644 index 0000000000..2807e15d37 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/hal_system_init.c @@ -0,0 +1,57 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/mynewt.h" +#include "mcu/stm32_hal.h" +#include + +void SystemClock_Config(void); + +void +hal_system_init(void) +{ + /* Configure System Clock */ + SystemClock_Config(); + + /* Update SystemCoreClock global variable */ + SystemCoreClockUpdate(); + + /* Relocate the vector table */ + NVIC_Relocate(); + + if (MYNEWT_VAL_STM32_FLASH_PREFETCH_ENABLE) { + __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); + } else { + __HAL_FLASH_PREFETCH_BUFFER_DISABLE(); + } + + if (MYNEWT_VAL_STM32_ENABLE_ICACHE) { + HAL_ICACHE_Enable(); + } + +#ifdef DCACHE1 + if (MYNEWT_VAL_STM32_ENABLE_DCACHE) { + DCACHE_HandleTypeDef cache = { + .Instance = DCACHE1, + .Init.ReadBurstType = DCACHE_READ_BURST_WRAP, + }; + HAL_DCACHE_Init(&cache); + } +#endif +} diff --git a/hw/mcu/stm/stm32h5xx/src/hal_timer_freq.c b/hw/mcu/stm/stm32h5xx/src/hal_timer_freq.c new file mode 100644 index 0000000000..42f13e0ec5 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/hal_timer_freq.c @@ -0,0 +1,129 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include "os/mynewt.h" + +#include +#include +#include + +static uint32_t +stm32_hal_timer_abp_clk_div(uint32_t divider) +{ + switch (divider) { + case RCC_HCLK_DIV1: + return 1; + case RCC_HCLK_DIV2: + return 2; + case RCC_HCLK_DIV4: + return 4; + case RCC_HCLK_DIV8: + return 8; + case RCC_HCLK_DIV16: + return 16; + } + return 0; +} + +uint32_t +stm32_hal_timer_get_freq(void *timx) +{ + uintptr_t regs = (uintptr_t)timx; + RCC_ClkInitTypeDef clocks; + uint32_t flashLatency; + uint32_t freq = 0; + uint32_t div = 0; + + HAL_RCC_GetClockConfig(&clocks, &flashLatency); + + switch (regs) { +#ifdef TIM1 + case (uintptr_t)TIM1: +#endif +#ifdef TIM8 + case (uintptr_t)TIM8: +#endif +#ifdef TIM15 + case (uintptr_t)TIM15: +#endif +#ifdef TIM16 + case (uintptr_t)TIM16: +#endif +#ifdef TIM17 + case (uintptr_t)TIM17: +#endif + freq = HAL_RCC_GetPCLK2Freq(); + div = stm32_hal_timer_abp_clk_div(clocks.APB2CLKDivider); + break; + +#ifdef TIM2 + case (uintptr_t)TIM2: +#endif +#ifdef TIM3 + case (uintptr_t)TIM3: +#endif +#ifdef TIM4 + case (uintptr_t)TIM4: +#endif +#ifdef TIM5 + case (uintptr_t)TIM5: +#endif +#ifdef TIM6 + case (uintptr_t)TIM6: +#endif +#ifdef TIM7 + case (uintptr_t)TIM7: +#endif + +#ifdef TIM12 + case (uintptr_t)TIM12: +#endif +#ifdef TIM13 + case (uintptr_t)TIM13: +#endif +#ifdef TIM14 + case (uintptr_t)TIM14: +#endif +#ifdef TIM23 + case (uintptr_t)TIM23: +#endif +#ifdef TIM24 + case (uintptr_t)TIM24: +#endif + freq = HAL_RCC_GetPCLK1Freq(); + div = stm32_hal_timer_abp_clk_div(clocks.APB1CLKDivider); + break; + + default: + assert(0); + return 0; + } + + if (RCC_TIMPRES_ACTIVATED == READ_BIT(RCC->CFGR1, RCC_CFGR1_TIMPRE)) { + if (div > 2) { + return freq * 4; + } + return freq * div; + } + + if (div > 1) { + return freq * 2; + } + return freq; +} diff --git a/hw/mcu/stm/stm32h5xx/src/stm32_clock.c b/hw/mcu/stm/stm32h5xx/src/stm32_clock.c new file mode 100644 index 0000000000..189727389c --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/stm32_clock.c @@ -0,0 +1,96 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include +#include +#include + +#define STM32_PER_CLOCK_DEF(per) \ +void per##_clock_enable(stm32_clock_t clock) \ +{\ + __HAL_RCC_##per##_CLK_ENABLE(); \ +}\ +void per##_clock_disable(stm32_clock_t clock) \ +{\ + __HAL_RCC_##per##_CLK_ENABLE(); \ +}\ +const struct stm32_clock_ops per##_clock_ops = { \ + .enable = per##_clock_enable, \ + .disable = per##_clock_disable, \ +};\ +const struct stm32_clock _##per##_clock = { \ + .ops = &per##_clock_ops, \ +}; + +#define STM32_CLKSEL_DEF1(per, rcc_reg, reg_field, reg_val) \ +const struct stm32_clock_src _##per##_##reg_val = {\ + .base.ops = &stm32_clksel_ops,\ + .reg = &RCC->rcc_reg,\ + .mask = RCC_##rcc_reg##_##reg_field,\ + .value = LL_RCC##_##per##_CLKSOURCE_##reg_val,\ +} + +#define STM32_CLKSEL_DEF2(per, rcc_reg, reg_field, reg_val) \ +const struct stm32_clock_src _##per##_##reg_val = {\ + .base.ops = &stm32_clksel_ops,\ + .reg = &RCC->rcc_reg,\ + .mask = RCC_##rcc_reg##_##reg_field,\ + .value = (((LL_RCC_##per##_CLKSOURCE_##reg_val) >> LL_RCC_CONFIG_SHIFT) && 0xFF)\ + << RCC_##rcc_reg##_##reg_field##_Pos,\ +} + +#include + +void +stm32_clock_enable(stm32_clock_t clock) +{ + clock->ops->enable(clock); +} + +void +stm32_clock_disable(stm32_clock_t clock) +{ + clock->ops->disable(clock); +} + + +struct stm32_clock_src { + struct stm32_clock base; + __IO uint32_t *reg; + uint32_t mask; + uint32_t value; +}; + +void stm32_clksel_enable(stm32_clock_t clock) +{ + stm32_clock_src_t clksel = (stm32_clock_src_t)clock; + + *clksel->reg = (*clksel->reg & ~clksel->mask) | clksel->value; +} + +void stm32_clksel_disable(stm32_clock_t clock) +{ +} + +static const struct stm32_clock_ops stm32_clksel_ops = { + .enable = stm32_clksel_enable, + .disable = stm32_clksel_disable, +}; + +#include diff --git a/hw/mcu/stm/stm32h5xx/src/stm32_pin_cfg.c b/hw/mcu/stm/stm32h5xx/src/stm32_pin_cfg.c new file mode 100644 index 0000000000..f2af0a9ad0 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/stm32_pin_cfg.c @@ -0,0 +1,112 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include +#include +#include + +#define STM32_PIN_FUN_CFG(port_n, pin_n, pf, af) \ +const struct stm32_pin_cfg _P##port_n##pin_n##_##pf = {\ + .pin = MCU_GPIO_PORT##port_n(pin_n),\ + .hal_init = {\ + .Pin = 1 << (pin_n), \ + .Mode = GPIO_MODE_AF_PP, \ + .Pull = GPIO_NOPULL, \ + .Speed = GPIO_SPEED_FREQ_VERY_HIGH, \ + .Alternate = af, \ + }\ +};\ +static stm32_pin_cfg_t const P##port_n##pin_n##_##pf __unused = &_P##port_n##pin_n##_##pf; + +#define STM32_PIN_FUN_OD_CFG(port_n, pin_n, pf, af) \ +const struct stm32_pin_cfg _P##port_n##pin_n##_##pf##_OD = {\ + .pin = MCU_GPIO_PORT##port_n(pin_n),\ + .hal_init = {\ + .Pin = 1 << (pin_n), \ + .Mode = GPIO_MODE_AF_OD, \ + .Pull = GPIO_NOPULL, \ + .Speed = GPIO_SPEED_FREQ_VERY_HIGH, \ + .Alternate = af, \ + }\ +};\ +static stm32_pin_cfg_t const P##port_n##pin_n##_##pf##_OD __unused = &_P##port_n##pin_n##_##pf##_OD; + +#define STM32_PIN_FUN_OD_PU_CFG(port_n, pin_n, pf, af) \ +const struct stm32_pin_cfg _P##port_n##pin_n##_##pf##_OD_PU = {\ + .pin = MCU_GPIO_PORT##port_n(pin_n),\ + .hal_init = {\ + .Pin = 1 << (pin_n), \ + .Mode = GPIO_MODE_AF_OD, \ + .Pull = GPIO_PULLUP, \ + .Speed = GPIO_SPEED_FREQ_VERY_HIGH, \ + .Alternate = af, \ + }\ +};\ +static stm32_pin_cfg_t const P##port_n##pin_n##_##pf##_OD_PU __unused = &_P##port_n##pin_n##_##pf##_OD_PU; + +#define STM32_PIN_DEF(port_n, pin_n, pin_mode) \ +const struct stm32_pin_cfg _P##port_n##pin_n##_##pin_mode = {\ + .pin = MCU_GPIO_PORT##port_n(pin_n),\ + .hal_init = {\ + .Pin = 1 << (pin_n), \ + .Mode = GPIO_MODE_##pin_mode, \ + .Pull = GPIO_NOPULL, \ + .Speed = GPIO_SPEED_FREQ_VERY_HIGH, \ + }\ +};\ +const stm32_pin_t P##port_n##pin_n##_##pin_mode __unused = &_P##port_n##pin_n##_##pin_mode; + +#include + +void +stm32_pin_config(stm32_pin_cfg_t cfg) +{ + if (cfg) { + hal_gpio_init_stm(cfg->pin, (GPIO_InitTypeDef *)&cfg->hal_init); + } +} + +void +stm32_pin_write(stm32_pin_cfg_t cfg, uint8_t val) +{ + if (cfg) { + hal_gpio_write(cfg->pin, val); + } +} + +uint8_t +stm32_pin_read(stm32_pin_cfg_t cfg) +{ + return cfg ? hal_gpio_read(cfg->pin) : 0; +} + +void +stm32_pin_pulse(hal_gpio_pin_t pin) +{ + hal_gpio_write(pin, 1); + hal_gpio_write(pin, 0); +} + +void +stm32_pin_pulse_n(hal_gpio_pin_t pin, int pulse_count) +{ + for (int i = 0; i < pulse_count; i++) { + stm32_pin_pulse(pin); + } +} diff --git a/hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c b/hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c new file mode 100644 index 0000000000..d4ea96004e --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/src/system_stm32h5xx.c @@ -0,0 +1,403 @@ +/** + ****************************************************************************** + * @file system_stm32h5xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 64000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 64000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL1_N | 129 + *----------------------------------------------------------------------------- + * PLL1_P | 2 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL1_FRACN | 0 + *----------------------------------------------------------------------------- + * PLL2_SRC | No clock + *----------------------------------------------------------------------------- + * PLL2_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL2_N | 129 + *----------------------------------------------------------------------------- + * PLL2_P | 2 + *----------------------------------------------------------------------------- + * PLL2_Q | 2 + *----------------------------------------------------------------------------- + * PLL2_R | 2 + *----------------------------------------------------------------------------- + * PLL2_FRACN | 0 + *----------------------------------------------------------------------------- + * PLL3_SRC | No clock + *----------------------------------------------------------------------------- + * PLL3_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL3_N | 129 + *----------------------------------------------------------------------------- + * PLL3_P | 2 + *----------------------------------------------------------------------------- + * PLL3_Q | 2 + *----------------------------------------------------------------------------- + * PLL3_R | 2 + *----------------------------------------------------------------------------- + * PLL3_FRACN | 0 + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32H5xx_system + * @{ + */ + +/** @addtogroup STM32H5xx_System_Private_Includes + * @{ + */ + +#include "stm32h5xx.h" + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Defines + * @{ + */ + +#if !defined (HSE_VALUE) + #define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + uint32_t reg_opsr; + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit while preserving the current HSIDIV value*/ + RCC->CR = (RCC->CR & RCC_CR_HSIDIV_Msk) | RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + + /* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */ +#if defined(RCC_CR_PLL3ON) + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIKERON | \ + RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); +#else + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIKERON | \ + RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON); +#endif + + /* Reset PLLxCFGR register */ + RCC->PLL1CFGR = 0U; + RCC->PLL2CFGR = 0U; +#if defined(RCC_CR_PLL3ON) + RCC->PLL3CFGR = 0U; +#endif /* RCC_CR_PLL3ON */ + + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280U; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000U; + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280U; + /* Reset PLL2FRACR register */ + RCC->PLL2FRACR = 0x00000000U; +#if defined(RCC_CR_PLL3ON) + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280U; + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000U; +#endif /* RCC_CR_PLL3ON */ + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + + /* Configure the Vector Table location add offset address ------------------*/ + #ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + #else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif /* VECT_TAB_SRAM */ + + /* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */ + reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP; + if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1))) + { + /* Check FLASH Option Control Register access */ + if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte registers programming */ + FLASH->OPTKEYR = 0x08192A3BU; + FLASH->OPTKEYR = 0x4C5D6E7FU; + } + /* Launch the option bytes change operation */ + FLASH->OPTCR |= FLASH_OPTCR_OPTSTART; + + /* Lock the FLASH Option Control Register access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + } +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + float_t fracn1, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case 0x00UL: /* HSI used as system clock source */ + SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case 0x08UL: /* CSI used as system clock source */ + SystemCoreClock = CSI_VALUE; + break; + + case 0x10UL: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + + case 0x18UL: /* PLL1 used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case 0x01UL: /* HSI used as PLL clock source */ + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x02UL: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x03UL: /* HSE used as PLL clock source */ + pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: /* No clock sent to PLL*/ + pllvco = (float_t) 0U; + break; + } + + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ; + SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/hw/mcu/stm/stm32h5xx/syscfg.yml b/hw/mcu/stm/stm32h5xx/syscfg.yml new file mode 100644 index 0000000000..2a647af1b2 --- /dev/null +++ b/hw/mcu/stm/stm32h5xx/syscfg.yml @@ -0,0 +1,294 @@ +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + MCU_FLASH_MIN_WRITE_SIZE: + description: > + Specifies the required alignment for internal flash writes. + Used internally by the newt tool. + value: 16 + + MCU_STM32H5: + description: MCUs are of STM32H5xx family + value: 1 + MCU_TARGET: + description: Specifies target MCU, shall be set by BSP. + value: + restrictions: $notnull + choices: + - STM32H503 + - STM32H523 + - STM32H533 + - STM32H562 + - STM32H563 + - STM32H573 + + STM32_CLOCK_VOLTAGESCALING_CONFIG: + description: Voltage scale + value: 0 + + STM32_CLOCK_LSI: + description: Enable low-speed internal clock source + value: 1 + + STM32_CLOCK_LSE: + description: Enable low-speed external clock source (aka RTC xtal) + value: 0 + + STM32_CLOCK_LSE_BYPASS: + description: 0 for 32768 xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSE: + description: Enable high-speed external clock source + value: 0 + + STM32_CLOCK_HSE_BYPASS: + description: 0 for xtal; 1 for input clock + value: 0 + + STM32_CLOCK_HSI: + description: Enable high-speed internal clock source + value: 1 + + STM32_CLOCK_HSIDIV: + description: HSI divider LL_RCC_HSI_DIV_x where x=(1,2,4,8) + value: LL_RCC_HSI_DIV_1 + + STM32_CLOCK_HSI_CALIBRATION: + description: HSI calibration value + value: 'RCC_HSICALIBRATION_DEFAULT' + + STM32_CLOCK_HSI48: + description: Enable high-speed 48MHz internal clock source + value: 1 + + STM32_CLOCK_USBSEL: + description: > + Select USB clock source. + 0 - disabled + Other acceptable values + RCC_USBCLKSOURCE_PLL1Q, RCC_USBCLKSOURCE_PLL2Q, RCC_USBCLKSOURCE_PLL3Q, RCC_USBCLKSOURCE_HSI48 + value: RCC_USBCLKSOURCE_HSI48 + STM32_CLOCK_SYSCLK_SOURCE: + description: > + System clock selection (LL_RCC_SYS_CLKSOURCE_HSI, LL_RCC_SYS_CLKSOURCE_CSI, LL_RCC_SYS_CLKSOURCE_HSE + LL_RCC_SYS_CLKSOURCE_PLL1) + value: LL_RCC_SYS_CLKSOURCE_HSI + STM32_CLOCK_PLL_PLLM: + description: PLL config M parameter + value: 0 + + STM32_CLOCK_PLL_PLLN: + description: PLL config N parameter + value: 0 + + STM32_CLOCK_PLL_PLLP: + description: PLL config P parameter + value: 0 + + STM32_CLOCK_PLL_PLLQ: + description: PLL config Q parameter + value: 0 + + STM32_CLOCK_PLL_PLLR: + description: PLL config R parameter + value: 0 + + STM32_CLOCK_PLL1: + description: Enable PLL1 + value: 0 + + STM32_CLOCK_PLL1_SOURCE: + description: PLL1 source + value: LL_RCC_PLL1SOURCE_HSI + + STM32_CLOCK_PLL1_PLLM: + description: PLL1 config M parameter + value: 1 + + STM32_CLOCK_PLL1_PLLN: + description: PLL1 config N parameter + value: 0 + + STM32_CLOCK_PLL1_PLLFRACN: + description: PLL1FRACN parameter + value: 0 + + STM32_CLOCK_PLL1_PLLP: + description: PLL1 config P parameter + value: 0 + + STM32_CLOCK_PLL1_PLLQ: + description: PLL1 config Q parameter + value: 0 + + STM32_CLOCK_PLL1_PLLR: + description: PLL1 config R parameter + value: 0 + + STM32_CLOCK_PLL1_RGE: + description: PLL input frequency range + value: RCC_PLL1_VCIRANGE_0 + + STM32_CLOCK_PLL2: + description: Enable PLL2 + value: 0 + + STM32_CLOCK_PLL2_SOURCE: + description: PLL2 source + value: LL_RCC_PLL2SOURCE_HSI + + STM32_CLOCK_PLL2_PLLM: + description: PLL2 config M parameter + value: 1 + + STM32_CLOCK_PLL2_PLLN: + description: PLL2 config N parameter + value: 0 + + STM32_CLOCK_PLL2_PLLFRACN: + description: PLL2FRACN parameter + value: 0 + + STM32_CLOCK_PLL2_PLLP: + description: PLL2 config P parameter + value: 0 + + STM32_CLOCK_PLL2_PLLQ: + description: PLL2 config Q parameter + value: 0 + + STM32_CLOCK_PLL2_PLLR: + description: PLL2 config R parameter + value: 0 + + STM32_CLOCK_PLL2_RGE: + description: PLL input frequency range + value: 0 + + STM32_CLOCK_PLL3: + description: Enable PLL3 + value: 0 + + STM32_CLOCK_PLL3_SOURCE: + description: PLL3 source + value: LL_RCC_PLL3SOURCE_HSI + + STM32_CLOCK_PLL3_PLLM: + description: PLL3 config M parameter + value: 1 + + STM32_CLOCK_PLL3_PLLN: + description: PLL3 config N parameter + value: 0 + + STM32_CLOCK_PLL3_PLLFRACN: + description: PLL3FRACN parameter + value: 0 + + STM32_CLOCK_PLL3_PLLP: + description: PLL3 config P parameter + value: 0 + + STM32_CLOCK_PLL3_PLLQ: + description: PLL3 config Q parameter + value: 0 + + STM32_CLOCK_PLL3_PLLR: + description: PLL3 config R parameter + value: 0 + + STM32_CLOCK_PLL3_RGE: + description: PLL input frequency range + value: 0 + + STM32_CLOCK_AHB_DIVIDER: + description: AHB prescaler + value: 0 + + STM32_CLOCK_APB1_DIVIDER: + description: APB low-speed prescaler + value: 0 + + STM32_CLOCK_APB2_DIVIDER: + description: APB high-speed prescaler + value: 0 + + STM32_CLOCK_APB3_DIVIDER: + description: APB low-speed prescaler + value: 0 + + STM32_CLOCK_APB4_DIVIDER: + description: APB high-speed prescaler + value: 0 + + STM32_FLASH_LATENCY: + description: Number of wait-states + value: 0 + STM32_FLASH_PROGRAM_DELAY: + description: > + Programmin delay: + FLASH_PROGRAMMING_DELAY_0 for system runnig <= 84 MHz + FLASH_PROGRAMMING_DELAY_1 for system runnig <= 168 MHz + value: FLASH_PROGRAMMING_DELAY_2 + + STM32_ENABLE_ICACHE: + description: Enable instruction caching + value: 1 + + STM32_ENABLE_DCACHE: + description: Enable instruction caching + value: 1 + + STM32_FLASH_PREFETCH_ENABLE: + description: Enable pre-fetch of instructions (when latency > 0) + value: 1 + + STM32_HAL_SPI_HAS_FIFO: + description: This MCU has a SPI with FIFO + value: 1 + + STM32_HAL_I2C_HAS_CLOCKSPEED: + description: This MCU's I2C has no clock speed register (has TIMINGR) + value: 0 + + STM32_HAL_UART_HAS_SR: + description: This MCU's UART uses ISR register (not SR) for status. + value: 0 + + MCU_FLASH_ERASED_VAL: + description: Value read from erased flash. + value: 0xff + +syscfg.vals: + MCU_RAM_START: 0x20000000 + +syscfg.vals.'MCU_TARGET=="STM32H503"': + MCU_RAM_SIZE: 0x8000 +syscfg.vals.'MCU_TARGET=="STM32H523"': + MCU_RAM_SIZE: 0x2B000 +syscfg.vals.'MCU_TARGET=="STM32H533"': + MCU_RAM_SIZE: 0x2B000 +syscfg.vals.'MCU_TARGET=="STM32H562"': + MCU_RAM_SIZE: 0xA0000 +syscfg.vals.'MCU_TARGET=="STM32H563"': + MCU_RAM_SIZE: 0xA0000 + +syscfg.vals.STM32_CLOCK_HSI48: + STM32_CLOCK_USBSEL: RCC_USBCLKSOURCE_HSI48 diff --git a/hw/usb/tinyusb/pkg.yml b/hw/usb/tinyusb/pkg.yml index 0f5e941451..2555cb6887 100644 --- a/hw/usb/tinyusb/pkg.yml +++ b/hw/usb/tinyusb/pkg.yml @@ -48,6 +48,8 @@ pkg.deps.MCU_LPC55XX: - "@apache-mynewt-core/hw/usb/tinyusb/lpc55" pkg.deps.MCU_STM32F4: - "@apache-mynewt-core/hw/usb/tinyusb/synopsys" +pkg.deps.MCU_STM32H5: + - "@apache-mynewt-core/hw/usb/tinyusb/stm32_fsdev/stm32h5" pkg.deps.MCU_STM32H7: - "@apache-mynewt-core/hw/usb/tinyusb/synopsys" pkg.deps.MCU_STM32F7: diff --git a/hw/usb/tinyusb/stm32_fsdev/stm32h5/include/tusb_hw.h b/hw/usb/tinyusb/stm32_fsdev/stm32h5/include/tusb_hw.h new file mode 100644 index 0000000000..61df1fba73 --- /dev/null +++ b/hw/usb/tinyusb/stm32_fsdev/stm32h5/include/tusb_hw.h @@ -0,0 +1,89 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#ifndef __TUSB_HW_H__ +#define __TUSB_HW_H__ + +#define CFG_TUSB_MCU OPT_MCU_STM32H5 + +#include + +#define CFG_TUSB_RHPORT0_SPEED OPT_MODE_FULL_SPEED + +#if defined(MYNEWT_VAL_USBD_CDC_NOTIFY_EP) +#define USBD_CDC_NOTIFY_EP MYNEWT_VAL(USBD_CDC_NOTIFY_EP) +#else +#define USBD_CDC_NOTIFY_EP 0x81 +#endif + +#if defined(MYNEWT_VAL_USBD_CDC_NOTIFY_EP_SIZE) +#define USBD_CDC_NOTIFY_EP_SIZE MYNEWT_VAL(USBD_CDC_NOTIFY_EP_SIZE) +#else +#define USBD_CDC_NOTIFY_EP_SIZE 0x08 +#endif + +#if defined(MYNEWT_VAL_USBD_CDC_DATA_OUT_EP) +#define USBD_CDC_DATA_OUT_EP MYNEWT_VAL(USBD_CDC_DATA_OUT_EP) +#else +#define USBD_CDC_DATA_OUT_EP 0x01 +#endif + +#if defined(MYNEWT_VAL_USBD_CDC_DATA_IN_EP) +#define USBD_CDC_DATA_IN_EP MYNEWT_VAL(USBD_CDC_DATA_IN_EP) +#else +#define USBD_CDC_DATA_IN_EP 0x82 +#endif + +#if defined(MYNEWT_VAL_USBD_CDC_DATA_EP_SIZE) +#define USBD_CDC_DATA_EP_SIZE MYNEWT_VAL(USBD_CDC_DATA_EP_SIZE) +#else +#define USBD_CDC_DATA_EP_SIZE 0x40 +#endif + +#if defined(MYNEWT_VAL_USBD_HID_REPORT_EP) +#define USBD_HID_REPORT_EP MYNEWT_VAL(USBD_HID_REPORT_EP) +#else +#define USBD_HID_REPORT_EP 0x83 +#endif + +#if defined(MYNEWT_VAL_USBD_HID_REPORT_EP_SIZE) +#define USBD_HID_REPORT_EP_SIZE MYNEWT_VAL(USBD_HID_REPORT_EP_SIZE) +#else +#define USBD_HID_REPORT_EP_SIZE 0x10 +#endif + +#if defined(MYNEWT_VAL_USBD_HID_REPORT_EP_INTERVAL) +#define USBD_HID_REPORT_EP_INTERVAL MYNEWT_VAL(USBD_HID_REPORT_EP_INTERVAL) +#else +#define USBD_HID_REPORT_EP_INTERVAL 10 +#endif + +#if defined(MYNEWT_VAL_USBD_MSC_DATA_IN_EP) +#define USBD_MSC_DATA_IN_EP MYNEWT_VAL(USBD_MSC_DATA_IN_EP) +#else +#define USBD_MSC_DATA_IN_EP 0x86 +#endif + +#if defined(MYNEWT_VAL_USBD_MSC_DATA_OUT_EP) +#define USBD_MSC_DATA_OUT_EP MYNEWT_VAL(USBD_MSC_DATA_OUT_EP) +#else +#define USBD_MSC_DATA_OUT_EP 0x06 +#endif + +#endif diff --git a/hw/usb/tinyusb/stm32_fsdev/stm32h5/pkg.yml b/hw/usb/tinyusb/stm32_fsdev/stm32h5/pkg.yml new file mode 100644 index 0000000000..7e314a2e07 --- /dev/null +++ b/hw/usb/tinyusb/stm32_fsdev/stm32h5/pkg.yml @@ -0,0 +1,33 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +pkg.name: hw/usb/tinyusb/stm32_fsdev/stm32h5 +pkg.description: Hardware initialization for TinyUSB +pkg.author: "Apache Mynewt " +pkg.homepage: "http://mynewt.apache.org/" +pkg.keywords: + - usb + - tinyusb + +pkg.apis: + - TINYUSB_HW_INIT + +pkg.deps: + - "@apache-mynewt-core/kernel/os" + - "@apache-mynewt-core/hw/usb/tinyusb" diff --git a/hw/usb/tinyusb/stm32_fsdev/stm32h5/src/stm32_fsdev.c b/hw/usb/tinyusb/stm32_fsdev/stm32h5/src/stm32_fsdev.c new file mode 100644 index 0000000000..6be1a0b626 --- /dev/null +++ b/hw/usb/tinyusb/stm32_fsdev/stm32h5/src/stm32_fsdev.c @@ -0,0 +1,60 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +#include +#include + +#include + +#include +#include +#include +#include + +static void +USB_IRQHandler(void) +{ + tud_int_handler(0); +} + +void +tinyusb_hardware_init(void) +{ + /* TinyUSB provides interrupt handler, here it is setup the mynewt way */ + NVIC_SetVector(USB_DRD_FS_IRQn, (uint32_t)USB_IRQHandler); + NVIC_SetPriority(USB_DRD_FS_IRQn, 2); + + if (MYNEWT_VAL_CHOICE(USB_CLOCK_SOURCE, hsi48_ker_ck)) { + RCC->CCIPR4 = RCC->CCIPR4 | RCC_USBCLKSOURCE_HSI48; + } else if (MYNEWT_VAL_CHOICE(USB_CLOCK_SOURCE, pll1_q_ck)) { + RCC->CCIPR4 = (RCC->CCIPR4 & ~RCC_CCIPR4_USBSEL) | RCC_USBCLKSOURCE_PLL1Q; + } else if (MYNEWT_VAL_CHOICE(USB_CLOCK_SOURCE, pll3_q_ck)) { + RCC->CCIPR4 = (RCC->CCIPR4 & ~RCC_CCIPR4_USBSEL) | RCC_USBCLKSOURCE_PLL3Q; + } + + /* + * Enable USB clock + */ + __HAL_RCC_USB_CLK_ENABLE(); + +#if defined(PWR_USBSCR_USB33DEN) + /* Enable VDDUSB */ + HAL_PWREx_EnableVddUSB(); +#endif +} diff --git a/hw/usb/tinyusb/stm32_fsdev/stm32h5/syscfg.yml b/hw/usb/tinyusb/stm32_fsdev/stm32h5/syscfg.yml new file mode 100644 index 0000000000..51a52af1d3 --- /dev/null +++ b/hw/usb/tinyusb/stm32_fsdev/stm32h5/syscfg.yml @@ -0,0 +1,36 @@ +# +# Licensed to the Apache Software Foundation (ASF) under one +# or more contributor license agreements. See the NOTICE file +# distributed with this work for additional information +# regarding copyright ownership. The ASF licenses this file +# to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance +# with the License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, +# software distributed under the License is distributed on an +# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY +# KIND, either express or implied. See the License for the +# specific language governing permissions and limitations +# under the License. +# + +syscfg.defs: + USB_DP_HAS_EXTERNAL_PULL_UP: + description: > + Set this to 1 if hardware has external pull up resistor. + Setting this changes DP pin to 0 at startup for a fraction + then device is discovered by host. + value: 0 + + USB_CLOCK_SOURCE: + description: > + Source of USB clock. + choices: + - pll1_q_ck + - pll3_q_ck + - hsi48_ker_ck + value: hsi48_ker_ck +